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edd2d250 |
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22-Apr-2024 |
Duanqiang Wen <duanqiangwen@net-swift.com> |
Revert "net: txgbe: fix clk_name exceed MAX_DEV_ID limits" This reverts commit e30cef001da259e8df354b813015d0e5acc08740. commit 99f4570cfba1 ("clkdev: Update clkdev id usage to allow for longer names") can fix clk_name exceed MAX_DEV_ID limits, so this commit is meaningless. Signed-off-by: Duanqiang Wen <duanqiangwen@net-swift.com> Reviewed-by: Jacob Keller <jacob.e.keller@intel.com> Link: https://lore.kernel.org/r/20240422084109.3201-2-duanqiangwen@net-swift.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
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8d6bf83f |
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22-Apr-2024 |
Duanqiang Wen <duanqiangwen@net-swift.com> |
Revert "net: txgbe: fix i2c dev name cannot match clkdev" This reverts commit c644920ce9220d83e070f575a4df711741c07f07. when register i2c dev, txgbe shorten "i2c_designware" to "i2c_dw", will cause this i2c dev can't match platfom driver i2c_designware_platform. Signed-off-by: Duanqiang Wen <duanqiangwen@net-swift.com> Reviewed-by: Jacob Keller <jacob.e.keller@intel.com> Link: https://lore.kernel.org/r/20240422084109.3201-1-duanqiangwen@net-swift.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
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c644920c |
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01-Apr-2024 |
Duanqiang Wen <duanqiangwen@net-swift.com> |
net: txgbe: fix i2c dev name cannot match clkdev txgbe clkdev shortened clk_name, so i2c_dev info_name also need to shorten. Otherwise, i2c_dev cannot initialize clock. Fixes: e30cef001da2 ("net: txgbe: fix clk_name exceed MAX_DEV_ID limits") Signed-off-by: Duanqiang Wen <duanqiangwen@net-swift.com> Link: https://lore.kernel.org/r/20240402021843.126192-1-duanqiangwen@net-swift.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
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e30cef00 |
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13-Mar-2024 |
Duanqiang Wen <duanqiangwen@net-swift.com> |
net: txgbe: fix clk_name exceed MAX_DEV_ID limits txgbe register clk which name is i2c_designware.pci_dev_id(), clk_name will be stored in clk_lookup_alloc. If PCIe bus number is larger than 0x39, clk_name size will be larger than 20 bytes. It exceeds clk_lookup_alloc MAX_DEV_ID limits. So the driver shortened clk_name. Fixes: b63f20485e43 ("net: txgbe: Register fixed rate clock") Signed-off-by: Duanqiang Wen <duanqiangwen@net-swift.com> Reviewed-by: Michal Kubiak <michal.kubiak@intel.com> Link: https://lore.kernel.org/r/20240313080634.459523-1-duanqiangwen@net-swift.com Signed-off-by: Paolo Abeni <pabeni@redhat.com>
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0e71862a |
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01-Mar-2024 |
Jiawen Wu <jiawenwu@trustnetic.com> |
net: txgbe: fix to clear interrupt status after handling IRQ GPIO EOI is not set to clear interrupt status after handling the interrupt. It should be done in irq_chip->irq_ack, but this function is not called in handle_nested_irq(). So executing function txgbe_gpio_irq_ack() manually in txgbe_gpio_irq_handler(). Fixes: aefd013624a1 ("net: txgbe: use irq_domain for interrupt controller") Signed-off-by: Jiawen Wu <jiawenwu@trustnetic.com> Link: https://lore.kernel.org/r/20240301092956.18544-2-jiawenwu@trustnetic.com Signed-off-by: Paolo Abeni <pabeni@redhat.com>
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b4a2496c |
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01-Mar-2024 |
Jiawen Wu <jiawenwu@trustnetic.com> |
net: txgbe: fix GPIO interrupt blocking The register of GPIO interrupt status is masked before MAC IRQ is enabled. This is because of hardware deficiency. So manually clear the interrupt status before using them. Otherwise, GPIO interrupts will never be reported again. There is a workaround for clearing interrupts to set GPIO EOI in txgbe_up_complete(). Fixes: aefd013624a1 ("net: txgbe: use irq_domain for interrupt controller") Signed-off-by: Jiawen Wu <jiawenwu@trustnetic.com> Link: https://lore.kernel.org/r/20240301092956.18544-1-jiawenwu@trustnetic.com Signed-off-by: Paolo Abeni <pabeni@redhat.com>
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aefd0136 |
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24-Jan-2024 |
Jiawen Wu <jiawenwu@trustnetic.com> |
net: txgbe: use irq_domain for interrupt controller In the current interrupt controller, the MAC interrupt acts as the parent interrupt in the GPIO IRQ chip. But when the number of Rx/Tx ring changes, the PCI IRQ vector needs to be reallocated. Then this interrupt controller would be corrupted. So use irq_domain structure to avoid the above problem. Signed-off-by: Jiawen Wu <jiawenwu@trustnetic.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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937d46ec |
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02-Jan-2024 |
Jiawen Wu <jiawenwu@trustnetic.com> |
net: wangxun: add ethtool_ops for channel number Add support to get RX/TX queue number with ethtool -l, and set RX/TX queue number with ethtool -L. Since interrupts need to be rescheduled, adjust the allocation of msix enties. Signed-off-by: Jiawen Wu <jiawenwu@trustnetic.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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2fe2ca09 |
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02-Jan-2024 |
Jiawen Wu <jiawenwu@trustnetic.com> |
net: wangxun: add flow control support Add support to set pause params with ethtool -A and get pause params with ethtool -a, for ethernet driver txgbe and ngbe. Signed-off-by: Jiawen Wu <jiawenwu@trustnetic.com> Reviewed-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk> Signed-off-by: David S. Miller <davem@davemloft.net>
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4491c602 |
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02-Jan-2024 |
Jiawen Wu <jiawenwu@trustnetic.com> |
net: txgbe: use phylink bits added in libwx Convert txgbe to use phylink and phylink_config added in libwx. Signed-off-by: Jiawen Wu <jiawenwu@trustnetic.com> Reviewed-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk> Signed-off-by: David S. Miller <davem@davemloft.net>
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f5575240 |
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11-Sep-2023 |
Jiawen Wu <jiawenwu@trustnetic.com> |
net: wangxun: move MDIO bus implementation to the library Move similar code of accessing MDIO bus from txgbe/ngbe to libwx. Signed-off-by: Jiawen Wu <jiawenwu@trustnetic.com> Reviewed-by: Simon Horman <horms@kernel.org> Link: https://lore.kernel.org/r/20230912031424.721386-1-jiawenwu@trustnetic.com Signed-off-by: Paolo Abeni <pabeni@redhat.com>
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02b2a6f9 |
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23-Aug-2023 |
Jiawen Wu <jiawenwu@trustnetic.com> |
net: txgbe: support copper NIC with external PHY Wangxun SP chip supports to connect with external PHY (marvell 88x3310), which links to 10GBASE-T/1000BASE-T/100BASE-T. Add the identification of media types from subsystem device IDs. For sp_media_copper, register mdio bus for the external PHY. Signed-off-by: Jiawen Wu <jiawenwu@trustnetic.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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a4414dd1 |
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23-Aug-2023 |
Jiawen Wu <jiawenwu@trustnetic.com> |
net: txgbe: support switching mode to 1000BASE-X and SGMII Disable data path before PCS VR reset while switching PCS mode, to prevent the blocking of data path. Enable AN interrupt for CL37 auto-negotiation. Signed-off-by: Jiawen Wu <jiawenwu@trustnetic.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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d8c21ef7 |
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07-Aug-2023 |
Xiongfeng Wang <wangxiongfeng2@huawei.com> |
net: txgbe: Use pci_dev_id() to simplify the code PCI core API pci_dev_id() can be used to get the BDF number for a pci device. We don't need to compose it manually. Use pci_dev_id() to simplify the code a little bit. Signed-off-by: Xiongfeng Wang <wangxiongfeng2@huawei.com> Reviewed-by: Yang Yingliang <yangyingliang@huawei.com> Reviewed-by: Simon Horman <horms@kernel.org> Link: https://lore.kernel.org/r/20230808024931.147048-1-wangxiongfeng2@huawei.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
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08f08f93 |
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06-Jun-2023 |
Jiawen Wu <jiawenwu@trustnetic.com> |
net: txgbe: Support phylink MAC layer Add phylink support to Wangxun 10Gb Ethernet controller for the 10GBASE-R interface. Signed-off-by: Jiawen Wu <jiawenwu@trustnetic.com> Reviewed-by: Maciej Fijalkowski <maciej.fijalkowski@intel.com> Signed-off-by: Paolo Abeni <pabeni@redhat.com>
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854cace6 |
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06-Jun-2023 |
Jiawen Wu <jiawenwu@trustnetic.com> |
net: txgbe: Implement phylink pcs Register MDIO bus for PCS layer to use Synopsys designware XPCS, support 10GBASE-R interface to the controller. Signed-off-by: Jiawen Wu <jiawenwu@trustnetic.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Reviewed-by: Maciej Fijalkowski <maciej.fijalkowski@intel.com> Signed-off-by: Paolo Abeni <pabeni@redhat.com>
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b83c3731 |
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06-Jun-2023 |
Jiawen Wu <jiawenwu@trustnetic.com> |
net: txgbe: Support GPIO to SFP socket Register GPIO chip and handle GPIO IRQ for SFP socket. Signed-off-by: Jiawen Wu <jiawenwu@trustnetic.com> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Maciej Fijalkowski <maciej.fijalkowski@intel.com> Signed-off-by: Paolo Abeni <pabeni@redhat.com>
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04d94236 |
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06-Jun-2023 |
Jiawen Wu <jiawenwu@trustnetic.com> |
net: txgbe: Add SFP module identify Register SFP platform device to get modules information. Signed-off-by: Jiawen Wu <jiawenwu@trustnetic.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Reviewed-by: Piotr Raczynski <piotr.raczynski@intel.com> Reviewed-by: Maciej Fijalkowski <maciej.fijalkowski@intel.com> Signed-off-by: Paolo Abeni <pabeni@redhat.com>
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c625e725 |
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06-Jun-2023 |
Jiawen Wu <jiawenwu@trustnetic.com> |
net: txgbe: Register I2C platform device Register the platform device to use Designware I2C bus master driver. Use regmap to read/write I2C device region from given base offset. Signed-off-by: Jiawen Wu <jiawenwu@trustnetic.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Reviewed-by: Piotr Raczynski <piotr.raczynski@intel.com> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Maciej Fijalkowski <maciej.fijalkowski@intel.com> Signed-off-by: Paolo Abeni <pabeni@redhat.com>
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b63f2048 |
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06-Jun-2023 |
Jiawen Wu <jiawenwu@trustnetic.com> |
net: txgbe: Register fixed rate clock In order for I2C to be able to work in standard mode, register a fixed rate clock for each I2C device. Signed-off-by: Jiawen Wu <jiawenwu@trustnetic.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Reviewed-by: Maciej Fijalkowski <maciej.fijalkowski@intel.com> Signed-off-by: Paolo Abeni <pabeni@redhat.com>
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c3e382ad |
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06-Jun-2023 |
Jiawen Wu <jiawenwu@trustnetic.com> |
net: txgbe: Add software nodes to support phylink Register software nodes for GPIO, I2C, SFP and PHYLINK. Define the device properties. Signed-off-by: Jiawen Wu <jiawenwu@trustnetic.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Reviewed-by: Piotr Raczynski <piotr.raczynski@intel.com> Reviewed-by: Maciej Fijalkowski <maciej.fijalkowski@intel.com> Signed-off-by: Paolo Abeni <pabeni@redhat.com>
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