mmc/host/sdhci-msm.c

263 	struct clk *bus_clk;	/* SDHC bus voter clock */
341 	 * The SDHC requires internal clock frequency to be double the
342 	 * actual clock that will be set for DDR mode. The controller
343 	 * uses the faster clock(100/400MHz) for some of its parts and
344 	 * send the actual required clock (50/200MHz) to the card.
355 					    unsigned int clock)
367 	desired_rate = clock * mult;
370 		pr_err("%s: Failed to set clock at rate %u at timing %d\n",
376 	 * Qualcomm clock drivers by default round clock _up_ if they can't
389 	pr_debug("%s: Setting clock at rate %lu at timing %d\n",
450 	 * Write the selected DLL clock output phase (0 ... 15)
483  * DLL clock output phases that can be used as sampling
488  * selected DLL clock output phase.
600 	if (host->clock <= 112000000)
602 	else if (host->clock <= 125000000)
604 	else if (host->clock <= 137000000)
606 	else if (host->clock <= 150000000)
608 	else if (host->clock <= 162000000)
610 	else if (host->clock <= 175000000)
612 	else if (host->clock <= 187000000)
614 	else if (host->clock <= 200000000)
641 	 * Make sure that clock is always enabled when DLL
643 	 * turn off the clock.
690 			mclk_freq = DIV_ROUND_CLOSEST_ULL((host->clock * 8),
693 			mclk_freq = DIV_ROUND_CLOSEST_ULL((host->clock * 4),
703 		/* wait for 5us before enabling DLL clock */
829 	/* Select the divided clock (free running MCLK/2) */
885  * correct input clock for DLL depending on the mode.
887  * HS400 - divided clock (free running MCLK/2)
1129 	 * if clock frequency is greater than 100MHz in these modes.
1131 	if (host->clock <= CORE_FREQ_100MHZ ||
1218 		msm_set_clock_rate_for_bus_mode(host, ios.clock);
1295  * DLL operation is only needed for clock > 100MHz. For clock <= 100MHz
1296  * fixed feedback clock is used.
1304 	if (host->clock > CORE_FREQ_100MHZ &&
1352 	 * When clock frequency is less than 100MHz, the feedback clock must be
1354 	 * provide feedback clock, the mode selection can be any value less
1357 	if (host->clock <= CORE_FREQ_100MHZ) {
1363 		 * DLL is not required for clock <= 100MHz
1380 		 * when the clock frequency is set back to 400MHz.
1385 	dev_dbg(mmc_dev(mmc), "%s: clock=%u uhs=%u ctrl_2=0x%x\n",
1386 		mmc_hostname(host->mmc), host->clock, uhs, ctrl_2);
1759  * __sdhci_msm_set_clock - sdhci_msm clock control.
1763  * instead directly control the GCC clock as per
1766 static void __sdhci_msm_set_clock(struct sdhci_host *host, unsigned int clock)
1772 	if (clock == 0)
1776 	 * MSM controller do not use clock divider.
1778 	 * clock with no divider value programmed.
1785 static void sdhci_msm_set_clock(struct sdhci_host *host, unsigned int clock)
1790 	if (!clock) {
1797 	msm_set_clock_rate_for_bus_mode(host, clock);
1799 	__sdhci_msm_set_clock(host, clock);
1979 	 * using 4 * MCLK * 2^(count + 13). where MCLK = 1 / host->clock.
1981 	if (cmd && cmd->data && host->clock > 400000 &&
1982 	    host->clock <= 50000000 &&
1983 	    ((1 << (count + start)) > (10 * host->clock)))
2384 	 * is at least 3-4 sleep clock (32.7KHz) cycles, which comes to
2451 	/* Setup SDCC bus voter clock. */
2463 	/* Setup main peripheral bus clock */
2472 	/* Setup SDC MMC clock */
2497 	/* Vote for maximum clock rate for maximum performance */
2500 		dev_warn(&pdev->dev, "core clock boost failed\n");
2518 	 * xo clock is needed for FLL feature of cm_dll.
2519 	 * In case if xo clock is not mentioned in DT, warn and proceed.
2724 	 * Whenever core-clock is gated dynamically, it's needed to
2725 	 * restore the SDR DLL settings when the clock is ungated.