Searched refs:CSR_WRITE_2 (Results 1 - 25 of 41) sorted by path

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/haiku/src/add-ons/kernel/drivers/network/wlan/aironetwifi/dev/an/
H A Dif_an.c341 CSR_WRITE_2(sc, AN_INT_EN(sc->mpi350), 0);
342 CSR_WRITE_2(sc, AN_EVENT_ACK(sc->mpi350), 0xFFFF);
1206 CSR_WRITE_2(sc, AN_INT_EN(sc->mpi350), 0);
1209 CSR_WRITE_2(sc, AN_EVENT_ACK(sc->mpi350), ~AN_INTRS(sc->mpi350));
1212 CSR_WRITE_2(sc, AN_EVENT_ACK(sc->mpi350), AN_EV_MIC);
1221 CSR_WRITE_2(sc, AN_EVENT_ACK(sc->mpi350), AN_EV_LINKSTAT);
1226 CSR_WRITE_2(sc, AN_EVENT_ACK(sc->mpi350), AN_EV_RX);
1231 CSR_WRITE_2(sc, AN_EVENT_ACK(sc->mpi350), AN_EV_TX_CPY);
1236 CSR_WRITE_2(sc, AN_EVENT_ACK(sc->mpi350), AN_EV_TX);
1241 CSR_WRITE_2(s
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H A Dif_anreg.h50 #define CSR_WRITE_2(sc, reg, val) bus_write_2(sc->port_res, reg, val) macro
/haiku/src/add-ons/kernel/drivers/network/wlan/iprowifi2100/dev/ipw/
H A Dif_ipwreg.h339 #define CSR_WRITE_2(sc, reg, val) \ macro
367 CSR_WRITE_2((sc), IPW_CSR_INDIRECT_DATA, (val)); \
/haiku/src/add-ons/kernel/drivers/network/wlan/iprowifi2200/dev/iwi/
H A Dif_iwireg.h589 #define CSR_WRITE_2(sc, reg, val) \ macro
609 CSR_WRITE_2((sc), IWI_CSR_INDIRECT_DATA, (val)); \
/haiku/src/add-ons/kernel/drivers/network/ether/3com/dev/xl/
H A Dif_xl.c411 CSR_WRITE_2(sc, XL_W4_PHY_MGMT, val);
576 CSR_WRITE_2(sc, XL_W0_EE_CMD,
579 CSR_WRITE_2(sc, XL_W0_EE_CMD,
648 CSR_WRITE_2(sc, XL_COMMAND, rxfilt | XL_CMD_RX_SET_FILT);
689 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_HASH | i);
711 CSR_WRITE_2(sc, XL_COMMAND,
720 CSR_WRITE_2(sc, XL_COMMAND, rxfilt | XL_CMD_RX_SET_FILT);
741 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP);
826 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_START);
828 CSR_WRITE_2(s
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H A Dif_xlreg.h659 #define CSR_WRITE_2(sc, reg, val) \ macro
677 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_WINSEL | x); \
/haiku/src/add-ons/kernel/drivers/network/ether/3com/
H A Dglue.c49 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STAT_ENB);
50 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ACK | (status & XL_INTRS));
60 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STAT_ENB | XL_INTRS);
/haiku/src/add-ons/kernel/drivers/network/ether/atheros813x/dev/alc/
H A Dif_alc.c906 CSR_WRITE_2(sc, ALC_GPHY_CFG, GPHY_CFG_SEL_ANA_RESET);
910 CSR_WRITE_2(sc, ALC_GPHY_CFG, GPHY_CFG_EXT_RESET |
1128 CSR_WRITE_2(sc, ALC_GPHY_CFG, GPHY_CFG_EXT_RESET |
1174 CSR_WRITE_2(sc, sc->alc_expcap + PCIER_LINK_CTL,
3004 CSR_WRITE_2(sc, ALC_MBOX_TD_PRI0_PROD_IDX,
3603 CSR_WRITE_2(sc, ALC_MBOX_RD0_PROD_IDX,
H A Dif_alcvar.h264 #define CSR_WRITE_2(_sc, reg, val) \ macro
/haiku/src/add-ons/kernel/drivers/network/ether/atheros81xx/dev/ale/
H A Dif_ale.c411 CSR_WRITE_2(sc, ALE_GPHY_CTRL,
415 CSR_WRITE_2(sc, ALE_GPHY_CTRL,
1512 CSR_WRITE_2(sc, ALE_GPHY_CTRL,
1544 CSR_WRITE_2(sc, ALE_GPHY_CTRL,
2731 CSR_WRITE_2(sc, ALE_INTR_CLR_TIMER, ALE_USECS(1000));
H A Dif_alevar.h233 #define CSR_WRITE_2(_sc, reg, val) \ macro
/haiku/src/add-ons/kernel/drivers/network/ether/attansic_l1/dev/age/
H A Dif_age.c2671 CSR_WRITE_2(sc, AGE_IM_TIMER, AGE_USECS(sc->age_int_mod));
2682 CSR_WRITE_2(sc, AGE_INTR_CLR_TIMER, AGE_USECS(1000));
H A Dif_agevar.h241 #define CSR_WRITE_2(_sc, reg, val) \ macro
/haiku/src/add-ons/kernel/drivers/network/ether/ipro100/dev/fxp/
H A Dif_fxp.c1151 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
1153 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK);
1155 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
1173 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
1187 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
1189 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK);
1191 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
1206 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK);
1210 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
1213 CSR_WRITE_2(s
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H A Dif_fxpvar.h253 #define CSR_WRITE_2(sc, reg, val) bus_write_2(sc->fxp_res[0], reg, val) macro
/haiku/src/add-ons/kernel/drivers/network/ether/marvell_yukon/dev/msk/
H A Dif_msk.c689 CSR_WRITE_2(sc_if->msk_softc,
754 CSR_WRITE_2(sc_if->msk_softc,
822 CSR_WRITE_2(sc_if->msk_softc,
1296 CSR_WRITE_2(sc, B0_CTST, Y2_HW_WOL_ON);
1310 CSR_WRITE_2(sc, MR_ADDR(i, GMAC_LINK_CTRL),
1312 CSR_WRITE_2(sc, MR_ADDR(i, GMAC_LINK_CTRL),
1369 CSR_WRITE_2(sc, B28_Y2_ASF_HCU_CCSR, status);
1373 CSR_WRITE_2(sc, B0_CTST, Y2_ASF_DISABLE);
1378 CSR_WRITE_2(sc, B0_CTST, CS_RST_SET);
1379 CSR_WRITE_2(s
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H A Dif_mskreg.h2127 #define CSR_WRITE_2(sc, reg, val) \ macro
2163 CSR_WRITE_2((sc_if)->msk_softc, (reg), (val))
2170 CSR_WRITE_2((sc), GMAC_REG((port), (reg)), (val))
/haiku/src/add-ons/kernel/drivers/network/ether/pcnet/dev/pcn/
H A Dif_pcn.c226 CSR_WRITE_2(sc, PCN_IO16_RAP, reg);
255 CSR_WRITE_2(sc, PCN_IO16_RAP, reg);
H A Dif_pcnreg.h486 #define CSR_WRITE_2(sc, reg, val) \ macro
/haiku/src/add-ons/kernel/drivers/network/ether/rdc/dev/vte/
H A Dif_vte.c180 CSR_WRITE_2(sc, VTE_MMDIO, MMDIO_READ |
204 CSR_WRITE_2(sc, VTE_MMWD, val);
205 CSR_WRITE_2(sc, VTE_MMDIO, MMDIO_WRITE |
261 CSR_WRITE_2(sc, VTE_MRICR, val);
269 CSR_WRITE_2(sc, VTE_MTICR, val);
1161 CSR_WRITE_2(sc, VTE_TX_POLL, TX_POLL_START);
1257 CSR_WRITE_2(sc, VTE_MCR0, mcr);
1358 CSR_WRITE_2(sc, VTE_MIER, 0);
1379 CSR_WRITE_2(sc, VTE_MIER, VTE_INTRS);
1578 CSR_WRITE_2(s
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H A Dif_vtevar.h151 #define CSR_WRITE_2(_sc, reg, val) \ macro
/haiku/src/add-ons/kernel/drivers/network/ether/rtl8139/dev/rl/
H A Dif_rl.c470 CSR_WRITE_2(sc, rl8139_reg, data);
1217 CSR_WRITE_2(sc, RL_CURRXADDR, cur_rx - 16);
1328 CSR_WRITE_2(sc, RL_CSCFG, RL_CSCFG_LINK_DOWN_OFF_CMD);
1331 CSR_WRITE_2(sc, RL_CSCFG, RL_CSCFG_LINK_DOWN_CMD);
1474 CSR_WRITE_2(sc, RL_ISR, status);
1513 CSR_WRITE_2(sc, RL_IMR, 0);
1515 CSR_WRITE_2(sc, RL_ISR, status);
1539 CSR_WRITE_2(sc, RL_IMR, RL_INTRS);
1751 CSR_WRITE_2(sc, RL_IMR, 0);
1755 CSR_WRITE_2(s
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H A Dif_rlreg.h950 #define CSR_WRITE_2(sc, reg, val) \ macro
972 CSR_WRITE_2(sc, offset, CSR_READ_2(sc, offset) | (val))
975 CSR_WRITE_2(sc, offset, CSR_READ_2(sc, offset) & ~(val))
/haiku/src/add-ons/kernel/drivers/network/ether/rtl8139/
H A Dglue.c25 CSR_WRITE_2(sc, RL_ISR, status);
31 CSR_WRITE_2(sc, RL_IMR, 0);
41 CSR_WRITE_2(sc, RL_IMR, RL_INTRS);
/haiku/src/add-ons/kernel/drivers/network/ether/rtl81xx/dev/re/
H A Dif_re.c613 CSR_WRITE_2(sc, re8139_reg, data);
823 CSR_WRITE_2(sc, RL_ISR, RL_INTRS);
840 CSR_WRITE_2(sc, RL_ISR, 0xFFFF);
852 CSR_WRITE_2(sc, RL_ISR, status);
2542 CSR_WRITE_2(sc, RL_ISR, status);
2571 CSR_WRITE_2(sc, RL_IMR, 0);
2592 CSR_WRITE_2(sc, RL_ISR, status);
2645 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS);
2666 CSR_WRITE_2(sc, RL_IMR, 0);
2674 CSR_WRITE_2(s
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