1221337Sdim/* $FreeBSD: releng/12.0/sys/dev/ipw/if_ipwreg.h 326255 2017-11-27 14:52:40Z pfg $ */ 2221337Sdim 3221337Sdim/*- 4221337Sdim * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 5221337Sdim * 6221337Sdim * Copyright (c) 2004-2006 7221337Sdim * Damien Bergamini <damien.bergamini@free.fr>. All rights reserved. 8221337Sdim * 9221337Sdim * Redistribution and use in source and binary forms, with or without 10221337Sdim * modification, are permitted provided that the following conditions 11221337Sdim * are met: 12221337Sdim * 1. Redistributions of source code must retain the above copyright 13221337Sdim * notice unmodified, this list of conditions, and the following 14221337Sdim * disclaimer. 15221337Sdim * 2. Redistributions in binary form must reproduce the above copyright 16221337Sdim * notice, this list of conditions and the following disclaimer in the 17221337Sdim * documentation and/or other materials provided with the distribution. 18221337Sdim * 19221337Sdim * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 20221337Sdim * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21221337Sdim * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22221337Sdim * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 23221337Sdim * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24221337Sdim * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 25221337Sdim * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26221337Sdim * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27221337Sdim * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28221337Sdim * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29221337Sdim * SUCH DAMAGE. 30221337Sdim */ 31221337Sdim 32221337Sdim#define IPW_NTBD 128 33221337Sdim#define IPW_TBD_SZ (IPW_NTBD * sizeof (struct ipw_bd)) 34221337Sdim#define IPW_NDATA (IPW_NTBD / 2) 35221337Sdim#define IPW_NRBD 128 36221337Sdim#define IPW_RBD_SZ (IPW_NRBD * sizeof (struct ipw_bd)) 37221337Sdim#define IPW_STATUS_SZ (IPW_NRBD * sizeof (struct ipw_status)) 38221337Sdim 39221337Sdim#define IPW_CSR_INTR 0x0008 40221337Sdim#define IPW_CSR_INTR_MASK 0x000c 41221337Sdim#define IPW_CSR_INDIRECT_ADDR 0x0010 42221337Sdim#define IPW_CSR_INDIRECT_DATA 0x0014 43221337Sdim#define IPW_CSR_AUTOINC_ADDR 0x0018 44221337Sdim#define IPW_CSR_AUTOINC_DATA 0x001c 45221337Sdim#define IPW_CSR_RST 0x0020 46224145Sdim#define IPW_CSR_CTL 0x0024 47224145Sdim#define IPW_CSR_IO 0x0030 48224145Sdim#define IPW_CSR_TX_BASE 0x0200 49221337Sdim#define IPW_CSR_TX_SIZE 0x0204 50221337Sdim#define IPW_CSR_RX_BASE 0x0240 51221337Sdim#define IPW_CSR_STATUS_BASE 0x0244 52221337Sdim#define IPW_CSR_RX_SIZE 0x0248 53221337Sdim#define IPW_CSR_TX_READ 0x0280 54221337Sdim#define IPW_CSR_RX_READ 0x02a0 55221337Sdim#define IPW_CSR_TABLE1_BASE 0x0380 56221337Sdim#define IPW_CSR_TABLE2_BASE 0x0384 57221337Sdim#define IPW_CSR_TX_WRITE 0x0f80 58221337Sdim#define IPW_CSR_RX_WRITE 0x0fa0 59221337Sdim 60221337Sdim/* possible flags for register IPW_CSR_INTR */ 61221337Sdim#define IPW_INTR_TX_TRANSFER 0x00000001 62221337Sdim#define IPW_INTR_RX_TRANSFER 0x00000002 63221337Sdim#define IPW_INTR_STATUS_CHANGE 0x00000010 64221337Sdim#define IPW_INTR_COMMAND_DONE 0x00010000 65221337Sdim#define IPW_INTR_FW_INIT_DONE 0x01000000 66221337Sdim#define IPW_INTR_FATAL_ERROR 0x40000000 67221337Sdim#define IPW_INTR_PARITY_ERROR 0x80000000 68221337Sdim 69221337Sdim#define IPW_INTR_MASK \ 70221337Sdim (IPW_INTR_TX_TRANSFER | IPW_INTR_RX_TRANSFER | \ 71221337Sdim IPW_INTR_STATUS_CHANGE | IPW_INTR_COMMAND_DONE | \ 72221337Sdim IPW_INTR_FW_INIT_DONE | IPW_INTR_FATAL_ERROR | \ 73221337Sdim IPW_INTR_PARITY_ERROR) 74224145Sdim 75221337Sdim/* possible flags for register IPW_CSR_RST */ 76221337Sdim#define IPW_RST_PRINCETON_RESET 0x00000001 77224145Sdim#define IPW_RST_SW_RESET 0x00000080 78221337Sdim#define IPW_RST_MASTER_DISABLED 0x00000100 79221337Sdim#define IPW_RST_STOP_MASTER 0x00000200 80221337Sdim 81221337Sdim/* possible flags for register IPW_CSR_CTL */ 82221337Sdim#define IPW_CTL_CLOCK_READY 0x00000001 83221337Sdim#define IPW_CTL_ALLOW_STANDBY 0x00000002 84221337Sdim#define IPW_CTL_INIT 0x00000004 85224145Sdim 86224145Sdim/* possible flags for register IPW_CSR_IO */ 87224145Sdim#define IPW_IO_GPIO1_ENABLE 0x00000008 88224145Sdim#define IPW_IO_GPIO1_MASK 0x0000000c 89221337Sdim#define IPW_IO_GPIO3_MASK 0x000000c0 90221337Sdim#define IPW_IO_LED_OFF 0x00002000 91221337Sdim#define IPW_IO_RADIO_DISABLED 0x00010000 92221337Sdim 93221337Sdim/* state codes sent by fw on IPW_STATUS_CODE_NEWSTATE interrupt */ 94221337Sdim#define IPW_STATE_INITIALIZED 0x0001 95221337Sdim#define IPW_STATE_CC_FOUND 0x0002 /* 802.11d cc received */ 96221337Sdim#define IPW_STATE_ASSOCIATED 0x0004 97221337Sdim#define IPW_STATE_ASSOCIATION_LOST 0x0008 98221337Sdim#define IPW_STATE_ASSOCIATION_CHANGED 0x0010 /* assoc params changed? */ 99221337Sdim#define IPW_STATE_SCAN_COMPLETE 0x0020 100221337Sdim#define IPW_STATE_PS_ENTER 0x0040 /* entered power-save mode */ 101221337Sdim#define IPW_STATE_PS_EXIT 0x0080 /* exited power-save mode */ 102221337Sdim#define IPW_STATE_RADIO_DISABLED 0x0100 103221337Sdim#define IPW_STATE_DISABLED 0x0200 104221337Sdim#define IPW_STATE_POWER_DOWN 0x0400 /* ??? */ 105221337Sdim#define IPW_STATE_SCANNING 0x0800 106221337Sdim 107221337Sdim/* table1 offsets */ 108221337Sdim#define IPW_INFO_LOCK 480 109221337Sdim#define IPW_INFO_APS_CNT 604 110221337Sdim#define IPW_INFO_APS_BASE 608 111221337Sdim#define IPW_INFO_CARD_DISABLED 628 112221337Sdim#define IPW_INFO_CURRENT_CHANNEL 756 113221337Sdim#define IPW_INFO_CURRENT_TX_RATE 768 114221337Sdim 115221337Sdim/* table2 offsets */ 116221337Sdim#define IPW_INFO_CURRENT_SSID 48 117221337Sdim#define IPW_INFO_CURRENT_BSSID 112 118221337Sdim 119221337Sdim/* supported rates */ 120221337Sdim#define IPW_RATE_DS1 1 121221337Sdim#define IPW_RATE_DS2 2 122221337Sdim#define IPW_RATE_DS5 4 123221337Sdim#define IPW_RATE_DS11 8 124221337Sdim 125221337Sdim/* firmware binary image header */ 126221337Sdimstruct ipw_firmware_hdr { 127221337Sdim uint32_t version; 128221337Sdim uint32_t mainsz; 129221337Sdim uint32_t ucodesz; 130221337Sdim} __packed; 131221337Sdim 132221337Sdim/* buffer descriptor */ 133224145Sdimstruct ipw_bd { 134224145Sdim uint32_t physaddr; 135224145Sdim uint32_t len; 136224145Sdim uint8_t flags; 137221337Sdim#define IPW_BD_FLAG_TX_FRAME_802_3 0x00 138221337Sdim#define IPW_BD_FLAG_TX_NOT_LAST_FRAGMENT 0x01 139221337Sdim#define IPW_BD_FLAG_TX_FRAME_COMMAND 0x02 140221337Sdim#define IPW_BD_FLAG_TX_FRAME_802_11 0x04 141226890Sdim#define IPW_BD_FLAG_TX_LAST_FRAGMENT 0x08 142224145Sdim uint8_t nfrag; /* number of fragments */ 143224145Sdim uint8_t reserved[6]; 144224145Sdim} __packed; 145224145Sdim 146224145Sdim/* status */ 147224145Sdimstruct ipw_status { 148224145Sdim uint32_t len; 149224145Sdim uint16_t code; 150224145Sdim#define IPW_STATUS_CODE_COMMAND 0 151224145Sdim#define IPW_STATUS_CODE_NEWSTATE 1 152224145Sdim#define IPW_STATUS_CODE_DATA_802_11 2 153224145Sdim#define IPW_STATUS_CODE_DATA_802_3 3 154221337Sdim#define IPW_STATUS_CODE_NOTIFICATION 4 155224145Sdim uint8_t flags; 156224145Sdim#define IPW_STATUS_FLAG_DECRYPTED 0x01 157224145Sdim#define IPW_STATUS_FLAG_WEP_ENCRYPTED 0x02 158221337Sdim#define IPW_STATUS_FLAG_CRC_ERROR 0x04 159224145Sdim uint8_t rssi; /* received signal strength indicator */ 160224145Sdim#define IPW_RSSI_TO_DBM (-98) /* XXX fixed nf to convert dBm */ 161224145Sdim} __packed; 162224145Sdim 163224145Sdim/* data header */ 164224145Sdimstruct ipw_hdr { 165224145Sdim uint32_t type; 166224145Sdim#define IPW_HDR_TYPE_SEND 33 167224145Sdim uint32_t subtype; 168224145Sdim uint8_t encrypted; 169224145Sdim uint8_t encrypt; 170224145Sdim uint8_t keyidx; 171224145Sdim uint8_t keysz; 172224145Sdim uint8_t key[IEEE80211_KEYBUF_SIZE]; 173224145Sdim uint8_t reserved[10]; 174224145Sdim uint8_t src_addr[IEEE80211_ADDR_LEN]; 175224145Sdim uint8_t dst_addr[IEEE80211_ADDR_LEN]; 176224145Sdim uint16_t fragmentsz; 177221337Sdim} __packed; 178221337Sdim 179226890Sdim/* command */ 180221337Sdimstruct ipw_cmd { 181221337Sdim uint32_t type; 182221337Sdim#define IPW_CMD_ENABLE 2 183221337Sdim#define IPW_CMD_SET_CONFIGURATION 6 184221337Sdim#define IPW_CMD_SET_ESSID 8 185221337Sdim#define IPW_CMD_SET_MANDATORY_BSSID 9 186221337Sdim#define IPW_CMD_SET_MAC_ADDRESS 11 187221337Sdim#define IPW_CMD_SET_MODE 12 188221337Sdim#define IPW_CMD_SET_CHANNEL 14 189221337Sdim#define IPW_CMD_SET_RTS_THRESHOLD 15 190221337Sdim#define IPW_CMD_SET_FRAG_THRESHOLD 16 191221337Sdim#define IPW_CMD_SET_POWER_MODE 17 192221337Sdim#define IPW_CMD_SET_TX_RATES 18 193221337Sdim#define IPW_CMD_SET_BASIC_TX_RATES 19 194221337Sdim#define IPW_CMD_SET_WEP_KEY 20 195221337Sdim#define IPW_CMD_SET_WEP_KEY_INDEX 25 196221337Sdim#define IPW_CMD_SET_WEP_FLAGS 26 197221337Sdim#define IPW_CMD_ADD_MULTICAST 27 198221337Sdim#define IPW_CMD_SET_BEACON_INTERVAL 29 199221337Sdim#define IPW_CMD_SET_TX_POWER_INDEX 36 200221337Sdim#define IPW_CMD_BROADCAST_SCAN 43 201221337Sdim#define IPW_CMD_DISABLE 44 202221337Sdim#define IPW_CMD_SET_DESIRED_BSSID 45 203221337Sdim#define IPW_CMD_SET_SCAN_OPTIONS 46 204221337Sdim#define IPW_CMD_SET_SCAN_DWELL_TIME 47 205221337Sdim#define IPW_CMD_SET_SHORT_RETRY 51 206#define IPW_CMD_SET_LONG_RETRY 52 207#define IPW_CMD_PREPARE_POWER_DOWN 58 208#define IPW_CMD_DISABLE_PHY 61 209#define IPW_CMD_SET_MSDU_TX_RATES 62 210#define IPW_CMD_SET_SECURITY_INFO 67 211#define IPW_CMD_DISASSOCIATE 68 212#define IPW_CMD_SET_WPA_IE 69 213 uint32_t subtype; 214 uint32_t seq; 215 uint32_t len; 216 uint8_t data[400]; 217 uint32_t status; 218 uint8_t reserved[68]; 219} __packed; 220 221/* possible values for command IPW_CMD_SET_POWER_MODE */ 222#define IPW_POWER_MODE_CAM 0 223#define IPW_POWER_MODE_AUTO 6 224 225/* possible values for command IPW_CMD_SET_MODE */ 226#define IPW_MODE_BSS 0 227#define IPW_MODE_IBSS 1 228#define IPW_MODE_MONITOR 2 229 230/* possible flags for command IPW_CMD_SET_WEP_FLAGS */ 231#define IPW_WEPON 0x8 232 233/* structure for command IPW_CMD_SET_WEP_KEY */ 234struct ipw_wep_key { 235 uint8_t idx; 236 uint8_t len; 237 uint8_t key[13]; 238} __packed; 239 240/* structure for command IPW_CMD_SET_SECURITY_INFORMATION */ 241struct ipw_security { 242 uint32_t ciphers; 243#define IPW_CIPHER_NONE 0x00000001 244#define IPW_CIPHER_WEP40 0x00000002 245#define IPW_CIPHER_TKIP 0x00000004 246#define IPW_CIPHER_CCMP 0x00000010 247#define IPW_CIPHER_WEP104 0x00000020 248#define IPW_CIPHER_CKIP 0x00000040 249 uint16_t reserved1; 250 uint8_t authmode; 251#define IPW_AUTH_OPEN 0 252#define IPW_AUTH_SHARED 1 253 uint16_t reserved2; 254} __packed; 255 256/* structure for command IPW_CMD_SET_SCAN_OPTIONS */ 257struct ipw_scan_options { 258 uint32_t flags; 259#define IPW_SCAN_DO_NOT_ASSOCIATE 0x00000001 260#define IPW_SCAN_MIXED_CELL 0x00000002 261#define IPW_SCAN_PASSIVE 0x00000008 262 uint32_t channels; 263} __packed; 264 265/* structure for command IPW_CMD_SET_CONFIGURATION */ 266struct ipw_configuration { 267 uint32_t flags; 268#define IPW_CFG_PROMISCUOUS 0x00000004 269#define IPW_CFG_PREAMBLE_AUTO 0x00000010 270#define IPW_CFG_IBSS_AUTO_START 0x00000020 271#define IPW_CFG_802_1x_ENABLE 0x00004000 272#define IPW_CFG_BSS_MASK 0x00008000 273#define IPW_CFG_IBSS_MASK 0x00010000 274 uint32_t bss_chan; 275 uint32_t ibss_chan; 276} __packed; 277 278/* structure for command IPW_CMD_SET_WPA_IE */ 279struct ipw_wpa_ie { 280 uint16_t mask; 281 uint16_t capinfo; 282 uint16_t lintval; 283 uint8_t bssid[IEEE80211_ADDR_LEN]; 284 uint32_t len; 285 struct ieee80211_ie_wpa ie; 286} __packed; 287 288/* element in AP table */ 289struct ipw_node { 290 uint32_t reserved1[2]; 291 uint8_t bssid[IEEE80211_ADDR_LEN]; 292 uint8_t chan; 293 uint8_t rates; 294 uint16_t reserved2; 295 uint16_t capinfo; 296 uint16_t reserved3; 297 uint16_t intval; 298 uint8_t reserved4[28]; 299 uint8_t essid[IEEE80211_NWID_LEN]; 300 uint16_t reserved5; 301 uint8_t esslen; 302 uint8_t reserved6[7]; 303 uint8_t rssi; 304} __packed; 305 306/* EEPROM = Electrically Erasable Programmable Read-Only Memory */ 307 308#define IPW_MEM_EEPROM_CTL 0x00300040 309 310#define IPW_EEPROM_RADIO 0x11 311#define IPW_EEPROM_MAC 0x21 312#define IPW_EEPROM_CHANNEL_LIST 0x37 313 314#define IPW_EEPROM_DELAY 1 /* minimum hold time (microsecond) */ 315 316#define IPW_EEPROM_C (1 << 0) /* Serial Clock */ 317#define IPW_EEPROM_S (1 << 1) /* Chip Select */ 318#define IPW_EEPROM_D (1 << 2) /* Serial data input */ 319#define IPW_EEPROM_Q (1 << 4) /* Serial data output */ 320 321#define IPW_EEPROM_SHIFT_D 2 322#define IPW_EEPROM_SHIFT_Q 4 323 324/* 325 * control and status registers access macros 326 */ 327#define CSR_READ_1(sc, reg) \ 328 bus_space_read_1((sc)->sc_st, (sc)->sc_sh, (reg)) 329 330#define CSR_READ_2(sc, reg) \ 331 bus_space_read_2((sc)->sc_st, (sc)->sc_sh, (reg)) 332 333#define CSR_READ_4(sc, reg) \ 334 bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg)) 335 336#define CSR_WRITE_1(sc, reg, val) \ 337 bus_space_write_1((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 338 339#define CSR_WRITE_2(sc, reg, val) \ 340 bus_space_write_2((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 341 342#define CSR_WRITE_4(sc, reg, val) \ 343 bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 344 345#define CSR_WRITE_MULTI_1(sc, reg, buf, len) \ 346 bus_space_write_multi_1((sc)->sc_st, (sc)->sc_sh, (reg), \ 347 (buf), (len)) 348 349/* 350 * indirect memory space access macros 351 */ 352#define MEM_READ_1(sc, addr) \ 353 (CSR_WRITE_4((sc), IPW_CSR_INDIRECT_ADDR, (addr)), \ 354 CSR_READ_1((sc), IPW_CSR_INDIRECT_DATA)) 355 356#define MEM_READ_4(sc, addr) \ 357 (CSR_WRITE_4((sc), IPW_CSR_INDIRECT_ADDR, (addr)), \ 358 CSR_READ_4((sc), IPW_CSR_INDIRECT_DATA)) 359 360#define MEM_WRITE_1(sc, addr, val) do { \ 361 CSR_WRITE_4((sc), IPW_CSR_INDIRECT_ADDR, (addr)); \ 362 CSR_WRITE_1((sc), IPW_CSR_INDIRECT_DATA, (val)); \ 363} while (/* CONSTCOND */0) 364 365#define MEM_WRITE_2(sc, addr, val) do { \ 366 CSR_WRITE_4((sc), IPW_CSR_INDIRECT_ADDR, (addr)); \ 367 CSR_WRITE_2((sc), IPW_CSR_INDIRECT_DATA, (val)); \ 368} while (/* CONSTCOND */0) 369 370#define MEM_WRITE_4(sc, addr, val) do { \ 371 CSR_WRITE_4((sc), IPW_CSR_INDIRECT_ADDR, (addr)); \ 372 CSR_WRITE_4((sc), IPW_CSR_INDIRECT_DATA, (val)); \ 373} while (/* CONSTCOND */0) 374 375#define MEM_WRITE_MULTI_1(sc, addr, buf, len) do { \ 376 CSR_WRITE_4((sc), IPW_CSR_INDIRECT_ADDR, (addr)); \ 377 CSR_WRITE_MULTI_1((sc), IPW_CSR_INDIRECT_DATA, (buf), (len)); \ 378} while (/* CONSTCOND */0) 379 380/* 381 * EEPROM access macro 382 */ 383#define IPW_EEPROM_CTL(sc, val) do { \ 384 MEM_WRITE_4((sc), IPW_MEM_EEPROM_CTL, (val)); \ 385 DELAY(IPW_EEPROM_DELAY); \ 386} while (0) 387