1/*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2008, Pyun YongHyeon <yongari@FreeBSD.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice unmodified, this list of conditions, and the following 12 * disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30/* Driver for Atheros AR8121/AR8113/AR8114 PCIe Ethernet. */ 31 32#include <sys/cdefs.h> 33__FBSDID("$FreeBSD: releng/12.0/sys/dev/ale/if_ale.c 338948 2018-09-26 17:12:14Z imp $"); 34 35#include <sys/param.h> 36#include <sys/systm.h> 37#include <sys/bus.h> 38#include <sys/endian.h> 39#include <sys/kernel.h> 40#include <sys/malloc.h> 41#include <sys/mbuf.h> 42#include <sys/module.h> 43#include <sys/rman.h> 44#include <sys/queue.h> 45#include <sys/socket.h> 46#include <sys/sockio.h> 47#include <sys/sysctl.h> 48#include <sys/taskqueue.h> 49 50#include <net/bpf.h> 51#include <net/if.h> 52#include <net/if_var.h> 53#include <net/if_arp.h> 54#include <net/ethernet.h> 55#include <net/if_dl.h> 56#include <net/if_llc.h> 57#include <net/if_media.h> 58#include <net/if_types.h> 59#include <net/if_vlan_var.h> 60 61#include <netinet/in.h> 62#include <netinet/in_systm.h> 63#include <netinet/ip.h> 64#include <netinet/tcp.h> 65 66#include <dev/mii/mii.h> 67#include <dev/mii/miivar.h> 68 69#include <dev/pci/pcireg.h> 70#include <dev/pci/pcivar.h> 71 72#include <machine/bus.h> 73#include <machine/in_cksum.h> 74 75#include <dev/ale/if_alereg.h> 76#include <dev/ale/if_alevar.h> 77 78/* "device miibus" required. See GENERIC if you get errors here. */ 79#include "miibus_if.h" 80 81/* For more information about Tx checksum offload issues see ale_encap(). */ 82#define ALE_CSUM_FEATURES (CSUM_TCP | CSUM_UDP) 83 84MODULE_DEPEND(ale, pci, 1, 1, 1); 85MODULE_DEPEND(ale, ether, 1, 1, 1); 86MODULE_DEPEND(ale, miibus, 1, 1, 1); 87 88/* Tunables. */ 89static int msi_disable = 0; 90static int msix_disable = 0; 91TUNABLE_INT("hw.ale.msi_disable", &msi_disable); 92TUNABLE_INT("hw.ale.msix_disable", &msix_disable); 93 94/* 95 * Devices supported by this driver. 96 */ 97static const struct ale_dev { 98 uint16_t ale_vendorid; 99 uint16_t ale_deviceid; 100 const char *ale_name; 101} ale_devs[] = { 102 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR81XX, 103 "Atheros AR8121/AR8113/AR8114 PCIe Ethernet" }, 104}; 105 106static int ale_attach(device_t); 107static int ale_check_boundary(struct ale_softc *); 108static int ale_detach(device_t); 109static int ale_dma_alloc(struct ale_softc *); 110static void ale_dma_free(struct ale_softc *); 111static void ale_dmamap_cb(void *, bus_dma_segment_t *, int, int); 112static int ale_encap(struct ale_softc *, struct mbuf **); 113static void ale_get_macaddr(struct ale_softc *); 114static void ale_init(void *); 115static void ale_init_locked(struct ale_softc *); 116static void ale_init_rx_pages(struct ale_softc *); 117static void ale_init_tx_ring(struct ale_softc *); 118static void ale_int_task(void *, int); 119static int ale_intr(void *); 120static int ale_ioctl(struct ifnet *, u_long, caddr_t); 121static void ale_mac_config(struct ale_softc *); 122static int ale_miibus_readreg(device_t, int, int); 123static void ale_miibus_statchg(device_t); 124static int ale_miibus_writereg(device_t, int, int, int); 125static int ale_mediachange(struct ifnet *); 126static void ale_mediastatus(struct ifnet *, struct ifmediareq *); 127static void ale_phy_reset(struct ale_softc *); 128static int ale_probe(device_t); 129static void ale_reset(struct ale_softc *); 130static int ale_resume(device_t); 131static void ale_rx_update_page(struct ale_softc *, struct ale_rx_page **, 132 uint32_t, uint32_t *); 133static void ale_rxcsum(struct ale_softc *, struct mbuf *, uint32_t); 134static int ale_rxeof(struct ale_softc *sc, int); 135static void ale_rxfilter(struct ale_softc *); 136static void ale_rxvlan(struct ale_softc *); 137static void ale_setlinkspeed(struct ale_softc *); 138static void ale_setwol(struct ale_softc *); 139static int ale_shutdown(device_t); 140static void ale_start(struct ifnet *); 141static void ale_start_locked(struct ifnet *); 142static void ale_stats_clear(struct ale_softc *); 143static void ale_stats_update(struct ale_softc *); 144static void ale_stop(struct ale_softc *); 145static void ale_stop_mac(struct ale_softc *); 146static int ale_suspend(device_t); 147static void ale_sysctl_node(struct ale_softc *); 148static void ale_tick(void *); 149static void ale_txeof(struct ale_softc *); 150static void ale_watchdog(struct ale_softc *); 151static int sysctl_int_range(SYSCTL_HANDLER_ARGS, int, int); 152static int sysctl_hw_ale_proc_limit(SYSCTL_HANDLER_ARGS); 153static int sysctl_hw_ale_int_mod(SYSCTL_HANDLER_ARGS); 154 155static device_method_t ale_methods[] = { 156 /* Device interface. */ 157 DEVMETHOD(device_probe, ale_probe), 158 DEVMETHOD(device_attach, ale_attach), 159 DEVMETHOD(device_detach, ale_detach), 160 DEVMETHOD(device_shutdown, ale_shutdown), 161 DEVMETHOD(device_suspend, ale_suspend), 162 DEVMETHOD(device_resume, ale_resume), 163 164 /* MII interface. */ 165 DEVMETHOD(miibus_readreg, ale_miibus_readreg), 166 DEVMETHOD(miibus_writereg, ale_miibus_writereg), 167 DEVMETHOD(miibus_statchg, ale_miibus_statchg), 168 169 DEVMETHOD_END 170}; 171 172static driver_t ale_driver = { 173 "ale", 174 ale_methods, 175 sizeof(struct ale_softc) 176}; 177 178static devclass_t ale_devclass; 179 180DRIVER_MODULE(ale, pci, ale_driver, ale_devclass, NULL, NULL); 181MODULE_PNP_INFO("U16:vendor;U16:device;D:#", pci, ale, ale_devs, 182 nitems(ale_devs)); 183DRIVER_MODULE(miibus, ale, miibus_driver, miibus_devclass, NULL, NULL); 184 185static struct resource_spec ale_res_spec_mem[] = { 186 { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE }, 187 { -1, 0, 0 } 188}; 189 190static struct resource_spec ale_irq_spec_legacy[] = { 191 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE }, 192 { -1, 0, 0 } 193}; 194 195static struct resource_spec ale_irq_spec_msi[] = { 196 { SYS_RES_IRQ, 1, RF_ACTIVE }, 197 { -1, 0, 0 } 198}; 199 200static struct resource_spec ale_irq_spec_msix[] = { 201 { SYS_RES_IRQ, 1, RF_ACTIVE }, 202 { -1, 0, 0 } 203}; 204 205static int 206ale_miibus_readreg(device_t dev, int phy, int reg) 207{ 208 struct ale_softc *sc; 209 uint32_t v; 210 int i; 211 212 sc = device_get_softc(dev); 213 214 CSR_WRITE_4(sc, ALE_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ | 215 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); 216 for (i = ALE_PHY_TIMEOUT; i > 0; i--) { 217 DELAY(5); 218 v = CSR_READ_4(sc, ALE_MDIO); 219 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) 220 break; 221 } 222 223 if (i == 0) { 224 device_printf(sc->ale_dev, "phy read timeout : %d\n", reg); 225 return (0); 226 } 227 228 return ((v & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT); 229} 230 231static int 232ale_miibus_writereg(device_t dev, int phy, int reg, int val) 233{ 234 struct ale_softc *sc; 235 uint32_t v; 236 int i; 237 238 sc = device_get_softc(dev); 239 240 CSR_WRITE_4(sc, ALE_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE | 241 (val & MDIO_DATA_MASK) << MDIO_DATA_SHIFT | 242 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); 243 for (i = ALE_PHY_TIMEOUT; i > 0; i--) { 244 DELAY(5); 245 v = CSR_READ_4(sc, ALE_MDIO); 246 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) 247 break; 248 } 249 250 if (i == 0) 251 device_printf(sc->ale_dev, "phy write timeout : %d\n", reg); 252 253 return (0); 254} 255 256static void 257ale_miibus_statchg(device_t dev) 258{ 259 struct ale_softc *sc; 260 struct mii_data *mii; 261 struct ifnet *ifp; 262 uint32_t reg; 263 264 sc = device_get_softc(dev); 265 mii = device_get_softc(sc->ale_miibus); 266 ifp = sc->ale_ifp; 267 if (mii == NULL || ifp == NULL || 268 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 269 return; 270 271 sc->ale_flags &= ~ALE_FLAG_LINK; 272 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 273 (IFM_ACTIVE | IFM_AVALID)) { 274 switch (IFM_SUBTYPE(mii->mii_media_active)) { 275 case IFM_10_T: 276 case IFM_100_TX: 277 sc->ale_flags |= ALE_FLAG_LINK; 278 break; 279 case IFM_1000_T: 280 if ((sc->ale_flags & ALE_FLAG_FASTETHER) == 0) 281 sc->ale_flags |= ALE_FLAG_LINK; 282 break; 283 default: 284 break; 285 } 286 } 287 288 /* Stop Rx/Tx MACs. */ 289 ale_stop_mac(sc); 290 291 /* Program MACs with resolved speed/duplex/flow-control. */ 292 if ((sc->ale_flags & ALE_FLAG_LINK) != 0) { 293 ale_mac_config(sc); 294 /* Reenable Tx/Rx MACs. */ 295 reg = CSR_READ_4(sc, ALE_MAC_CFG); 296 reg |= MAC_CFG_TX_ENB | MAC_CFG_RX_ENB; 297 CSR_WRITE_4(sc, ALE_MAC_CFG, reg); 298 } 299} 300 301static void 302ale_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 303{ 304 struct ale_softc *sc; 305 struct mii_data *mii; 306 307 sc = ifp->if_softc; 308 ALE_LOCK(sc); 309 if ((ifp->if_flags & IFF_UP) == 0) { 310 ALE_UNLOCK(sc); 311 return; 312 } 313 mii = device_get_softc(sc->ale_miibus); 314 315 mii_pollstat(mii); 316 ifmr->ifm_status = mii->mii_media_status; 317 ifmr->ifm_active = mii->mii_media_active; 318 ALE_UNLOCK(sc); 319} 320 321static int 322ale_mediachange(struct ifnet *ifp) 323{ 324 struct ale_softc *sc; 325 struct mii_data *mii; 326 struct mii_softc *miisc; 327 int error; 328 329 sc = ifp->if_softc; 330 ALE_LOCK(sc); 331 mii = device_get_softc(sc->ale_miibus); 332 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 333 PHY_RESET(miisc); 334 error = mii_mediachg(mii); 335 ALE_UNLOCK(sc); 336 337 return (error); 338} 339 340static int 341ale_probe(device_t dev) 342{ 343 const struct ale_dev *sp; 344 int i; 345 uint16_t vendor, devid; 346 347 vendor = pci_get_vendor(dev); 348 devid = pci_get_device(dev); 349 sp = ale_devs; 350 for (i = 0; i < nitems(ale_devs); i++) { 351 if (vendor == sp->ale_vendorid && 352 devid == sp->ale_deviceid) { 353 device_set_desc(dev, sp->ale_name); 354 return (BUS_PROBE_DEFAULT); 355 } 356 sp++; 357 } 358 359 return (ENXIO); 360} 361 362static void 363ale_get_macaddr(struct ale_softc *sc) 364{ 365 uint32_t ea[2], reg; 366 int i, vpdc; 367 368 reg = CSR_READ_4(sc, ALE_SPI_CTRL); 369 if ((reg & SPI_VPD_ENB) != 0) { 370 reg &= ~SPI_VPD_ENB; 371 CSR_WRITE_4(sc, ALE_SPI_CTRL, reg); 372 } 373 374 if (pci_find_cap(sc->ale_dev, PCIY_VPD, &vpdc) == 0) { 375 /* 376 * PCI VPD capability found, let TWSI reload EEPROM. 377 * This will set ethernet address of controller. 378 */ 379 CSR_WRITE_4(sc, ALE_TWSI_CTRL, CSR_READ_4(sc, ALE_TWSI_CTRL) | 380 TWSI_CTRL_SW_LD_START); 381 for (i = 100; i > 0; i--) { 382 DELAY(1000); 383 reg = CSR_READ_4(sc, ALE_TWSI_CTRL); 384 if ((reg & TWSI_CTRL_SW_LD_START) == 0) 385 break; 386 } 387 if (i == 0) 388 device_printf(sc->ale_dev, 389 "reloading EEPROM timeout!\n"); 390 } else { 391 if (bootverbose) 392 device_printf(sc->ale_dev, 393 "PCI VPD capability not found!\n"); 394 } 395 396 ea[0] = CSR_READ_4(sc, ALE_PAR0); 397 ea[1] = CSR_READ_4(sc, ALE_PAR1); 398 sc->ale_eaddr[0] = (ea[1] >> 8) & 0xFF; 399 sc->ale_eaddr[1] = (ea[1] >> 0) & 0xFF; 400 sc->ale_eaddr[2] = (ea[0] >> 24) & 0xFF; 401 sc->ale_eaddr[3] = (ea[0] >> 16) & 0xFF; 402 sc->ale_eaddr[4] = (ea[0] >> 8) & 0xFF; 403 sc->ale_eaddr[5] = (ea[0] >> 0) & 0xFF; 404} 405 406static void 407ale_phy_reset(struct ale_softc *sc) 408{ 409 410 /* Reset magic from Linux. */ 411 CSR_WRITE_2(sc, ALE_GPHY_CTRL, 412 GPHY_CTRL_HIB_EN | GPHY_CTRL_HIB_PULSE | GPHY_CTRL_SEL_ANA_RESET | 413 GPHY_CTRL_PHY_PLL_ON); 414 DELAY(1000); 415 CSR_WRITE_2(sc, ALE_GPHY_CTRL, 416 GPHY_CTRL_EXT_RESET | GPHY_CTRL_HIB_EN | GPHY_CTRL_HIB_PULSE | 417 GPHY_CTRL_SEL_ANA_RESET | GPHY_CTRL_PHY_PLL_ON); 418 DELAY(1000); 419 420#define ATPHY_DBG_ADDR 0x1D 421#define ATPHY_DBG_DATA 0x1E 422 423 /* Enable hibernation mode. */ 424 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 425 ATPHY_DBG_ADDR, 0x0B); 426 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 427 ATPHY_DBG_DATA, 0xBC00); 428 /* Set Class A/B for all modes. */ 429 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 430 ATPHY_DBG_ADDR, 0x00); 431 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 432 ATPHY_DBG_DATA, 0x02EF); 433 /* Enable 10BT power saving. */ 434 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 435 ATPHY_DBG_ADDR, 0x12); 436 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 437 ATPHY_DBG_DATA, 0x4C04); 438 /* Adjust 1000T power. */ 439 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 440 ATPHY_DBG_ADDR, 0x04); 441 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 442 ATPHY_DBG_ADDR, 0x8BBB); 443 /* 10BT center tap voltage. */ 444 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 445 ATPHY_DBG_ADDR, 0x05); 446 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 447 ATPHY_DBG_ADDR, 0x2C46); 448 449#undef ATPHY_DBG_ADDR 450#undef ATPHY_DBG_DATA 451 DELAY(1000); 452} 453 454static int 455ale_attach(device_t dev) 456{ 457 struct ale_softc *sc; 458 struct ifnet *ifp; 459 uint16_t burst; 460 int error, i, msic, msixc, pmc; 461 uint32_t rxf_len, txf_len; 462 463 error = 0; 464 sc = device_get_softc(dev); 465 sc->ale_dev = dev; 466 467 mtx_init(&sc->ale_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 468 MTX_DEF); 469 callout_init_mtx(&sc->ale_tick_ch, &sc->ale_mtx, 0); 470 TASK_INIT(&sc->ale_int_task, 0, ale_int_task, sc); 471 472 /* Map the device. */ 473 pci_enable_busmaster(dev); 474 sc->ale_res_spec = ale_res_spec_mem; 475 sc->ale_irq_spec = ale_irq_spec_legacy; 476 error = bus_alloc_resources(dev, sc->ale_res_spec, sc->ale_res); 477 if (error != 0) { 478 device_printf(dev, "cannot allocate memory resources.\n"); 479 goto fail; 480 } 481 482 /* Set PHY address. */ 483 sc->ale_phyaddr = ALE_PHY_ADDR; 484 485 /* Reset PHY. */ 486 ale_phy_reset(sc); 487 488 /* Reset the ethernet controller. */ 489 ale_reset(sc); 490 491 /* Get PCI and chip id/revision. */ 492 sc->ale_rev = pci_get_revid(dev); 493 if (sc->ale_rev >= 0xF0) { 494 /* L2E Rev. B. AR8114 */ 495 sc->ale_flags |= ALE_FLAG_FASTETHER; 496 } else { 497 if ((CSR_READ_4(sc, ALE_PHY_STATUS) & PHY_STATUS_100M) != 0) { 498 /* L1E AR8121 */ 499 sc->ale_flags |= ALE_FLAG_JUMBO; 500 } else { 501 /* L2E Rev. A. AR8113 */ 502 sc->ale_flags |= ALE_FLAG_FASTETHER; 503 } 504 } 505 /* 506 * All known controllers seems to require 4 bytes alignment 507 * of Tx buffers to make Tx checksum offload with custom 508 * checksum generation method work. 509 */ 510 sc->ale_flags |= ALE_FLAG_TXCSUM_BUG; 511 /* 512 * All known controllers seems to have issues on Rx checksum 513 * offload for fragmented IP datagrams. 514 */ 515 sc->ale_flags |= ALE_FLAG_RXCSUM_BUG; 516 /* 517 * Don't use Tx CMB. It is known to cause RRS update failure 518 * under certain circumstances. Typical phenomenon of the 519 * issue would be unexpected sequence number encountered in 520 * Rx handler. 521 */ 522 sc->ale_flags |= ALE_FLAG_TXCMB_BUG; 523 sc->ale_chip_rev = CSR_READ_4(sc, ALE_MASTER_CFG) >> 524 MASTER_CHIP_REV_SHIFT; 525 if (bootverbose) { 526 device_printf(dev, "PCI device revision : 0x%04x\n", 527 sc->ale_rev); 528 device_printf(dev, "Chip id/revision : 0x%04x\n", 529 sc->ale_chip_rev); 530 } 531 txf_len = CSR_READ_4(sc, ALE_SRAM_TX_FIFO_LEN); 532 rxf_len = CSR_READ_4(sc, ALE_SRAM_RX_FIFO_LEN); 533 /* 534 * Uninitialized hardware returns an invalid chip id/revision 535 * as well as 0xFFFFFFFF for Tx/Rx fifo length. 536 */ 537 if (sc->ale_chip_rev == 0xFFFF || txf_len == 0xFFFFFFFF || 538 rxf_len == 0xFFFFFFF) { 539 device_printf(dev,"chip revision : 0x%04x, %u Tx FIFO " 540 "%u Rx FIFO -- not initialized?\n", sc->ale_chip_rev, 541 txf_len, rxf_len); 542 error = ENXIO; 543 goto fail; 544 } 545 device_printf(dev, "%u Tx FIFO, %u Rx FIFO\n", txf_len, rxf_len); 546 547 /* Allocate IRQ resources. */ 548 msixc = pci_msix_count(dev); 549 msic = pci_msi_count(dev); 550 if (bootverbose) { 551 device_printf(dev, "MSIX count : %d\n", msixc); 552 device_printf(dev, "MSI count : %d\n", msic); 553 } 554 555 /* Prefer MSIX over MSI. */ 556 if (msix_disable == 0 || msi_disable == 0) { 557 if (msix_disable == 0 && msixc == ALE_MSIX_MESSAGES && 558 pci_alloc_msix(dev, &msixc) == 0) { 559 if (msixc == ALE_MSIX_MESSAGES) { 560 device_printf(dev, "Using %d MSIX messages.\n", 561 msixc); 562 sc->ale_flags |= ALE_FLAG_MSIX; 563 sc->ale_irq_spec = ale_irq_spec_msix; 564 } else 565 pci_release_msi(dev); 566 } 567 if (msi_disable == 0 && (sc->ale_flags & ALE_FLAG_MSIX) == 0 && 568 msic == ALE_MSI_MESSAGES && 569 pci_alloc_msi(dev, &msic) == 0) { 570 if (msic == ALE_MSI_MESSAGES) { 571 device_printf(dev, "Using %d MSI messages.\n", 572 msic); 573 sc->ale_flags |= ALE_FLAG_MSI; 574 sc->ale_irq_spec = ale_irq_spec_msi; 575 } else 576 pci_release_msi(dev); 577 } 578 } 579 580 error = bus_alloc_resources(dev, sc->ale_irq_spec, sc->ale_irq); 581 if (error != 0) { 582 device_printf(dev, "cannot allocate IRQ resources.\n"); 583 goto fail; 584 } 585 586 /* Get DMA parameters from PCIe device control register. */ 587 if (pci_find_cap(dev, PCIY_EXPRESS, &i) == 0) { 588 sc->ale_flags |= ALE_FLAG_PCIE; 589 burst = pci_read_config(dev, i + 0x08, 2); 590 /* Max read request size. */ 591 sc->ale_dma_rd_burst = ((burst >> 12) & 0x07) << 592 DMA_CFG_RD_BURST_SHIFT; 593 /* Max payload size. */ 594 sc->ale_dma_wr_burst = ((burst >> 5) & 0x07) << 595 DMA_CFG_WR_BURST_SHIFT; 596 if (bootverbose) { 597 device_printf(dev, "Read request size : %d bytes.\n", 598 128 << ((burst >> 12) & 0x07)); 599 device_printf(dev, "TLP payload size : %d bytes.\n", 600 128 << ((burst >> 5) & 0x07)); 601 } 602 } else { 603 sc->ale_dma_rd_burst = DMA_CFG_RD_BURST_128; 604 sc->ale_dma_wr_burst = DMA_CFG_WR_BURST_128; 605 } 606 607 /* Create device sysctl node. */ 608 ale_sysctl_node(sc); 609 610 if ((error = ale_dma_alloc(sc)) != 0) 611 goto fail; 612 613 /* Load station address. */ 614 ale_get_macaddr(sc); 615 616 ifp = sc->ale_ifp = if_alloc(IFT_ETHER); 617 if (ifp == NULL) { 618 device_printf(dev, "cannot allocate ifnet structure.\n"); 619 error = ENXIO; 620 goto fail; 621 } 622 623 ifp->if_softc = sc; 624 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 625 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 626 ifp->if_ioctl = ale_ioctl; 627 ifp->if_start = ale_start; 628 ifp->if_init = ale_init; 629 ifp->if_snd.ifq_drv_maxlen = ALE_TX_RING_CNT - 1; 630 IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen); 631 IFQ_SET_READY(&ifp->if_snd); 632 ifp->if_capabilities = IFCAP_RXCSUM | IFCAP_TXCSUM | IFCAP_TSO4; 633 ifp->if_hwassist = ALE_CSUM_FEATURES | CSUM_TSO; 634 if (pci_find_cap(dev, PCIY_PMG, &pmc) == 0) { 635 sc->ale_flags |= ALE_FLAG_PMCAP; 636 ifp->if_capabilities |= IFCAP_WOL_MAGIC | IFCAP_WOL_MCAST; 637 } 638 ifp->if_capenable = ifp->if_capabilities; 639 640 /* Set up MII bus. */ 641 error = mii_attach(dev, &sc->ale_miibus, ifp, ale_mediachange, 642 ale_mediastatus, BMSR_DEFCAPMASK, sc->ale_phyaddr, MII_OFFSET_ANY, 643 MIIF_DOPAUSE); 644 if (error != 0) { 645 device_printf(dev, "attaching PHYs failed\n"); 646 goto fail; 647 } 648 649 ether_ifattach(ifp, sc->ale_eaddr); 650 651 /* VLAN capability setup. */ 652 ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING | 653 IFCAP_VLAN_HWCSUM | IFCAP_VLAN_HWTSO; 654 ifp->if_capenable = ifp->if_capabilities; 655 /* 656 * Even though controllers supported by ale(3) have Rx checksum 657 * offload bug the workaround for fragmented frames seemed to 658 * work so far. However it seems Rx checksum offload does not 659 * work under certain conditions. So disable Rx checksum offload 660 * until I find more clue about it but allow users to override it. 661 */ 662 ifp->if_capenable &= ~IFCAP_RXCSUM; 663 664 /* Tell the upper layer(s) we support long frames. */ 665 ifp->if_hdrlen = sizeof(struct ether_vlan_header); 666 667 /* Create local taskq. */ 668 sc->ale_tq = taskqueue_create_fast("ale_taskq", M_WAITOK, 669 taskqueue_thread_enqueue, &sc->ale_tq); 670 if (sc->ale_tq == NULL) { 671 device_printf(dev, "could not create taskqueue.\n"); 672 ether_ifdetach(ifp); 673 error = ENXIO; 674 goto fail; 675 } 676 taskqueue_start_threads(&sc->ale_tq, 1, PI_NET, "%s taskq", 677 device_get_nameunit(sc->ale_dev)); 678 679 if ((sc->ale_flags & ALE_FLAG_MSIX) != 0) 680 msic = ALE_MSIX_MESSAGES; 681 else if ((sc->ale_flags & ALE_FLAG_MSI) != 0) 682 msic = ALE_MSI_MESSAGES; 683 else 684 msic = 1; 685 for (i = 0; i < msic; i++) { 686 error = bus_setup_intr(dev, sc->ale_irq[i], 687 INTR_TYPE_NET | INTR_MPSAFE, ale_intr, NULL, sc, 688 &sc->ale_intrhand[i]); 689 if (error != 0) 690 break; 691 } 692 if (error != 0) { 693 device_printf(dev, "could not set up interrupt handler.\n"); 694 taskqueue_free(sc->ale_tq); 695 sc->ale_tq = NULL; 696 ether_ifdetach(ifp); 697 goto fail; 698 } 699 700fail: 701 if (error != 0) 702 ale_detach(dev); 703 704 return (error); 705} 706 707static int 708ale_detach(device_t dev) 709{ 710 struct ale_softc *sc; 711 struct ifnet *ifp; 712 int i, msic; 713 714 sc = device_get_softc(dev); 715 716 ifp = sc->ale_ifp; 717 if (device_is_attached(dev)) { 718 ether_ifdetach(ifp); 719 ALE_LOCK(sc); 720 ale_stop(sc); 721 ALE_UNLOCK(sc); 722 callout_drain(&sc->ale_tick_ch); 723 taskqueue_drain(sc->ale_tq, &sc->ale_int_task); 724 } 725 726 if (sc->ale_tq != NULL) { 727 taskqueue_drain(sc->ale_tq, &sc->ale_int_task); 728 taskqueue_free(sc->ale_tq); 729 sc->ale_tq = NULL; 730 } 731 732 if (sc->ale_miibus != NULL) { 733 device_delete_child(dev, sc->ale_miibus); 734 sc->ale_miibus = NULL; 735 } 736 bus_generic_detach(dev); 737 ale_dma_free(sc); 738 739 if (ifp != NULL) { 740 if_free(ifp); 741 sc->ale_ifp = NULL; 742 } 743 744 if ((sc->ale_flags & ALE_FLAG_MSIX) != 0) 745 msic = ALE_MSIX_MESSAGES; 746 else if ((sc->ale_flags & ALE_FLAG_MSI) != 0) 747 msic = ALE_MSI_MESSAGES; 748 else 749 msic = 1; 750 for (i = 0; i < msic; i++) { 751 if (sc->ale_intrhand[i] != NULL) { 752 bus_teardown_intr(dev, sc->ale_irq[i], 753 sc->ale_intrhand[i]); 754 sc->ale_intrhand[i] = NULL; 755 } 756 } 757 758 bus_release_resources(dev, sc->ale_irq_spec, sc->ale_irq); 759 if ((sc->ale_flags & (ALE_FLAG_MSI | ALE_FLAG_MSIX)) != 0) 760 pci_release_msi(dev); 761 bus_release_resources(dev, sc->ale_res_spec, sc->ale_res); 762 mtx_destroy(&sc->ale_mtx); 763 764 return (0); 765} 766 767#define ALE_SYSCTL_STAT_ADD32(c, h, n, p, d) \ 768 SYSCTL_ADD_UINT(c, h, OID_AUTO, n, CTLFLAG_RD, p, 0, d) 769 770#if __FreeBSD_version >= 900030 771#define ALE_SYSCTL_STAT_ADD64(c, h, n, p, d) \ 772 SYSCTL_ADD_UQUAD(c, h, OID_AUTO, n, CTLFLAG_RD, p, d) 773#elif __FreeBSD_version > 800000 774#define ALE_SYSCTL_STAT_ADD64(c, h, n, p, d) \ 775 SYSCTL_ADD_QUAD(c, h, OID_AUTO, n, CTLFLAG_RD, p, d) 776#else 777#define ALE_SYSCTL_STAT_ADD64(c, h, n, p, d) \ 778 SYSCTL_ADD_ULONG(c, h, OID_AUTO, n, CTLFLAG_RD, p, d) 779#endif 780 781static void 782ale_sysctl_node(struct ale_softc *sc) 783{ 784 struct sysctl_ctx_list *ctx; 785 struct sysctl_oid_list *child, *parent; 786 struct sysctl_oid *tree; 787 struct ale_hw_stats *stats; 788 int error; 789 790 stats = &sc->ale_stats; 791 ctx = device_get_sysctl_ctx(sc->ale_dev); 792 child = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->ale_dev)); 793 794 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "int_rx_mod", 795 CTLTYPE_INT | CTLFLAG_RW, &sc->ale_int_rx_mod, 0, 796 sysctl_hw_ale_int_mod, "I", "ale Rx interrupt moderation"); 797 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "int_tx_mod", 798 CTLTYPE_INT | CTLFLAG_RW, &sc->ale_int_tx_mod, 0, 799 sysctl_hw_ale_int_mod, "I", "ale Tx interrupt moderation"); 800 /* Pull in device tunables. */ 801 sc->ale_int_rx_mod = ALE_IM_RX_TIMER_DEFAULT; 802 error = resource_int_value(device_get_name(sc->ale_dev), 803 device_get_unit(sc->ale_dev), "int_rx_mod", &sc->ale_int_rx_mod); 804 if (error == 0) { 805 if (sc->ale_int_rx_mod < ALE_IM_TIMER_MIN || 806 sc->ale_int_rx_mod > ALE_IM_TIMER_MAX) { 807 device_printf(sc->ale_dev, "int_rx_mod value out of " 808 "range; using default: %d\n", 809 ALE_IM_RX_TIMER_DEFAULT); 810 sc->ale_int_rx_mod = ALE_IM_RX_TIMER_DEFAULT; 811 } 812 } 813 sc->ale_int_tx_mod = ALE_IM_TX_TIMER_DEFAULT; 814 error = resource_int_value(device_get_name(sc->ale_dev), 815 device_get_unit(sc->ale_dev), "int_tx_mod", &sc->ale_int_tx_mod); 816 if (error == 0) { 817 if (sc->ale_int_tx_mod < ALE_IM_TIMER_MIN || 818 sc->ale_int_tx_mod > ALE_IM_TIMER_MAX) { 819 device_printf(sc->ale_dev, "int_tx_mod value out of " 820 "range; using default: %d\n", 821 ALE_IM_TX_TIMER_DEFAULT); 822 sc->ale_int_tx_mod = ALE_IM_TX_TIMER_DEFAULT; 823 } 824 } 825 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "process_limit", 826 CTLTYPE_INT | CTLFLAG_RW, &sc->ale_process_limit, 0, 827 sysctl_hw_ale_proc_limit, "I", 828 "max number of Rx events to process"); 829 /* Pull in device tunables. */ 830 sc->ale_process_limit = ALE_PROC_DEFAULT; 831 error = resource_int_value(device_get_name(sc->ale_dev), 832 device_get_unit(sc->ale_dev), "process_limit", 833 &sc->ale_process_limit); 834 if (error == 0) { 835 if (sc->ale_process_limit < ALE_PROC_MIN || 836 sc->ale_process_limit > ALE_PROC_MAX) { 837 device_printf(sc->ale_dev, 838 "process_limit value out of range; " 839 "using default: %d\n", ALE_PROC_DEFAULT); 840 sc->ale_process_limit = ALE_PROC_DEFAULT; 841 } 842 } 843 844 /* Misc statistics. */ 845 ALE_SYSCTL_STAT_ADD32(ctx, child, "reset_brk_seq", 846 &stats->reset_brk_seq, 847 "Controller resets due to broken Rx sequnce number"); 848 849 tree = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "stats", CTLFLAG_RD, 850 NULL, "ATE statistics"); 851 parent = SYSCTL_CHILDREN(tree); 852 853 /* Rx statistics. */ 854 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "rx", CTLFLAG_RD, 855 NULL, "Rx MAC statistics"); 856 child = SYSCTL_CHILDREN(tree); 857 ALE_SYSCTL_STAT_ADD32(ctx, child, "good_frames", 858 &stats->rx_frames, "Good frames"); 859 ALE_SYSCTL_STAT_ADD32(ctx, child, "good_bcast_frames", 860 &stats->rx_bcast_frames, "Good broadcast frames"); 861 ALE_SYSCTL_STAT_ADD32(ctx, child, "good_mcast_frames", 862 &stats->rx_mcast_frames, "Good multicast frames"); 863 ALE_SYSCTL_STAT_ADD32(ctx, child, "pause_frames", 864 &stats->rx_pause_frames, "Pause control frames"); 865 ALE_SYSCTL_STAT_ADD32(ctx, child, "control_frames", 866 &stats->rx_control_frames, "Control frames"); 867 ALE_SYSCTL_STAT_ADD32(ctx, child, "crc_errs", 868 &stats->rx_crcerrs, "CRC errors"); 869 ALE_SYSCTL_STAT_ADD32(ctx, child, "len_errs", 870 &stats->rx_lenerrs, "Frames with length mismatched"); 871 ALE_SYSCTL_STAT_ADD64(ctx, child, "good_octets", 872 &stats->rx_bytes, "Good octets"); 873 ALE_SYSCTL_STAT_ADD64(ctx, child, "good_bcast_octets", 874 &stats->rx_bcast_bytes, "Good broadcast octets"); 875 ALE_SYSCTL_STAT_ADD64(ctx, child, "good_mcast_octets", 876 &stats->rx_mcast_bytes, "Good multicast octets"); 877 ALE_SYSCTL_STAT_ADD32(ctx, child, "runts", 878 &stats->rx_runts, "Too short frames"); 879 ALE_SYSCTL_STAT_ADD32(ctx, child, "fragments", 880 &stats->rx_fragments, "Fragmented frames"); 881 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_64", 882 &stats->rx_pkts_64, "64 bytes frames"); 883 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_65_127", 884 &stats->rx_pkts_65_127, "65 to 127 bytes frames"); 885 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_128_255", 886 &stats->rx_pkts_128_255, "128 to 255 bytes frames"); 887 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_256_511", 888 &stats->rx_pkts_256_511, "256 to 511 bytes frames"); 889 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_512_1023", 890 &stats->rx_pkts_512_1023, "512 to 1023 bytes frames"); 891 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_1024_1518", 892 &stats->rx_pkts_1024_1518, "1024 to 1518 bytes frames"); 893 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_1519_max", 894 &stats->rx_pkts_1519_max, "1519 to max frames"); 895 ALE_SYSCTL_STAT_ADD32(ctx, child, "trunc_errs", 896 &stats->rx_pkts_truncated, "Truncated frames due to MTU size"); 897 ALE_SYSCTL_STAT_ADD32(ctx, child, "fifo_oflows", 898 &stats->rx_fifo_oflows, "FIFO overflows"); 899 ALE_SYSCTL_STAT_ADD32(ctx, child, "rrs_errs", 900 &stats->rx_rrs_errs, "Return status write-back errors"); 901 ALE_SYSCTL_STAT_ADD32(ctx, child, "align_errs", 902 &stats->rx_alignerrs, "Alignment errors"); 903 ALE_SYSCTL_STAT_ADD32(ctx, child, "filtered", 904 &stats->rx_pkts_filtered, 905 "Frames dropped due to address filtering"); 906 907 /* Tx statistics. */ 908 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "tx", CTLFLAG_RD, 909 NULL, "Tx MAC statistics"); 910 child = SYSCTL_CHILDREN(tree); 911 ALE_SYSCTL_STAT_ADD32(ctx, child, "good_frames", 912 &stats->tx_frames, "Good frames"); 913 ALE_SYSCTL_STAT_ADD32(ctx, child, "good_bcast_frames", 914 &stats->tx_bcast_frames, "Good broadcast frames"); 915 ALE_SYSCTL_STAT_ADD32(ctx, child, "good_mcast_frames", 916 &stats->tx_mcast_frames, "Good multicast frames"); 917 ALE_SYSCTL_STAT_ADD32(ctx, child, "pause_frames", 918 &stats->tx_pause_frames, "Pause control frames"); 919 ALE_SYSCTL_STAT_ADD32(ctx, child, "control_frames", 920 &stats->tx_control_frames, "Control frames"); 921 ALE_SYSCTL_STAT_ADD32(ctx, child, "excess_defers", 922 &stats->tx_excess_defer, "Frames with excessive derferrals"); 923 ALE_SYSCTL_STAT_ADD32(ctx, child, "defers", 924 &stats->tx_excess_defer, "Frames with derferrals"); 925 ALE_SYSCTL_STAT_ADD64(ctx, child, "good_octets", 926 &stats->tx_bytes, "Good octets"); 927 ALE_SYSCTL_STAT_ADD64(ctx, child, "good_bcast_octets", 928 &stats->tx_bcast_bytes, "Good broadcast octets"); 929 ALE_SYSCTL_STAT_ADD64(ctx, child, "good_mcast_octets", 930 &stats->tx_mcast_bytes, "Good multicast octets"); 931 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_64", 932 &stats->tx_pkts_64, "64 bytes frames"); 933 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_65_127", 934 &stats->tx_pkts_65_127, "65 to 127 bytes frames"); 935 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_128_255", 936 &stats->tx_pkts_128_255, "128 to 255 bytes frames"); 937 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_256_511", 938 &stats->tx_pkts_256_511, "256 to 511 bytes frames"); 939 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_512_1023", 940 &stats->tx_pkts_512_1023, "512 to 1023 bytes frames"); 941 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_1024_1518", 942 &stats->tx_pkts_1024_1518, "1024 to 1518 bytes frames"); 943 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_1519_max", 944 &stats->tx_pkts_1519_max, "1519 to max frames"); 945 ALE_SYSCTL_STAT_ADD32(ctx, child, "single_colls", 946 &stats->tx_single_colls, "Single collisions"); 947 ALE_SYSCTL_STAT_ADD32(ctx, child, "multi_colls", 948 &stats->tx_multi_colls, "Multiple collisions"); 949 ALE_SYSCTL_STAT_ADD32(ctx, child, "late_colls", 950 &stats->tx_late_colls, "Late collisions"); 951 ALE_SYSCTL_STAT_ADD32(ctx, child, "excess_colls", 952 &stats->tx_excess_colls, "Excessive collisions"); 953 ALE_SYSCTL_STAT_ADD32(ctx, child, "underruns", 954 &stats->tx_underrun, "FIFO underruns"); 955 ALE_SYSCTL_STAT_ADD32(ctx, child, "desc_underruns", 956 &stats->tx_desc_underrun, "Descriptor write-back errors"); 957 ALE_SYSCTL_STAT_ADD32(ctx, child, "len_errs", 958 &stats->tx_lenerrs, "Frames with length mismatched"); 959 ALE_SYSCTL_STAT_ADD32(ctx, child, "trunc_errs", 960 &stats->tx_pkts_truncated, "Truncated frames due to MTU size"); 961} 962 963#undef ALE_SYSCTL_STAT_ADD32 964#undef ALE_SYSCTL_STAT_ADD64 965 966struct ale_dmamap_arg { 967 bus_addr_t ale_busaddr; 968}; 969 970static void 971ale_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 972{ 973 struct ale_dmamap_arg *ctx; 974 975 if (error != 0) 976 return; 977 978 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 979 980 ctx = (struct ale_dmamap_arg *)arg; 981 ctx->ale_busaddr = segs[0].ds_addr; 982} 983 984/* 985 * Tx descriptors/RXF0/CMB DMA blocks share ALE_DESC_ADDR_HI register 986 * which specifies high address region of DMA blocks. Therefore these 987 * blocks should have the same high address of given 4GB address 988 * space(i.e. crossing 4GB boundary is not allowed). 989 */ 990static int 991ale_check_boundary(struct ale_softc *sc) 992{ 993 bus_addr_t rx_cmb_end[ALE_RX_PAGES], tx_cmb_end; 994 bus_addr_t rx_page_end[ALE_RX_PAGES], tx_ring_end; 995 996 rx_page_end[0] = sc->ale_cdata.ale_rx_page[0].page_paddr + 997 sc->ale_pagesize; 998 rx_page_end[1] = sc->ale_cdata.ale_rx_page[1].page_paddr + 999 sc->ale_pagesize; 1000 tx_ring_end = sc->ale_cdata.ale_tx_ring_paddr + ALE_TX_RING_SZ; 1001 tx_cmb_end = sc->ale_cdata.ale_tx_cmb_paddr + ALE_TX_CMB_SZ; 1002 rx_cmb_end[0] = sc->ale_cdata.ale_rx_page[0].cmb_paddr + ALE_RX_CMB_SZ; 1003 rx_cmb_end[1] = sc->ale_cdata.ale_rx_page[1].cmb_paddr + ALE_RX_CMB_SZ; 1004 1005 if ((ALE_ADDR_HI(tx_ring_end) != 1006 ALE_ADDR_HI(sc->ale_cdata.ale_tx_ring_paddr)) || 1007 (ALE_ADDR_HI(rx_page_end[0]) != 1008 ALE_ADDR_HI(sc->ale_cdata.ale_rx_page[0].page_paddr)) || 1009 (ALE_ADDR_HI(rx_page_end[1]) != 1010 ALE_ADDR_HI(sc->ale_cdata.ale_rx_page[1].page_paddr)) || 1011 (ALE_ADDR_HI(tx_cmb_end) != 1012 ALE_ADDR_HI(sc->ale_cdata.ale_tx_cmb_paddr)) || 1013 (ALE_ADDR_HI(rx_cmb_end[0]) != 1014 ALE_ADDR_HI(sc->ale_cdata.ale_rx_page[0].cmb_paddr)) || 1015 (ALE_ADDR_HI(rx_cmb_end[1]) != 1016 ALE_ADDR_HI(sc->ale_cdata.ale_rx_page[1].cmb_paddr))) 1017 return (EFBIG); 1018 1019 if ((ALE_ADDR_HI(tx_ring_end) != ALE_ADDR_HI(rx_page_end[0])) || 1020 (ALE_ADDR_HI(tx_ring_end) != ALE_ADDR_HI(rx_page_end[1])) || 1021 (ALE_ADDR_HI(tx_ring_end) != ALE_ADDR_HI(rx_cmb_end[0])) || 1022 (ALE_ADDR_HI(tx_ring_end) != ALE_ADDR_HI(rx_cmb_end[1])) || 1023 (ALE_ADDR_HI(tx_ring_end) != ALE_ADDR_HI(tx_cmb_end))) 1024 return (EFBIG); 1025 1026 return (0); 1027} 1028 1029static int 1030ale_dma_alloc(struct ale_softc *sc) 1031{ 1032 struct ale_txdesc *txd; 1033 bus_addr_t lowaddr; 1034 struct ale_dmamap_arg ctx; 1035 int error, guard_size, i; 1036 1037 if ((sc->ale_flags & ALE_FLAG_JUMBO) != 0) 1038 guard_size = ALE_JUMBO_FRAMELEN; 1039 else 1040 guard_size = ALE_MAX_FRAMELEN; 1041 sc->ale_pagesize = roundup(guard_size + ALE_RX_PAGE_SZ, 1042 ALE_RX_PAGE_ALIGN); 1043 lowaddr = BUS_SPACE_MAXADDR; 1044again: 1045 /* Create parent DMA tag. */ 1046 error = bus_dma_tag_create( 1047 bus_get_dma_tag(sc->ale_dev), /* parent */ 1048 1, 0, /* alignment, boundary */ 1049 lowaddr, /* lowaddr */ 1050 BUS_SPACE_MAXADDR, /* highaddr */ 1051 NULL, NULL, /* filter, filterarg */ 1052 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 1053 0, /* nsegments */ 1054 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 1055 0, /* flags */ 1056 NULL, NULL, /* lockfunc, lockarg */ 1057 &sc->ale_cdata.ale_parent_tag); 1058 if (error != 0) { 1059 device_printf(sc->ale_dev, 1060 "could not create parent DMA tag.\n"); 1061 goto fail; 1062 } 1063 1064 /* Create DMA tag for Tx descriptor ring. */ 1065 error = bus_dma_tag_create( 1066 sc->ale_cdata.ale_parent_tag, /* parent */ 1067 ALE_TX_RING_ALIGN, 0, /* alignment, boundary */ 1068 BUS_SPACE_MAXADDR, /* lowaddr */ 1069 BUS_SPACE_MAXADDR, /* highaddr */ 1070 NULL, NULL, /* filter, filterarg */ 1071 ALE_TX_RING_SZ, /* maxsize */ 1072 1, /* nsegments */ 1073 ALE_TX_RING_SZ, /* maxsegsize */ 1074 0, /* flags */ 1075 NULL, NULL, /* lockfunc, lockarg */ 1076 &sc->ale_cdata.ale_tx_ring_tag); 1077 if (error != 0) { 1078 device_printf(sc->ale_dev, 1079 "could not create Tx ring DMA tag.\n"); 1080 goto fail; 1081 } 1082 1083 /* Create DMA tag for Rx pages. */ 1084 for (i = 0; i < ALE_RX_PAGES; i++) { 1085 error = bus_dma_tag_create( 1086 sc->ale_cdata.ale_parent_tag, /* parent */ 1087 ALE_RX_PAGE_ALIGN, 0, /* alignment, boundary */ 1088 BUS_SPACE_MAXADDR, /* lowaddr */ 1089 BUS_SPACE_MAXADDR, /* highaddr */ 1090 NULL, NULL, /* filter, filterarg */ 1091 sc->ale_pagesize, /* maxsize */ 1092 1, /* nsegments */ 1093 sc->ale_pagesize, /* maxsegsize */ 1094 0, /* flags */ 1095 NULL, NULL, /* lockfunc, lockarg */ 1096 &sc->ale_cdata.ale_rx_page[i].page_tag); 1097 if (error != 0) { 1098 device_printf(sc->ale_dev, 1099 "could not create Rx page %d DMA tag.\n", i); 1100 goto fail; 1101 } 1102 } 1103 1104 /* Create DMA tag for Tx coalescing message block. */ 1105 error = bus_dma_tag_create( 1106 sc->ale_cdata.ale_parent_tag, /* parent */ 1107 ALE_CMB_ALIGN, 0, /* alignment, boundary */ 1108 BUS_SPACE_MAXADDR, /* lowaddr */ 1109 BUS_SPACE_MAXADDR, /* highaddr */ 1110 NULL, NULL, /* filter, filterarg */ 1111 ALE_TX_CMB_SZ, /* maxsize */ 1112 1, /* nsegments */ 1113 ALE_TX_CMB_SZ, /* maxsegsize */ 1114 0, /* flags */ 1115 NULL, NULL, /* lockfunc, lockarg */ 1116 &sc->ale_cdata.ale_tx_cmb_tag); 1117 if (error != 0) { 1118 device_printf(sc->ale_dev, 1119 "could not create Tx CMB DMA tag.\n"); 1120 goto fail; 1121 } 1122 1123 /* Create DMA tag for Rx coalescing message block. */ 1124 for (i = 0; i < ALE_RX_PAGES; i++) { 1125 error = bus_dma_tag_create( 1126 sc->ale_cdata.ale_parent_tag, /* parent */ 1127 ALE_CMB_ALIGN, 0, /* alignment, boundary */ 1128 BUS_SPACE_MAXADDR, /* lowaddr */ 1129 BUS_SPACE_MAXADDR, /* highaddr */ 1130 NULL, NULL, /* filter, filterarg */ 1131 ALE_RX_CMB_SZ, /* maxsize */ 1132 1, /* nsegments */ 1133 ALE_RX_CMB_SZ, /* maxsegsize */ 1134 0, /* flags */ 1135 NULL, NULL, /* lockfunc, lockarg */ 1136 &sc->ale_cdata.ale_rx_page[i].cmb_tag); 1137 if (error != 0) { 1138 device_printf(sc->ale_dev, 1139 "could not create Rx page %d CMB DMA tag.\n", i); 1140 goto fail; 1141 } 1142 } 1143 1144 /* Allocate DMA'able memory and load the DMA map for Tx ring. */ 1145 error = bus_dmamem_alloc(sc->ale_cdata.ale_tx_ring_tag, 1146 (void **)&sc->ale_cdata.ale_tx_ring, 1147 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1148 &sc->ale_cdata.ale_tx_ring_map); 1149 if (error != 0) { 1150 device_printf(sc->ale_dev, 1151 "could not allocate DMA'able memory for Tx ring.\n"); 1152 goto fail; 1153 } 1154 ctx.ale_busaddr = 0; 1155 error = bus_dmamap_load(sc->ale_cdata.ale_tx_ring_tag, 1156 sc->ale_cdata.ale_tx_ring_map, sc->ale_cdata.ale_tx_ring, 1157 ALE_TX_RING_SZ, ale_dmamap_cb, &ctx, 0); 1158 if (error != 0 || ctx.ale_busaddr == 0) { 1159 device_printf(sc->ale_dev, 1160 "could not load DMA'able memory for Tx ring.\n"); 1161 goto fail; 1162 } 1163 sc->ale_cdata.ale_tx_ring_paddr = ctx.ale_busaddr; 1164 1165 /* Rx pages. */ 1166 for (i = 0; i < ALE_RX_PAGES; i++) { 1167 error = bus_dmamem_alloc(sc->ale_cdata.ale_rx_page[i].page_tag, 1168 (void **)&sc->ale_cdata.ale_rx_page[i].page_addr, 1169 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1170 &sc->ale_cdata.ale_rx_page[i].page_map); 1171 if (error != 0) { 1172 device_printf(sc->ale_dev, 1173 "could not allocate DMA'able memory for " 1174 "Rx page %d.\n", i); 1175 goto fail; 1176 } 1177 ctx.ale_busaddr = 0; 1178 error = bus_dmamap_load(sc->ale_cdata.ale_rx_page[i].page_tag, 1179 sc->ale_cdata.ale_rx_page[i].page_map, 1180 sc->ale_cdata.ale_rx_page[i].page_addr, 1181 sc->ale_pagesize, ale_dmamap_cb, &ctx, 0); 1182 if (error != 0 || ctx.ale_busaddr == 0) { 1183 device_printf(sc->ale_dev, 1184 "could not load DMA'able memory for " 1185 "Rx page %d.\n", i); 1186 goto fail; 1187 } 1188 sc->ale_cdata.ale_rx_page[i].page_paddr = ctx.ale_busaddr; 1189 } 1190 1191 /* Tx CMB. */ 1192 error = bus_dmamem_alloc(sc->ale_cdata.ale_tx_cmb_tag, 1193 (void **)&sc->ale_cdata.ale_tx_cmb, 1194 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1195 &sc->ale_cdata.ale_tx_cmb_map); 1196 if (error != 0) { 1197 device_printf(sc->ale_dev, 1198 "could not allocate DMA'able memory for Tx CMB.\n"); 1199 goto fail; 1200 } 1201 ctx.ale_busaddr = 0; 1202 error = bus_dmamap_load(sc->ale_cdata.ale_tx_cmb_tag, 1203 sc->ale_cdata.ale_tx_cmb_map, sc->ale_cdata.ale_tx_cmb, 1204 ALE_TX_CMB_SZ, ale_dmamap_cb, &ctx, 0); 1205 if (error != 0 || ctx.ale_busaddr == 0) { 1206 device_printf(sc->ale_dev, 1207 "could not load DMA'able memory for Tx CMB.\n"); 1208 goto fail; 1209 } 1210 sc->ale_cdata.ale_tx_cmb_paddr = ctx.ale_busaddr; 1211 1212 /* Rx CMB. */ 1213 for (i = 0; i < ALE_RX_PAGES; i++) { 1214 error = bus_dmamem_alloc(sc->ale_cdata.ale_rx_page[i].cmb_tag, 1215 (void **)&sc->ale_cdata.ale_rx_page[i].cmb_addr, 1216 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1217 &sc->ale_cdata.ale_rx_page[i].cmb_map); 1218 if (error != 0) { 1219 device_printf(sc->ale_dev, "could not allocate " 1220 "DMA'able memory for Rx page %d CMB.\n", i); 1221 goto fail; 1222 } 1223 ctx.ale_busaddr = 0; 1224 error = bus_dmamap_load(sc->ale_cdata.ale_rx_page[i].cmb_tag, 1225 sc->ale_cdata.ale_rx_page[i].cmb_map, 1226 sc->ale_cdata.ale_rx_page[i].cmb_addr, 1227 ALE_RX_CMB_SZ, ale_dmamap_cb, &ctx, 0); 1228 if (error != 0 || ctx.ale_busaddr == 0) { 1229 device_printf(sc->ale_dev, "could not load DMA'able " 1230 "memory for Rx page %d CMB.\n", i); 1231 goto fail; 1232 } 1233 sc->ale_cdata.ale_rx_page[i].cmb_paddr = ctx.ale_busaddr; 1234 } 1235 1236 /* 1237 * Tx descriptors/RXF0/CMB DMA blocks share the same 1238 * high address region of 64bit DMA address space. 1239 */ 1240 if (lowaddr != BUS_SPACE_MAXADDR_32BIT && 1241 (error = ale_check_boundary(sc)) != 0) { 1242 device_printf(sc->ale_dev, "4GB boundary crossed, " 1243 "switching to 32bit DMA addressing mode.\n"); 1244 ale_dma_free(sc); 1245 /* 1246 * Limit max allowable DMA address space to 32bit 1247 * and try again. 1248 */ 1249 lowaddr = BUS_SPACE_MAXADDR_32BIT; 1250 goto again; 1251 } 1252 1253 /* 1254 * Create Tx buffer parent tag. 1255 * AR81xx allows 64bit DMA addressing of Tx buffers so it 1256 * needs separate parent DMA tag as parent DMA address space 1257 * could be restricted to be within 32bit address space by 1258 * 4GB boundary crossing. 1259 */ 1260 error = bus_dma_tag_create( 1261 bus_get_dma_tag(sc->ale_dev), /* parent */ 1262 1, 0, /* alignment, boundary */ 1263 BUS_SPACE_MAXADDR, /* lowaddr */ 1264 BUS_SPACE_MAXADDR, /* highaddr */ 1265 NULL, NULL, /* filter, filterarg */ 1266 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 1267 0, /* nsegments */ 1268 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 1269 0, /* flags */ 1270 NULL, NULL, /* lockfunc, lockarg */ 1271 &sc->ale_cdata.ale_buffer_tag); 1272 if (error != 0) { 1273 device_printf(sc->ale_dev, 1274 "could not create parent buffer DMA tag.\n"); 1275 goto fail; 1276 } 1277 1278 /* Create DMA tag for Tx buffers. */ 1279 error = bus_dma_tag_create( 1280 sc->ale_cdata.ale_buffer_tag, /* parent */ 1281 1, 0, /* alignment, boundary */ 1282 BUS_SPACE_MAXADDR, /* lowaddr */ 1283 BUS_SPACE_MAXADDR, /* highaddr */ 1284 NULL, NULL, /* filter, filterarg */ 1285 ALE_TSO_MAXSIZE, /* maxsize */ 1286 ALE_MAXTXSEGS, /* nsegments */ 1287 ALE_TSO_MAXSEGSIZE, /* maxsegsize */ 1288 0, /* flags */ 1289 NULL, NULL, /* lockfunc, lockarg */ 1290 &sc->ale_cdata.ale_tx_tag); 1291 if (error != 0) { 1292 device_printf(sc->ale_dev, "could not create Tx DMA tag.\n"); 1293 goto fail; 1294 } 1295 1296 /* Create DMA maps for Tx buffers. */ 1297 for (i = 0; i < ALE_TX_RING_CNT; i++) { 1298 txd = &sc->ale_cdata.ale_txdesc[i]; 1299 txd->tx_m = NULL; 1300 txd->tx_dmamap = NULL; 1301 error = bus_dmamap_create(sc->ale_cdata.ale_tx_tag, 0, 1302 &txd->tx_dmamap); 1303 if (error != 0) { 1304 device_printf(sc->ale_dev, 1305 "could not create Tx dmamap.\n"); 1306 goto fail; 1307 } 1308 } 1309 1310fail: 1311 return (error); 1312} 1313 1314static void 1315ale_dma_free(struct ale_softc *sc) 1316{ 1317 struct ale_txdesc *txd; 1318 int i; 1319 1320 /* Tx buffers. */ 1321 if (sc->ale_cdata.ale_tx_tag != NULL) { 1322 for (i = 0; i < ALE_TX_RING_CNT; i++) { 1323 txd = &sc->ale_cdata.ale_txdesc[i]; 1324 if (txd->tx_dmamap != NULL) { 1325 bus_dmamap_destroy(sc->ale_cdata.ale_tx_tag, 1326 txd->tx_dmamap); 1327 txd->tx_dmamap = NULL; 1328 } 1329 } 1330 bus_dma_tag_destroy(sc->ale_cdata.ale_tx_tag); 1331 sc->ale_cdata.ale_tx_tag = NULL; 1332 } 1333 /* Tx descriptor ring. */ 1334 if (sc->ale_cdata.ale_tx_ring_tag != NULL) { 1335 if (sc->ale_cdata.ale_tx_ring_paddr != 0) 1336 bus_dmamap_unload(sc->ale_cdata.ale_tx_ring_tag, 1337 sc->ale_cdata.ale_tx_ring_map); 1338 if (sc->ale_cdata.ale_tx_ring != NULL) 1339 bus_dmamem_free(sc->ale_cdata.ale_tx_ring_tag, 1340 sc->ale_cdata.ale_tx_ring, 1341 sc->ale_cdata.ale_tx_ring_map); 1342 sc->ale_cdata.ale_tx_ring_paddr = 0; 1343 sc->ale_cdata.ale_tx_ring = NULL; 1344 bus_dma_tag_destroy(sc->ale_cdata.ale_tx_ring_tag); 1345 sc->ale_cdata.ale_tx_ring_tag = NULL; 1346 } 1347 /* Rx page block. */ 1348 for (i = 0; i < ALE_RX_PAGES; i++) { 1349 if (sc->ale_cdata.ale_rx_page[i].page_tag != NULL) { 1350 if (sc->ale_cdata.ale_rx_page[i].page_paddr != 0) 1351 bus_dmamap_unload( 1352 sc->ale_cdata.ale_rx_page[i].page_tag, 1353 sc->ale_cdata.ale_rx_page[i].page_map); 1354 if (sc->ale_cdata.ale_rx_page[i].page_addr != NULL) 1355 bus_dmamem_free( 1356 sc->ale_cdata.ale_rx_page[i].page_tag, 1357 sc->ale_cdata.ale_rx_page[i].page_addr, 1358 sc->ale_cdata.ale_rx_page[i].page_map); 1359 sc->ale_cdata.ale_rx_page[i].page_paddr = 0; 1360 sc->ale_cdata.ale_rx_page[i].page_addr = NULL; 1361 bus_dma_tag_destroy( 1362 sc->ale_cdata.ale_rx_page[i].page_tag); 1363 sc->ale_cdata.ale_rx_page[i].page_tag = NULL; 1364 } 1365 } 1366 /* Rx CMB. */ 1367 for (i = 0; i < ALE_RX_PAGES; i++) { 1368 if (sc->ale_cdata.ale_rx_page[i].cmb_tag != NULL) { 1369 if (sc->ale_cdata.ale_rx_page[i].cmb_paddr != 0) 1370 bus_dmamap_unload( 1371 sc->ale_cdata.ale_rx_page[i].cmb_tag, 1372 sc->ale_cdata.ale_rx_page[i].cmb_map); 1373 if (sc->ale_cdata.ale_rx_page[i].cmb_addr != NULL) 1374 bus_dmamem_free( 1375 sc->ale_cdata.ale_rx_page[i].cmb_tag, 1376 sc->ale_cdata.ale_rx_page[i].cmb_addr, 1377 sc->ale_cdata.ale_rx_page[i].cmb_map); 1378 sc->ale_cdata.ale_rx_page[i].cmb_paddr = 0; 1379 sc->ale_cdata.ale_rx_page[i].cmb_addr = NULL; 1380 bus_dma_tag_destroy( 1381 sc->ale_cdata.ale_rx_page[i].cmb_tag); 1382 sc->ale_cdata.ale_rx_page[i].cmb_tag = NULL; 1383 } 1384 } 1385 /* Tx CMB. */ 1386 if (sc->ale_cdata.ale_tx_cmb_tag != NULL) { 1387 if (sc->ale_cdata.ale_tx_cmb_paddr != 0) 1388 bus_dmamap_unload(sc->ale_cdata.ale_tx_cmb_tag, 1389 sc->ale_cdata.ale_tx_cmb_map); 1390 if (sc->ale_cdata.ale_tx_cmb != NULL) 1391 bus_dmamem_free(sc->ale_cdata.ale_tx_cmb_tag, 1392 sc->ale_cdata.ale_tx_cmb, 1393 sc->ale_cdata.ale_tx_cmb_map); 1394 sc->ale_cdata.ale_tx_cmb_paddr = 0; 1395 sc->ale_cdata.ale_tx_cmb = NULL; 1396 bus_dma_tag_destroy(sc->ale_cdata.ale_tx_cmb_tag); 1397 sc->ale_cdata.ale_tx_cmb_tag = NULL; 1398 } 1399 if (sc->ale_cdata.ale_buffer_tag != NULL) { 1400 bus_dma_tag_destroy(sc->ale_cdata.ale_buffer_tag); 1401 sc->ale_cdata.ale_buffer_tag = NULL; 1402 } 1403 if (sc->ale_cdata.ale_parent_tag != NULL) { 1404 bus_dma_tag_destroy(sc->ale_cdata.ale_parent_tag); 1405 sc->ale_cdata.ale_parent_tag = NULL; 1406 } 1407} 1408 1409static int 1410ale_shutdown(device_t dev) 1411{ 1412 1413 return (ale_suspend(dev)); 1414} 1415 1416/* 1417 * Note, this driver resets the link speed to 10/100Mbps by 1418 * restarting auto-negotiation in suspend/shutdown phase but we 1419 * don't know whether that auto-negotiation would succeed or not 1420 * as driver has no control after powering off/suspend operation. 1421 * If the renegotiation fail WOL may not work. Running at 1Gbps 1422 * will draw more power than 375mA at 3.3V which is specified in 1423 * PCI specification and that would result in complete 1424 * shutdowning power to ethernet controller. 1425 * 1426 * TODO 1427 * Save current negotiated media speed/duplex/flow-control to 1428 * softc and restore the same link again after resuming. PHY 1429 * handling such as power down/resetting to 100Mbps may be better 1430 * handled in suspend method in phy driver. 1431 */ 1432static void 1433ale_setlinkspeed(struct ale_softc *sc) 1434{ 1435 struct mii_data *mii; 1436 int aneg, i; 1437 1438 mii = device_get_softc(sc->ale_miibus); 1439 mii_pollstat(mii); 1440 aneg = 0; 1441 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 1442 (IFM_ACTIVE | IFM_AVALID)) { 1443 switch IFM_SUBTYPE(mii->mii_media_active) { 1444 case IFM_10_T: 1445 case IFM_100_TX: 1446 return; 1447 case IFM_1000_T: 1448 aneg++; 1449 break; 1450 default: 1451 break; 1452 } 1453 } 1454 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, MII_100T2CR, 0); 1455 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 1456 MII_ANAR, ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10 | ANAR_CSMA); 1457 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 1458 MII_BMCR, BMCR_RESET | BMCR_AUTOEN | BMCR_STARTNEG); 1459 DELAY(1000); 1460 if (aneg != 0) { 1461 /* 1462 * Poll link state until ale(4) get a 10/100Mbps link. 1463 */ 1464 for (i = 0; i < MII_ANEGTICKS_GIGE; i++) { 1465 mii_pollstat(mii); 1466 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) 1467 == (IFM_ACTIVE | IFM_AVALID)) { 1468 switch (IFM_SUBTYPE( 1469 mii->mii_media_active)) { 1470 case IFM_10_T: 1471 case IFM_100_TX: 1472 ale_mac_config(sc); 1473 return; 1474 default: 1475 break; 1476 } 1477 } 1478 ALE_UNLOCK(sc); 1479 pause("alelnk", hz); 1480 ALE_LOCK(sc); 1481 } 1482 if (i == MII_ANEGTICKS_GIGE) 1483 device_printf(sc->ale_dev, 1484 "establishing a link failed, WOL may not work!"); 1485 } 1486 /* 1487 * No link, force MAC to have 100Mbps, full-duplex link. 1488 * This is the last resort and may/may not work. 1489 */ 1490 mii->mii_media_status = IFM_AVALID | IFM_ACTIVE; 1491 mii->mii_media_active = IFM_ETHER | IFM_100_TX | IFM_FDX; 1492 ale_mac_config(sc); 1493} 1494 1495static void 1496ale_setwol(struct ale_softc *sc) 1497{ 1498 struct ifnet *ifp; 1499 uint32_t reg, pmcs; 1500 uint16_t pmstat; 1501 int pmc; 1502 1503 ALE_LOCK_ASSERT(sc); 1504 1505 if (pci_find_cap(sc->ale_dev, PCIY_PMG, &pmc) != 0) { 1506 /* Disable WOL. */ 1507 CSR_WRITE_4(sc, ALE_WOL_CFG, 0); 1508 reg = CSR_READ_4(sc, ALE_PCIE_PHYMISC); 1509 reg |= PCIE_PHYMISC_FORCE_RCV_DET; 1510 CSR_WRITE_4(sc, ALE_PCIE_PHYMISC, reg); 1511 /* Force PHY power down. */ 1512 CSR_WRITE_2(sc, ALE_GPHY_CTRL, 1513 GPHY_CTRL_EXT_RESET | GPHY_CTRL_HIB_EN | 1514 GPHY_CTRL_HIB_PULSE | GPHY_CTRL_PHY_PLL_ON | 1515 GPHY_CTRL_SEL_ANA_RESET | GPHY_CTRL_PHY_IDDQ | 1516 GPHY_CTRL_PCLK_SEL_DIS | GPHY_CTRL_PWDOWN_HW); 1517 return; 1518 } 1519 1520 ifp = sc->ale_ifp; 1521 if ((ifp->if_capenable & IFCAP_WOL) != 0) { 1522 if ((sc->ale_flags & ALE_FLAG_FASTETHER) == 0) 1523 ale_setlinkspeed(sc); 1524 } 1525 1526 pmcs = 0; 1527 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) 1528 pmcs |= WOL_CFG_MAGIC | WOL_CFG_MAGIC_ENB; 1529 CSR_WRITE_4(sc, ALE_WOL_CFG, pmcs); 1530 reg = CSR_READ_4(sc, ALE_MAC_CFG); 1531 reg &= ~(MAC_CFG_DBG | MAC_CFG_PROMISC | MAC_CFG_ALLMULTI | 1532 MAC_CFG_BCAST); 1533 if ((ifp->if_capenable & IFCAP_WOL_MCAST) != 0) 1534 reg |= MAC_CFG_ALLMULTI | MAC_CFG_BCAST; 1535 if ((ifp->if_capenable & IFCAP_WOL) != 0) 1536 reg |= MAC_CFG_RX_ENB; 1537 CSR_WRITE_4(sc, ALE_MAC_CFG, reg); 1538 1539 if ((ifp->if_capenable & IFCAP_WOL) == 0) { 1540 /* WOL disabled, PHY power down. */ 1541 reg = CSR_READ_4(sc, ALE_PCIE_PHYMISC); 1542 reg |= PCIE_PHYMISC_FORCE_RCV_DET; 1543 CSR_WRITE_4(sc, ALE_PCIE_PHYMISC, reg); 1544 CSR_WRITE_2(sc, ALE_GPHY_CTRL, 1545 GPHY_CTRL_EXT_RESET | GPHY_CTRL_HIB_EN | 1546 GPHY_CTRL_HIB_PULSE | GPHY_CTRL_SEL_ANA_RESET | 1547 GPHY_CTRL_PHY_IDDQ | GPHY_CTRL_PCLK_SEL_DIS | 1548 GPHY_CTRL_PWDOWN_HW); 1549 } 1550 /* Request PME. */ 1551 pmstat = pci_read_config(sc->ale_dev, pmc + PCIR_POWER_STATUS, 2); 1552 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); 1553 if ((ifp->if_capenable & IFCAP_WOL) != 0) 1554 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 1555 pci_write_config(sc->ale_dev, pmc + PCIR_POWER_STATUS, pmstat, 2); 1556} 1557 1558static int 1559ale_suspend(device_t dev) 1560{ 1561 struct ale_softc *sc; 1562 1563 sc = device_get_softc(dev); 1564 1565 ALE_LOCK(sc); 1566 ale_stop(sc); 1567 ale_setwol(sc); 1568 ALE_UNLOCK(sc); 1569 1570 return (0); 1571} 1572 1573static int 1574ale_resume(device_t dev) 1575{ 1576 struct ale_softc *sc; 1577 struct ifnet *ifp; 1578 int pmc; 1579 uint16_t pmstat; 1580 1581 sc = device_get_softc(dev); 1582 1583 ALE_LOCK(sc); 1584 if (pci_find_cap(sc->ale_dev, PCIY_PMG, &pmc) == 0) { 1585 /* Disable PME and clear PME status. */ 1586 pmstat = pci_read_config(sc->ale_dev, 1587 pmc + PCIR_POWER_STATUS, 2); 1588 if ((pmstat & PCIM_PSTAT_PMEENABLE) != 0) { 1589 pmstat &= ~PCIM_PSTAT_PMEENABLE; 1590 pci_write_config(sc->ale_dev, 1591 pmc + PCIR_POWER_STATUS, pmstat, 2); 1592 } 1593 } 1594 /* Reset PHY. */ 1595 ale_phy_reset(sc); 1596 ifp = sc->ale_ifp; 1597 if ((ifp->if_flags & IFF_UP) != 0) { 1598 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1599 ale_init_locked(sc); 1600 } 1601 ALE_UNLOCK(sc); 1602 1603 return (0); 1604} 1605 1606static int 1607ale_encap(struct ale_softc *sc, struct mbuf **m_head) 1608{ 1609 struct ale_txdesc *txd, *txd_last; 1610 struct tx_desc *desc; 1611 struct mbuf *m; 1612 struct ip *ip; 1613 struct tcphdr *tcp; 1614 bus_dma_segment_t txsegs[ALE_MAXTXSEGS]; 1615 bus_dmamap_t map; 1616 uint32_t cflags, hdrlen, ip_off, poff, vtag; 1617 int error, i, nsegs, prod, si; 1618 1619 ALE_LOCK_ASSERT(sc); 1620 1621 M_ASSERTPKTHDR((*m_head)); 1622 1623 m = *m_head; 1624 ip = NULL; 1625 tcp = NULL; 1626 cflags = vtag = 0; 1627 ip_off = poff = 0; 1628 if ((m->m_pkthdr.csum_flags & (ALE_CSUM_FEATURES | CSUM_TSO)) != 0) { 1629 /* 1630 * AR81xx requires offset of TCP/UDP payload in its Tx 1631 * descriptor to perform hardware Tx checksum offload. 1632 * Additionally, TSO requires IP/TCP header size and 1633 * modification of IP/TCP header in order to make TSO 1634 * engine work. This kind of operation takes many CPU 1635 * cycles on FreeBSD so fast host CPU is required to 1636 * get smooth TSO performance. 1637 */ 1638 struct ether_header *eh; 1639 1640 if (M_WRITABLE(m) == 0) { 1641 /* Get a writable copy. */ 1642 m = m_dup(*m_head, M_NOWAIT); 1643 /* Release original mbufs. */ 1644 m_freem(*m_head); 1645 if (m == NULL) { 1646 *m_head = NULL; 1647 return (ENOBUFS); 1648 } 1649 *m_head = m; 1650 } 1651 1652 /* 1653 * Buggy-controller requires 4 byte aligned Tx buffer 1654 * to make custom checksum offload work. 1655 */ 1656 if ((sc->ale_flags & ALE_FLAG_TXCSUM_BUG) != 0 && 1657 (m->m_pkthdr.csum_flags & ALE_CSUM_FEATURES) != 0 && 1658 (mtod(m, intptr_t) & 3) != 0) { 1659 m = m_defrag(*m_head, M_NOWAIT); 1660 if (m == NULL) { 1661 m_freem(*m_head); 1662 *m_head = NULL; 1663 return (ENOBUFS); 1664 } 1665 *m_head = m; 1666 } 1667 1668 ip_off = sizeof(struct ether_header); 1669 m = m_pullup(m, ip_off); 1670 if (m == NULL) { 1671 *m_head = NULL; 1672 return (ENOBUFS); 1673 } 1674 eh = mtod(m, struct ether_header *); 1675 /* 1676 * Check if hardware VLAN insertion is off. 1677 * Additional check for LLC/SNAP frame? 1678 */ 1679 if (eh->ether_type == htons(ETHERTYPE_VLAN)) { 1680 ip_off = sizeof(struct ether_vlan_header); 1681 m = m_pullup(m, ip_off); 1682 if (m == NULL) { 1683 *m_head = NULL; 1684 return (ENOBUFS); 1685 } 1686 } 1687 m = m_pullup(m, ip_off + sizeof(struct ip)); 1688 if (m == NULL) { 1689 *m_head = NULL; 1690 return (ENOBUFS); 1691 } 1692 ip = (struct ip *)(mtod(m, char *) + ip_off); 1693 poff = ip_off + (ip->ip_hl << 2); 1694 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 1695 /* 1696 * XXX 1697 * AR81xx requires the first descriptor should 1698 * not include any TCP playload for TSO case. 1699 * (i.e. ethernet header + IP + TCP header only) 1700 * m_pullup(9) above will ensure this too. 1701 * However it's not correct if the first mbuf 1702 * of the chain does not use cluster. 1703 */ 1704 m = m_pullup(m, poff + sizeof(struct tcphdr)); 1705 if (m == NULL) { 1706 *m_head = NULL; 1707 return (ENOBUFS); 1708 } 1709 ip = (struct ip *)(mtod(m, char *) + ip_off); 1710 tcp = (struct tcphdr *)(mtod(m, char *) + poff); 1711 m = m_pullup(m, poff + (tcp->th_off << 2)); 1712 if (m == NULL) { 1713 *m_head = NULL; 1714 return (ENOBUFS); 1715 } 1716 /* 1717 * AR81xx requires IP/TCP header size and offset as 1718 * well as TCP pseudo checksum which complicates 1719 * TSO configuration. I guess this comes from the 1720 * adherence to Microsoft NDIS Large Send 1721 * specification which requires insertion of 1722 * pseudo checksum by upper stack. The pseudo 1723 * checksum that NDIS refers to doesn't include 1724 * TCP payload length so ale(4) should recompute 1725 * the pseudo checksum here. Hopefully this wouldn't 1726 * be much burden on modern CPUs. 1727 * Reset IP checksum and recompute TCP pseudo 1728 * checksum as NDIS specification said. 1729 */ 1730 ip->ip_sum = 0; 1731 tcp->th_sum = in_pseudo(ip->ip_src.s_addr, 1732 ip->ip_dst.s_addr, htons(IPPROTO_TCP)); 1733 } 1734 *m_head = m; 1735 } 1736 1737 si = prod = sc->ale_cdata.ale_tx_prod; 1738 txd = &sc->ale_cdata.ale_txdesc[prod]; 1739 txd_last = txd; 1740 map = txd->tx_dmamap; 1741 1742 error = bus_dmamap_load_mbuf_sg(sc->ale_cdata.ale_tx_tag, map, 1743 *m_head, txsegs, &nsegs, 0); 1744 if (error == EFBIG) { 1745 m = m_collapse(*m_head, M_NOWAIT, ALE_MAXTXSEGS); 1746 if (m == NULL) { 1747 m_freem(*m_head); 1748 *m_head = NULL; 1749 return (ENOMEM); 1750 } 1751 *m_head = m; 1752 error = bus_dmamap_load_mbuf_sg(sc->ale_cdata.ale_tx_tag, map, 1753 *m_head, txsegs, &nsegs, 0); 1754 if (error != 0) { 1755 m_freem(*m_head); 1756 *m_head = NULL; 1757 return (error); 1758 } 1759 } else if (error != 0) 1760 return (error); 1761 if (nsegs == 0) { 1762 m_freem(*m_head); 1763 *m_head = NULL; 1764 return (EIO); 1765 } 1766 1767 /* Check descriptor overrun. */ 1768 if (sc->ale_cdata.ale_tx_cnt + nsegs >= ALE_TX_RING_CNT - 3) { 1769 bus_dmamap_unload(sc->ale_cdata.ale_tx_tag, map); 1770 return (ENOBUFS); 1771 } 1772 bus_dmamap_sync(sc->ale_cdata.ale_tx_tag, map, BUS_DMASYNC_PREWRITE); 1773 1774 m = *m_head; 1775 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 1776 /* Request TSO and set MSS. */ 1777 cflags |= ALE_TD_TSO; 1778 cflags |= ((uint32_t)m->m_pkthdr.tso_segsz << ALE_TD_MSS_SHIFT); 1779 /* Set IP/TCP header size. */ 1780 cflags |= ip->ip_hl << ALE_TD_IPHDR_LEN_SHIFT; 1781 cflags |= tcp->th_off << ALE_TD_TCPHDR_LEN_SHIFT; 1782 } else if ((m->m_pkthdr.csum_flags & ALE_CSUM_FEATURES) != 0) { 1783 /* 1784 * AR81xx supports Tx custom checksum offload feature 1785 * that offloads single 16bit checksum computation. 1786 * So you can choose one among IP, TCP and UDP. 1787 * Normally driver sets checksum start/insertion 1788 * position from the information of TCP/UDP frame as 1789 * TCP/UDP checksum takes more time than that of IP. 1790 * However it seems that custom checksum offload 1791 * requires 4 bytes aligned Tx buffers due to hardware 1792 * bug. 1793 * AR81xx also supports explicit Tx checksum computation 1794 * if it is told that the size of IP header and TCP 1795 * header(for UDP, the header size does not matter 1796 * because it's fixed length). However with this scheme 1797 * TSO does not work so you have to choose one either 1798 * TSO or explicit Tx checksum offload. I chosen TSO 1799 * plus custom checksum offload with work-around which 1800 * will cover most common usage for this consumer 1801 * ethernet controller. The work-around takes a lot of 1802 * CPU cycles if Tx buffer is not aligned on 4 bytes 1803 * boundary, though. 1804 */ 1805 cflags |= ALE_TD_CXSUM; 1806 /* Set checksum start offset. */ 1807 cflags |= (poff << ALE_TD_CSUM_PLOADOFFSET_SHIFT); 1808 /* Set checksum insertion position of TCP/UDP. */ 1809 cflags |= ((poff + m->m_pkthdr.csum_data) << 1810 ALE_TD_CSUM_XSUMOFFSET_SHIFT); 1811 } 1812 1813 /* Configure VLAN hardware tag insertion. */ 1814 if ((m->m_flags & M_VLANTAG) != 0) { 1815 vtag = ALE_TX_VLAN_TAG(m->m_pkthdr.ether_vtag); 1816 vtag = ((vtag << ALE_TD_VLAN_SHIFT) & ALE_TD_VLAN_MASK); 1817 cflags |= ALE_TD_INSERT_VLAN_TAG; 1818 } 1819 1820 i = 0; 1821 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 1822 /* 1823 * Make sure the first fragment contains 1824 * only ethernet and IP/TCP header with options. 1825 */ 1826 hdrlen = poff + (tcp->th_off << 2); 1827 desc = &sc->ale_cdata.ale_tx_ring[prod]; 1828 desc->addr = htole64(txsegs[i].ds_addr); 1829 desc->len = htole32(ALE_TX_BYTES(hdrlen) | vtag); 1830 desc->flags = htole32(cflags); 1831 sc->ale_cdata.ale_tx_cnt++; 1832 ALE_DESC_INC(prod, ALE_TX_RING_CNT); 1833 if (m->m_len - hdrlen > 0) { 1834 /* Handle remaining payload of the first fragment. */ 1835 desc = &sc->ale_cdata.ale_tx_ring[prod]; 1836 desc->addr = htole64(txsegs[i].ds_addr + hdrlen); 1837 desc->len = htole32(ALE_TX_BYTES(m->m_len - hdrlen) | 1838 vtag); 1839 desc->flags = htole32(cflags); 1840 sc->ale_cdata.ale_tx_cnt++; 1841 ALE_DESC_INC(prod, ALE_TX_RING_CNT); 1842 } 1843 i = 1; 1844 } 1845 for (; i < nsegs; i++) { 1846 desc = &sc->ale_cdata.ale_tx_ring[prod]; 1847 desc->addr = htole64(txsegs[i].ds_addr); 1848 desc->len = htole32(ALE_TX_BYTES(txsegs[i].ds_len) | vtag); 1849 desc->flags = htole32(cflags); 1850 sc->ale_cdata.ale_tx_cnt++; 1851 ALE_DESC_INC(prod, ALE_TX_RING_CNT); 1852 } 1853 /* Update producer index. */ 1854 sc->ale_cdata.ale_tx_prod = prod; 1855 /* Set TSO header on the first descriptor. */ 1856 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 1857 desc = &sc->ale_cdata.ale_tx_ring[si]; 1858 desc->flags |= htole32(ALE_TD_TSO_HDR); 1859 } 1860 1861 /* Finally set EOP on the last descriptor. */ 1862 prod = (prod + ALE_TX_RING_CNT - 1) % ALE_TX_RING_CNT; 1863 desc = &sc->ale_cdata.ale_tx_ring[prod]; 1864 desc->flags |= htole32(ALE_TD_EOP); 1865 1866 /* Swap dmamap of the first and the last. */ 1867 txd = &sc->ale_cdata.ale_txdesc[prod]; 1868 map = txd_last->tx_dmamap; 1869 txd_last->tx_dmamap = txd->tx_dmamap; 1870 txd->tx_dmamap = map; 1871 txd->tx_m = m; 1872 1873 /* Sync descriptors. */ 1874 bus_dmamap_sync(sc->ale_cdata.ale_tx_ring_tag, 1875 sc->ale_cdata.ale_tx_ring_map, 1876 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1877 1878 return (0); 1879} 1880 1881static void 1882ale_start(struct ifnet *ifp) 1883{ 1884 struct ale_softc *sc; 1885 1886 sc = ifp->if_softc; 1887 ALE_LOCK(sc); 1888 ale_start_locked(ifp); 1889 ALE_UNLOCK(sc); 1890} 1891 1892static void 1893ale_start_locked(struct ifnet *ifp) 1894{ 1895 struct ale_softc *sc; 1896 struct mbuf *m_head; 1897 int enq; 1898 1899 sc = ifp->if_softc; 1900 1901 ALE_LOCK_ASSERT(sc); 1902 1903 /* Reclaim transmitted frames. */ 1904 if (sc->ale_cdata.ale_tx_cnt >= ALE_TX_DESC_HIWAT) 1905 ale_txeof(sc); 1906 1907 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 1908 IFF_DRV_RUNNING || (sc->ale_flags & ALE_FLAG_LINK) == 0) 1909 return; 1910 1911 for (enq = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd); ) { 1912 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 1913 if (m_head == NULL) 1914 break; 1915 /* 1916 * Pack the data into the transmit ring. If we 1917 * don't have room, set the OACTIVE flag and wait 1918 * for the NIC to drain the ring. 1919 */ 1920 if (ale_encap(sc, &m_head)) { 1921 if (m_head == NULL) 1922 break; 1923 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 1924 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1925 break; 1926 } 1927 1928 enq++; 1929 /* 1930 * If there's a BPF listener, bounce a copy of this frame 1931 * to him. 1932 */ 1933 ETHER_BPF_MTAP(ifp, m_head); 1934 } 1935 1936 if (enq > 0) { 1937 /* Kick. */ 1938 CSR_WRITE_4(sc, ALE_MBOX_TPD_PROD_IDX, 1939 sc->ale_cdata.ale_tx_prod); 1940 /* Set a timeout in case the chip goes out to lunch. */ 1941 sc->ale_watchdog_timer = ALE_TX_TIMEOUT; 1942 } 1943} 1944 1945static void 1946ale_watchdog(struct ale_softc *sc) 1947{ 1948 struct ifnet *ifp; 1949 1950 ALE_LOCK_ASSERT(sc); 1951 1952 if (sc->ale_watchdog_timer == 0 || --sc->ale_watchdog_timer) 1953 return; 1954 1955 ifp = sc->ale_ifp; 1956 if ((sc->ale_flags & ALE_FLAG_LINK) == 0) { 1957 if_printf(sc->ale_ifp, "watchdog timeout (lost link)\n"); 1958 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 1959 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1960 ale_init_locked(sc); 1961 return; 1962 } 1963 if_printf(sc->ale_ifp, "watchdog timeout -- resetting\n"); 1964 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 1965 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1966 ale_init_locked(sc); 1967 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1968 ale_start_locked(ifp); 1969} 1970 1971static int 1972ale_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1973{ 1974 struct ale_softc *sc; 1975 struct ifreq *ifr; 1976 struct mii_data *mii; 1977 int error, mask; 1978 1979 sc = ifp->if_softc; 1980 ifr = (struct ifreq *)data; 1981 error = 0; 1982 switch (cmd) { 1983 case SIOCSIFMTU: 1984 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > ALE_JUMBO_MTU || 1985 ((sc->ale_flags & ALE_FLAG_JUMBO) == 0 && 1986 ifr->ifr_mtu > ETHERMTU)) 1987 error = EINVAL; 1988 else if (ifp->if_mtu != ifr->ifr_mtu) { 1989 ALE_LOCK(sc); 1990 ifp->if_mtu = ifr->ifr_mtu; 1991 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 1992 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1993 ale_init_locked(sc); 1994 } 1995 ALE_UNLOCK(sc); 1996 } 1997 break; 1998 case SIOCSIFFLAGS: 1999 ALE_LOCK(sc); 2000 if ((ifp->if_flags & IFF_UP) != 0) { 2001 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 2002 if (((ifp->if_flags ^ sc->ale_if_flags) 2003 & (IFF_PROMISC | IFF_ALLMULTI)) != 0) 2004 ale_rxfilter(sc); 2005 } else { 2006 ale_init_locked(sc); 2007 } 2008 } else { 2009 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 2010 ale_stop(sc); 2011 } 2012 sc->ale_if_flags = ifp->if_flags; 2013 ALE_UNLOCK(sc); 2014 break; 2015 case SIOCADDMULTI: 2016 case SIOCDELMULTI: 2017 ALE_LOCK(sc); 2018 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 2019 ale_rxfilter(sc); 2020 ALE_UNLOCK(sc); 2021 break; 2022 case SIOCSIFMEDIA: 2023 case SIOCGIFMEDIA: 2024 mii = device_get_softc(sc->ale_miibus); 2025 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd); 2026 break; 2027 case SIOCSIFCAP: 2028 ALE_LOCK(sc); 2029 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 2030 if ((mask & IFCAP_TXCSUM) != 0 && 2031 (ifp->if_capabilities & IFCAP_TXCSUM) != 0) { 2032 ifp->if_capenable ^= IFCAP_TXCSUM; 2033 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0) 2034 ifp->if_hwassist |= ALE_CSUM_FEATURES; 2035 else 2036 ifp->if_hwassist &= ~ALE_CSUM_FEATURES; 2037 } 2038 if ((mask & IFCAP_RXCSUM) != 0 && 2039 (ifp->if_capabilities & IFCAP_RXCSUM) != 0) 2040 ifp->if_capenable ^= IFCAP_RXCSUM; 2041 if ((mask & IFCAP_TSO4) != 0 && 2042 (ifp->if_capabilities & IFCAP_TSO4) != 0) { 2043 ifp->if_capenable ^= IFCAP_TSO4; 2044 if ((ifp->if_capenable & IFCAP_TSO4) != 0) 2045 ifp->if_hwassist |= CSUM_TSO; 2046 else 2047 ifp->if_hwassist &= ~CSUM_TSO; 2048 } 2049 2050 if ((mask & IFCAP_WOL_MCAST) != 0 && 2051 (ifp->if_capabilities & IFCAP_WOL_MCAST) != 0) 2052 ifp->if_capenable ^= IFCAP_WOL_MCAST; 2053 if ((mask & IFCAP_WOL_MAGIC) != 0 && 2054 (ifp->if_capabilities & IFCAP_WOL_MAGIC) != 0) 2055 ifp->if_capenable ^= IFCAP_WOL_MAGIC; 2056 if ((mask & IFCAP_VLAN_HWCSUM) != 0 && 2057 (ifp->if_capabilities & IFCAP_VLAN_HWCSUM) != 0) 2058 ifp->if_capenable ^= IFCAP_VLAN_HWCSUM; 2059 if ((mask & IFCAP_VLAN_HWTSO) != 0 && 2060 (ifp->if_capabilities & IFCAP_VLAN_HWTSO) != 0) 2061 ifp->if_capenable ^= IFCAP_VLAN_HWTSO; 2062 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 && 2063 (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) != 0) { 2064 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 2065 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) == 0) 2066 ifp->if_capenable &= ~IFCAP_VLAN_HWTSO; 2067 ale_rxvlan(sc); 2068 } 2069 ALE_UNLOCK(sc); 2070 VLAN_CAPABILITIES(ifp); 2071 break; 2072 default: 2073 error = ether_ioctl(ifp, cmd, data); 2074 break; 2075 } 2076 2077 return (error); 2078} 2079 2080static void 2081ale_mac_config(struct ale_softc *sc) 2082{ 2083 struct mii_data *mii; 2084 uint32_t reg; 2085 2086 ALE_LOCK_ASSERT(sc); 2087 2088 mii = device_get_softc(sc->ale_miibus); 2089 reg = CSR_READ_4(sc, ALE_MAC_CFG); 2090 reg &= ~(MAC_CFG_FULL_DUPLEX | MAC_CFG_TX_FC | MAC_CFG_RX_FC | 2091 MAC_CFG_SPEED_MASK); 2092 /* Reprogram MAC with resolved speed/duplex. */ 2093 switch (IFM_SUBTYPE(mii->mii_media_active)) { 2094 case IFM_10_T: 2095 case IFM_100_TX: 2096 reg |= MAC_CFG_SPEED_10_100; 2097 break; 2098 case IFM_1000_T: 2099 reg |= MAC_CFG_SPEED_1000; 2100 break; 2101 } 2102 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 2103 reg |= MAC_CFG_FULL_DUPLEX; 2104 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0) 2105 reg |= MAC_CFG_TX_FC; 2106 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0) 2107 reg |= MAC_CFG_RX_FC; 2108 } 2109 CSR_WRITE_4(sc, ALE_MAC_CFG, reg); 2110} 2111 2112static void 2113ale_stats_clear(struct ale_softc *sc) 2114{ 2115 struct smb sb; 2116 uint32_t *reg; 2117 int i; 2118 2119 for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered; reg++) { 2120 CSR_READ_4(sc, ALE_RX_MIB_BASE + i); 2121 i += sizeof(uint32_t); 2122 } 2123 /* Read Tx statistics. */ 2124 for (reg = &sb.tx_frames, i = 0; reg <= &sb.tx_mcast_bytes; reg++) { 2125 CSR_READ_4(sc, ALE_TX_MIB_BASE + i); 2126 i += sizeof(uint32_t); 2127 } 2128} 2129 2130static void 2131ale_stats_update(struct ale_softc *sc) 2132{ 2133 struct ale_hw_stats *stat; 2134 struct smb sb, *smb; 2135 struct ifnet *ifp; 2136 uint32_t *reg; 2137 int i; 2138 2139 ALE_LOCK_ASSERT(sc); 2140 2141 ifp = sc->ale_ifp; 2142 stat = &sc->ale_stats; 2143 smb = &sb; 2144 2145 /* Read Rx statistics. */ 2146 for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered; reg++) { 2147 *reg = CSR_READ_4(sc, ALE_RX_MIB_BASE + i); 2148 i += sizeof(uint32_t); 2149 } 2150 /* Read Tx statistics. */ 2151 for (reg = &sb.tx_frames, i = 0; reg <= &sb.tx_mcast_bytes; reg++) { 2152 *reg = CSR_READ_4(sc, ALE_TX_MIB_BASE + i); 2153 i += sizeof(uint32_t); 2154 } 2155 2156 /* Rx stats. */ 2157 stat->rx_frames += smb->rx_frames; 2158 stat->rx_bcast_frames += smb->rx_bcast_frames; 2159 stat->rx_mcast_frames += smb->rx_mcast_frames; 2160 stat->rx_pause_frames += smb->rx_pause_frames; 2161 stat->rx_control_frames += smb->rx_control_frames; 2162 stat->rx_crcerrs += smb->rx_crcerrs; 2163 stat->rx_lenerrs += smb->rx_lenerrs; 2164 stat->rx_bytes += smb->rx_bytes; 2165 stat->rx_runts += smb->rx_runts; 2166 stat->rx_fragments += smb->rx_fragments; 2167 stat->rx_pkts_64 += smb->rx_pkts_64; 2168 stat->rx_pkts_65_127 += smb->rx_pkts_65_127; 2169 stat->rx_pkts_128_255 += smb->rx_pkts_128_255; 2170 stat->rx_pkts_256_511 += smb->rx_pkts_256_511; 2171 stat->rx_pkts_512_1023 += smb->rx_pkts_512_1023; 2172 stat->rx_pkts_1024_1518 += smb->rx_pkts_1024_1518; 2173 stat->rx_pkts_1519_max += smb->rx_pkts_1519_max; 2174 stat->rx_pkts_truncated += smb->rx_pkts_truncated; 2175 stat->rx_fifo_oflows += smb->rx_fifo_oflows; 2176 stat->rx_rrs_errs += smb->rx_rrs_errs; 2177 stat->rx_alignerrs += smb->rx_alignerrs; 2178 stat->rx_bcast_bytes += smb->rx_bcast_bytes; 2179 stat->rx_mcast_bytes += smb->rx_mcast_bytes; 2180 stat->rx_pkts_filtered += smb->rx_pkts_filtered; 2181 2182 /* Tx stats. */ 2183 stat->tx_frames += smb->tx_frames; 2184 stat->tx_bcast_frames += smb->tx_bcast_frames; 2185 stat->tx_mcast_frames += smb->tx_mcast_frames; 2186 stat->tx_pause_frames += smb->tx_pause_frames; 2187 stat->tx_excess_defer += smb->tx_excess_defer; 2188 stat->tx_control_frames += smb->tx_control_frames; 2189 stat->tx_deferred += smb->tx_deferred; 2190 stat->tx_bytes += smb->tx_bytes; 2191 stat->tx_pkts_64 += smb->tx_pkts_64; 2192 stat->tx_pkts_65_127 += smb->tx_pkts_65_127; 2193 stat->tx_pkts_128_255 += smb->tx_pkts_128_255; 2194 stat->tx_pkts_256_511 += smb->tx_pkts_256_511; 2195 stat->tx_pkts_512_1023 += smb->tx_pkts_512_1023; 2196 stat->tx_pkts_1024_1518 += smb->tx_pkts_1024_1518; 2197 stat->tx_pkts_1519_max += smb->tx_pkts_1519_max; 2198 stat->tx_single_colls += smb->tx_single_colls; 2199 stat->tx_multi_colls += smb->tx_multi_colls; 2200 stat->tx_late_colls += smb->tx_late_colls; 2201 stat->tx_excess_colls += smb->tx_excess_colls; 2202 stat->tx_underrun += smb->tx_underrun; 2203 stat->tx_desc_underrun += smb->tx_desc_underrun; 2204 stat->tx_lenerrs += smb->tx_lenerrs; 2205 stat->tx_pkts_truncated += smb->tx_pkts_truncated; 2206 stat->tx_bcast_bytes += smb->tx_bcast_bytes; 2207 stat->tx_mcast_bytes += smb->tx_mcast_bytes; 2208 2209 /* Update counters in ifnet. */ 2210 if_inc_counter(ifp, IFCOUNTER_OPACKETS, smb->tx_frames); 2211 2212 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, smb->tx_single_colls + 2213 smb->tx_multi_colls * 2 + smb->tx_late_colls + 2214 smb->tx_excess_colls * HDPX_CFG_RETRY_DEFAULT); 2215 2216 if_inc_counter(ifp, IFCOUNTER_OERRORS, smb->tx_late_colls + 2217 smb->tx_excess_colls + smb->tx_underrun + smb->tx_pkts_truncated); 2218 2219 if_inc_counter(ifp, IFCOUNTER_IPACKETS, smb->rx_frames); 2220 2221 if_inc_counter(ifp, IFCOUNTER_IERRORS, 2222 smb->rx_crcerrs + smb->rx_lenerrs + 2223 smb->rx_runts + smb->rx_pkts_truncated + 2224 smb->rx_fifo_oflows + smb->rx_rrs_errs + 2225 smb->rx_alignerrs); 2226} 2227 2228static int 2229ale_intr(void *arg) 2230{ 2231 struct ale_softc *sc; 2232 uint32_t status; 2233 2234 sc = (struct ale_softc *)arg; 2235 2236 status = CSR_READ_4(sc, ALE_INTR_STATUS); 2237 if ((status & ALE_INTRS) == 0) 2238 return (FILTER_STRAY); 2239 /* Disable interrupts. */ 2240 CSR_WRITE_4(sc, ALE_INTR_STATUS, INTR_DIS_INT); 2241 taskqueue_enqueue(sc->ale_tq, &sc->ale_int_task); 2242 2243 return (FILTER_HANDLED); 2244} 2245 2246static void 2247ale_int_task(void *arg, int pending) 2248{ 2249 struct ale_softc *sc; 2250 struct ifnet *ifp; 2251 uint32_t status; 2252 int more; 2253 2254 sc = (struct ale_softc *)arg; 2255 2256 status = CSR_READ_4(sc, ALE_INTR_STATUS); 2257 ALE_LOCK(sc); 2258 if (sc->ale_morework != 0) 2259 status |= INTR_RX_PKT; 2260 if ((status & ALE_INTRS) == 0) 2261 goto done; 2262 2263 /* Acknowledge interrupts but still disable interrupts. */ 2264 CSR_WRITE_4(sc, ALE_INTR_STATUS, status | INTR_DIS_INT); 2265 2266 ifp = sc->ale_ifp; 2267 more = 0; 2268 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 2269 more = ale_rxeof(sc, sc->ale_process_limit); 2270 if (more == EAGAIN) 2271 sc->ale_morework = 1; 2272 else if (more == EIO) { 2273 sc->ale_stats.reset_brk_seq++; 2274 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2275 ale_init_locked(sc); 2276 ALE_UNLOCK(sc); 2277 return; 2278 } 2279 2280 if ((status & (INTR_DMA_RD_TO_RST | INTR_DMA_WR_TO_RST)) != 0) { 2281 if ((status & INTR_DMA_RD_TO_RST) != 0) 2282 device_printf(sc->ale_dev, 2283 "DMA read error! -- resetting\n"); 2284 if ((status & INTR_DMA_WR_TO_RST) != 0) 2285 device_printf(sc->ale_dev, 2286 "DMA write error! -- resetting\n"); 2287 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2288 ale_init_locked(sc); 2289 ALE_UNLOCK(sc); 2290 return; 2291 } 2292 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2293 ale_start_locked(ifp); 2294 } 2295 2296 if (more == EAGAIN || 2297 (CSR_READ_4(sc, ALE_INTR_STATUS) & ALE_INTRS) != 0) { 2298 ALE_UNLOCK(sc); 2299 taskqueue_enqueue(sc->ale_tq, &sc->ale_int_task); 2300 return; 2301 } 2302 2303done: 2304 ALE_UNLOCK(sc); 2305 2306 /* Re-enable interrupts. */ 2307 CSR_WRITE_4(sc, ALE_INTR_STATUS, 0x7FFFFFFF); 2308} 2309 2310static void 2311ale_txeof(struct ale_softc *sc) 2312{ 2313 struct ifnet *ifp; 2314 struct ale_txdesc *txd; 2315 uint32_t cons, prod; 2316 int prog; 2317 2318 ALE_LOCK_ASSERT(sc); 2319 2320 ifp = sc->ale_ifp; 2321 2322 if (sc->ale_cdata.ale_tx_cnt == 0) 2323 return; 2324 2325 bus_dmamap_sync(sc->ale_cdata.ale_tx_ring_tag, 2326 sc->ale_cdata.ale_tx_ring_map, 2327 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2328 if ((sc->ale_flags & ALE_FLAG_TXCMB_BUG) == 0) { 2329 bus_dmamap_sync(sc->ale_cdata.ale_tx_cmb_tag, 2330 sc->ale_cdata.ale_tx_cmb_map, 2331 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2332 prod = *sc->ale_cdata.ale_tx_cmb & TPD_CNT_MASK; 2333 } else 2334 prod = CSR_READ_2(sc, ALE_TPD_CONS_IDX); 2335 cons = sc->ale_cdata.ale_tx_cons; 2336 /* 2337 * Go through our Tx list and free mbufs for those 2338 * frames which have been transmitted. 2339 */ 2340 for (prog = 0; cons != prod; prog++, 2341 ALE_DESC_INC(cons, ALE_TX_RING_CNT)) { 2342 if (sc->ale_cdata.ale_tx_cnt <= 0) 2343 break; 2344 prog++; 2345 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2346 sc->ale_cdata.ale_tx_cnt--; 2347 txd = &sc->ale_cdata.ale_txdesc[cons]; 2348 if (txd->tx_m != NULL) { 2349 /* Reclaim transmitted mbufs. */ 2350 bus_dmamap_sync(sc->ale_cdata.ale_tx_tag, 2351 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 2352 bus_dmamap_unload(sc->ale_cdata.ale_tx_tag, 2353 txd->tx_dmamap); 2354 m_freem(txd->tx_m); 2355 txd->tx_m = NULL; 2356 } 2357 } 2358 2359 if (prog > 0) { 2360 sc->ale_cdata.ale_tx_cons = cons; 2361 /* 2362 * Unarm watchdog timer only when there is no pending 2363 * Tx descriptors in queue. 2364 */ 2365 if (sc->ale_cdata.ale_tx_cnt == 0) 2366 sc->ale_watchdog_timer = 0; 2367 } 2368} 2369 2370static void 2371ale_rx_update_page(struct ale_softc *sc, struct ale_rx_page **page, 2372 uint32_t length, uint32_t *prod) 2373{ 2374 struct ale_rx_page *rx_page; 2375 2376 rx_page = *page; 2377 /* Update consumer position. */ 2378 rx_page->cons += roundup(length + sizeof(struct rx_rs), 2379 ALE_RX_PAGE_ALIGN); 2380 if (rx_page->cons >= ALE_RX_PAGE_SZ) { 2381 /* 2382 * End of Rx page reached, let hardware reuse 2383 * this page. 2384 */ 2385 rx_page->cons = 0; 2386 *rx_page->cmb_addr = 0; 2387 bus_dmamap_sync(rx_page->cmb_tag, rx_page->cmb_map, 2388 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2389 CSR_WRITE_1(sc, ALE_RXF0_PAGE0 + sc->ale_cdata.ale_rx_curp, 2390 RXF_VALID); 2391 /* Switch to alternate Rx page. */ 2392 sc->ale_cdata.ale_rx_curp ^= 1; 2393 rx_page = *page = 2394 &sc->ale_cdata.ale_rx_page[sc->ale_cdata.ale_rx_curp]; 2395 /* Page flipped, sync CMB and Rx page. */ 2396 bus_dmamap_sync(rx_page->page_tag, rx_page->page_map, 2397 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2398 bus_dmamap_sync(rx_page->cmb_tag, rx_page->cmb_map, 2399 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2400 /* Sync completed, cache updated producer index. */ 2401 *prod = *rx_page->cmb_addr; 2402 } 2403} 2404 2405 2406/* 2407 * It seems that AR81xx controller can compute partial checksum. 2408 * The partial checksum value can be used to accelerate checksum 2409 * computation for fragmented TCP/UDP packets. Upper network stack 2410 * already takes advantage of the partial checksum value in IP 2411 * reassembly stage. But I'm not sure the correctness of the 2412 * partial hardware checksum assistance due to lack of data sheet. 2413 * In addition, the Rx feature of controller that requires copying 2414 * for every frames effectively nullifies one of most nice offload 2415 * capability of controller. 2416 */ 2417static void 2418ale_rxcsum(struct ale_softc *sc, struct mbuf *m, uint32_t status) 2419{ 2420 struct ifnet *ifp; 2421 struct ip *ip; 2422 char *p; 2423 2424 ifp = sc->ale_ifp; 2425 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 2426 if ((status & ALE_RD_IPCSUM_NOK) == 0) 2427 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 2428 2429 if ((sc->ale_flags & ALE_FLAG_RXCSUM_BUG) == 0) { 2430 if (((status & ALE_RD_IPV4_FRAG) == 0) && 2431 ((status & (ALE_RD_TCP | ALE_RD_UDP)) != 0) && 2432 ((status & ALE_RD_TCP_UDPCSUM_NOK) == 0)) { 2433 m->m_pkthdr.csum_flags |= 2434 CSUM_DATA_VALID | CSUM_PSEUDO_HDR; 2435 m->m_pkthdr.csum_data = 0xffff; 2436 } 2437 } else { 2438 if ((status & (ALE_RD_TCP | ALE_RD_UDP)) != 0 && 2439 (status & ALE_RD_TCP_UDPCSUM_NOK) == 0) { 2440 p = mtod(m, char *); 2441 p += ETHER_HDR_LEN; 2442 if ((status & ALE_RD_802_3) != 0) 2443 p += LLC_SNAPFRAMELEN; 2444 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) == 0 && 2445 (status & ALE_RD_VLAN) != 0) 2446 p += ETHER_VLAN_ENCAP_LEN; 2447 ip = (struct ip *)p; 2448 if (ip->ip_off != 0 && (status & ALE_RD_IPV4_DF) == 0) 2449 return; 2450 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID | 2451 CSUM_PSEUDO_HDR; 2452 m->m_pkthdr.csum_data = 0xffff; 2453 } 2454 } 2455 /* 2456 * Don't mark bad checksum for TCP/UDP frames 2457 * as fragmented frames may always have set 2458 * bad checksummed bit of frame status. 2459 */ 2460} 2461 2462/* Process received frames. */ 2463static int 2464ale_rxeof(struct ale_softc *sc, int count) 2465{ 2466 struct ale_rx_page *rx_page; 2467 struct rx_rs *rs; 2468 struct ifnet *ifp; 2469 struct mbuf *m; 2470 uint32_t length, prod, seqno, status, vtags; 2471 int prog; 2472 2473 ifp = sc->ale_ifp; 2474 rx_page = &sc->ale_cdata.ale_rx_page[sc->ale_cdata.ale_rx_curp]; 2475 bus_dmamap_sync(rx_page->cmb_tag, rx_page->cmb_map, 2476 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2477 bus_dmamap_sync(rx_page->page_tag, rx_page->page_map, 2478 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2479 /* 2480 * Don't directly access producer index as hardware may 2481 * update it while Rx handler is in progress. It would 2482 * be even better if there is a way to let hardware 2483 * know how far driver processed its received frames. 2484 * Alternatively, hardware could provide a way to disable 2485 * CMB updates until driver acknowledges the end of CMB 2486 * access. 2487 */ 2488 prod = *rx_page->cmb_addr; 2489 for (prog = 0; prog < count; prog++) { 2490 if (rx_page->cons >= prod) 2491 break; 2492 rs = (struct rx_rs *)(rx_page->page_addr + rx_page->cons); 2493 seqno = ALE_RX_SEQNO(le32toh(rs->seqno)); 2494 if (sc->ale_cdata.ale_rx_seqno != seqno) { 2495 /* 2496 * Normally I believe this should not happen unless 2497 * severe driver bug or corrupted memory. However 2498 * it seems to happen under certain conditions which 2499 * is triggered by abrupt Rx events such as initiation 2500 * of bulk transfer of remote host. It's not easy to 2501 * reproduce this and I doubt it could be related 2502 * with FIFO overflow of hardware or activity of Tx 2503 * CMB updates. I also remember similar behaviour 2504 * seen on RealTek 8139 which uses resembling Rx 2505 * scheme. 2506 */ 2507 if (bootverbose) 2508 device_printf(sc->ale_dev, 2509 "garbled seq: %u, expected: %u -- " 2510 "resetting!\n", seqno, 2511 sc->ale_cdata.ale_rx_seqno); 2512 return (EIO); 2513 } 2514 /* Frame received. */ 2515 sc->ale_cdata.ale_rx_seqno++; 2516 length = ALE_RX_BYTES(le32toh(rs->length)); 2517 status = le32toh(rs->flags); 2518 if ((status & ALE_RD_ERROR) != 0) { 2519 /* 2520 * We want to pass the following frames to upper 2521 * layer regardless of error status of Rx return 2522 * status. 2523 * 2524 * o IP/TCP/UDP checksum is bad. 2525 * o frame length and protocol specific length 2526 * does not match. 2527 */ 2528 if ((status & (ALE_RD_CRC | ALE_RD_CODE | 2529 ALE_RD_DRIBBLE | ALE_RD_RUNT | ALE_RD_OFLOW | 2530 ALE_RD_TRUNC)) != 0) { 2531 ale_rx_update_page(sc, &rx_page, length, &prod); 2532 continue; 2533 } 2534 } 2535 /* 2536 * m_devget(9) is major bottle-neck of ale(4)(It comes 2537 * from hardware limitation). For jumbo frames we could 2538 * get a slightly better performance if driver use 2539 * m_getjcl(9) with proper buffer size argument. However 2540 * that would make code more complicated and I don't 2541 * think users would expect good Rx performance numbers 2542 * on these low-end consumer ethernet controller. 2543 */ 2544 m = m_devget((char *)(rs + 1), length - ETHER_CRC_LEN, 2545 ETHER_ALIGN, ifp, NULL); 2546 if (m == NULL) { 2547 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1); 2548 ale_rx_update_page(sc, &rx_page, length, &prod); 2549 continue; 2550 } 2551 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0 && 2552 (status & ALE_RD_IPV4) != 0) 2553 ale_rxcsum(sc, m, status); 2554 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0 && 2555 (status & ALE_RD_VLAN) != 0) { 2556 vtags = ALE_RX_VLAN(le32toh(rs->vtags)); 2557 m->m_pkthdr.ether_vtag = ALE_RX_VLAN_TAG(vtags); 2558 m->m_flags |= M_VLANTAG; 2559 } 2560 2561 /* Pass it to upper layer. */ 2562 ALE_UNLOCK(sc); 2563 (*ifp->if_input)(ifp, m); 2564 ALE_LOCK(sc); 2565 2566 ale_rx_update_page(sc, &rx_page, length, &prod); 2567 } 2568 2569 return (count > 0 ? 0 : EAGAIN); 2570} 2571 2572static void 2573ale_tick(void *arg) 2574{ 2575 struct ale_softc *sc; 2576 struct mii_data *mii; 2577 2578 sc = (struct ale_softc *)arg; 2579 2580 ALE_LOCK_ASSERT(sc); 2581 2582 mii = device_get_softc(sc->ale_miibus); 2583 mii_tick(mii); 2584 ale_stats_update(sc); 2585 /* 2586 * Reclaim Tx buffers that have been transferred. It's not 2587 * needed here but it would release allocated mbuf chains 2588 * faster and limit the maximum delay to a hz. 2589 */ 2590 ale_txeof(sc); 2591 ale_watchdog(sc); 2592 callout_reset(&sc->ale_tick_ch, hz, ale_tick, sc); 2593} 2594 2595static void 2596ale_reset(struct ale_softc *sc) 2597{ 2598 uint32_t reg; 2599 int i; 2600 2601 /* Initialize PCIe module. From Linux. */ 2602 CSR_WRITE_4(sc, 0x1008, CSR_READ_4(sc, 0x1008) | 0x8000); 2603 2604 CSR_WRITE_4(sc, ALE_MASTER_CFG, MASTER_RESET); 2605 for (i = ALE_RESET_TIMEOUT; i > 0; i--) { 2606 DELAY(10); 2607 if ((CSR_READ_4(sc, ALE_MASTER_CFG) & MASTER_RESET) == 0) 2608 break; 2609 } 2610 if (i == 0) 2611 device_printf(sc->ale_dev, "master reset timeout!\n"); 2612 2613 for (i = ALE_RESET_TIMEOUT; i > 0; i--) { 2614 if ((reg = CSR_READ_4(sc, ALE_IDLE_STATUS)) == 0) 2615 break; 2616 DELAY(10); 2617 } 2618 2619 if (i == 0) 2620 device_printf(sc->ale_dev, "reset timeout(0x%08x)!\n", reg); 2621} 2622 2623static void 2624ale_init(void *xsc) 2625{ 2626 struct ale_softc *sc; 2627 2628 sc = (struct ale_softc *)xsc; 2629 ALE_LOCK(sc); 2630 ale_init_locked(sc); 2631 ALE_UNLOCK(sc); 2632} 2633 2634static void 2635ale_init_locked(struct ale_softc *sc) 2636{ 2637 struct ifnet *ifp; 2638 struct mii_data *mii; 2639 uint8_t eaddr[ETHER_ADDR_LEN]; 2640 bus_addr_t paddr; 2641 uint32_t reg, rxf_hi, rxf_lo; 2642 2643 ALE_LOCK_ASSERT(sc); 2644 2645 ifp = sc->ale_ifp; 2646 mii = device_get_softc(sc->ale_miibus); 2647 2648 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 2649 return; 2650 /* 2651 * Cancel any pending I/O. 2652 */ 2653 ale_stop(sc); 2654 /* 2655 * Reset the chip to a known state. 2656 */ 2657 ale_reset(sc); 2658 /* Initialize Tx descriptors, DMA memory blocks. */ 2659 ale_init_rx_pages(sc); 2660 ale_init_tx_ring(sc); 2661 2662 /* Reprogram the station address. */ 2663 bcopy(IF_LLADDR(ifp), eaddr, ETHER_ADDR_LEN); 2664 CSR_WRITE_4(sc, ALE_PAR0, 2665 eaddr[2] << 24 | eaddr[3] << 16 | eaddr[4] << 8 | eaddr[5]); 2666 CSR_WRITE_4(sc, ALE_PAR1, eaddr[0] << 8 | eaddr[1]); 2667 /* 2668 * Clear WOL status and disable all WOL feature as WOL 2669 * would interfere Rx operation under normal environments. 2670 */ 2671 CSR_READ_4(sc, ALE_WOL_CFG); 2672 CSR_WRITE_4(sc, ALE_WOL_CFG, 0); 2673 /* 2674 * Set Tx descriptor/RXF0/CMB base addresses. They share 2675 * the same high address part of DMAable region. 2676 */ 2677 paddr = sc->ale_cdata.ale_tx_ring_paddr; 2678 CSR_WRITE_4(sc, ALE_TPD_ADDR_HI, ALE_ADDR_HI(paddr)); 2679 CSR_WRITE_4(sc, ALE_TPD_ADDR_LO, ALE_ADDR_LO(paddr)); 2680 CSR_WRITE_4(sc, ALE_TPD_CNT, 2681 (ALE_TX_RING_CNT << TPD_CNT_SHIFT) & TPD_CNT_MASK); 2682 /* Set Rx page base address, note we use single queue. */ 2683 paddr = sc->ale_cdata.ale_rx_page[0].page_paddr; 2684 CSR_WRITE_4(sc, ALE_RXF0_PAGE0_ADDR_LO, ALE_ADDR_LO(paddr)); 2685 paddr = sc->ale_cdata.ale_rx_page[1].page_paddr; 2686 CSR_WRITE_4(sc, ALE_RXF0_PAGE1_ADDR_LO, ALE_ADDR_LO(paddr)); 2687 /* Set Tx/Rx CMB addresses. */ 2688 paddr = sc->ale_cdata.ale_tx_cmb_paddr; 2689 CSR_WRITE_4(sc, ALE_TX_CMB_ADDR_LO, ALE_ADDR_LO(paddr)); 2690 paddr = sc->ale_cdata.ale_rx_page[0].cmb_paddr; 2691 CSR_WRITE_4(sc, ALE_RXF0_CMB0_ADDR_LO, ALE_ADDR_LO(paddr)); 2692 paddr = sc->ale_cdata.ale_rx_page[1].cmb_paddr; 2693 CSR_WRITE_4(sc, ALE_RXF0_CMB1_ADDR_LO, ALE_ADDR_LO(paddr)); 2694 /* Mark RXF0 is valid. */ 2695 CSR_WRITE_1(sc, ALE_RXF0_PAGE0, RXF_VALID); 2696 CSR_WRITE_1(sc, ALE_RXF0_PAGE1, RXF_VALID); 2697 /* 2698 * No need to initialize RFX1/RXF2/RXF3. We don't use 2699 * multi-queue yet. 2700 */ 2701 2702 /* Set Rx page size, excluding guard frame size. */ 2703 CSR_WRITE_4(sc, ALE_RXF_PAGE_SIZE, ALE_RX_PAGE_SZ); 2704 /* Tell hardware that we're ready to load DMA blocks. */ 2705 CSR_WRITE_4(sc, ALE_DMA_BLOCK, DMA_BLOCK_LOAD); 2706 2707 /* Set Rx/Tx interrupt trigger threshold. */ 2708 CSR_WRITE_4(sc, ALE_INT_TRIG_THRESH, (1 << INT_TRIG_RX_THRESH_SHIFT) | 2709 (4 << INT_TRIG_TX_THRESH_SHIFT)); 2710 /* 2711 * XXX 2712 * Set interrupt trigger timer, its purpose and relation 2713 * with interrupt moderation mechanism is not clear yet. 2714 */ 2715 CSR_WRITE_4(sc, ALE_INT_TRIG_TIMER, 2716 ((ALE_USECS(10) << INT_TRIG_RX_TIMER_SHIFT) | 2717 (ALE_USECS(1000) << INT_TRIG_TX_TIMER_SHIFT))); 2718 2719 /* Configure interrupt moderation timer. */ 2720 reg = ALE_USECS(sc->ale_int_rx_mod) << IM_TIMER_RX_SHIFT; 2721 reg |= ALE_USECS(sc->ale_int_tx_mod) << IM_TIMER_TX_SHIFT; 2722 CSR_WRITE_4(sc, ALE_IM_TIMER, reg); 2723 reg = CSR_READ_4(sc, ALE_MASTER_CFG); 2724 reg &= ~(MASTER_CHIP_REV_MASK | MASTER_CHIP_ID_MASK); 2725 reg &= ~(MASTER_IM_RX_TIMER_ENB | MASTER_IM_TX_TIMER_ENB); 2726 if (ALE_USECS(sc->ale_int_rx_mod) != 0) 2727 reg |= MASTER_IM_RX_TIMER_ENB; 2728 if (ALE_USECS(sc->ale_int_tx_mod) != 0) 2729 reg |= MASTER_IM_TX_TIMER_ENB; 2730 CSR_WRITE_4(sc, ALE_MASTER_CFG, reg); 2731 CSR_WRITE_2(sc, ALE_INTR_CLR_TIMER, ALE_USECS(1000)); 2732 2733 /* Set Maximum frame size of controller. */ 2734 if (ifp->if_mtu < ETHERMTU) 2735 sc->ale_max_frame_size = ETHERMTU; 2736 else 2737 sc->ale_max_frame_size = ifp->if_mtu; 2738 sc->ale_max_frame_size += ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN + 2739 ETHER_CRC_LEN; 2740 CSR_WRITE_4(sc, ALE_FRAME_SIZE, sc->ale_max_frame_size); 2741 /* Configure IPG/IFG parameters. */ 2742 CSR_WRITE_4(sc, ALE_IPG_IFG_CFG, 2743 ((IPG_IFG_IPGT_DEFAULT << IPG_IFG_IPGT_SHIFT) & IPG_IFG_IPGT_MASK) | 2744 ((IPG_IFG_MIFG_DEFAULT << IPG_IFG_MIFG_SHIFT) & IPG_IFG_MIFG_MASK) | 2745 ((IPG_IFG_IPG1_DEFAULT << IPG_IFG_IPG1_SHIFT) & IPG_IFG_IPG1_MASK) | 2746 ((IPG_IFG_IPG2_DEFAULT << IPG_IFG_IPG2_SHIFT) & IPG_IFG_IPG2_MASK)); 2747 /* Set parameters for half-duplex media. */ 2748 CSR_WRITE_4(sc, ALE_HDPX_CFG, 2749 ((HDPX_CFG_LCOL_DEFAULT << HDPX_CFG_LCOL_SHIFT) & 2750 HDPX_CFG_LCOL_MASK) | 2751 ((HDPX_CFG_RETRY_DEFAULT << HDPX_CFG_RETRY_SHIFT) & 2752 HDPX_CFG_RETRY_MASK) | HDPX_CFG_EXC_DEF_EN | 2753 ((HDPX_CFG_ABEBT_DEFAULT << HDPX_CFG_ABEBT_SHIFT) & 2754 HDPX_CFG_ABEBT_MASK) | 2755 ((HDPX_CFG_JAMIPG_DEFAULT << HDPX_CFG_JAMIPG_SHIFT) & 2756 HDPX_CFG_JAMIPG_MASK)); 2757 2758 /* Configure Tx jumbo frame parameters. */ 2759 if ((sc->ale_flags & ALE_FLAG_JUMBO) != 0) { 2760 if (ifp->if_mtu < ETHERMTU) 2761 reg = sc->ale_max_frame_size; 2762 else if (ifp->if_mtu < 6 * 1024) 2763 reg = (sc->ale_max_frame_size * 2) / 3; 2764 else 2765 reg = sc->ale_max_frame_size / 2; 2766 CSR_WRITE_4(sc, ALE_TX_JUMBO_THRESH, 2767 roundup(reg, TX_JUMBO_THRESH_UNIT) >> 2768 TX_JUMBO_THRESH_UNIT_SHIFT); 2769 } 2770 /* Configure TxQ. */ 2771 reg = (128 << (sc->ale_dma_rd_burst >> DMA_CFG_RD_BURST_SHIFT)) 2772 << TXQ_CFG_TX_FIFO_BURST_SHIFT; 2773 reg |= (TXQ_CFG_TPD_BURST_DEFAULT << TXQ_CFG_TPD_BURST_SHIFT) & 2774 TXQ_CFG_TPD_BURST_MASK; 2775 CSR_WRITE_4(sc, ALE_TXQ_CFG, reg | TXQ_CFG_ENHANCED_MODE | TXQ_CFG_ENB); 2776 2777 /* Configure Rx jumbo frame & flow control parameters. */ 2778 if ((sc->ale_flags & ALE_FLAG_JUMBO) != 0) { 2779 reg = roundup(sc->ale_max_frame_size, RX_JUMBO_THRESH_UNIT); 2780 CSR_WRITE_4(sc, ALE_RX_JUMBO_THRESH, 2781 (((reg >> RX_JUMBO_THRESH_UNIT_SHIFT) << 2782 RX_JUMBO_THRESH_MASK_SHIFT) & RX_JUMBO_THRESH_MASK) | 2783 ((RX_JUMBO_LKAH_DEFAULT << RX_JUMBO_LKAH_SHIFT) & 2784 RX_JUMBO_LKAH_MASK)); 2785 reg = CSR_READ_4(sc, ALE_SRAM_RX_FIFO_LEN); 2786 rxf_hi = (reg * 7) / 10; 2787 rxf_lo = (reg * 3)/ 10; 2788 CSR_WRITE_4(sc, ALE_RX_FIFO_PAUSE_THRESH, 2789 ((rxf_lo << RX_FIFO_PAUSE_THRESH_LO_SHIFT) & 2790 RX_FIFO_PAUSE_THRESH_LO_MASK) | 2791 ((rxf_hi << RX_FIFO_PAUSE_THRESH_HI_SHIFT) & 2792 RX_FIFO_PAUSE_THRESH_HI_MASK)); 2793 } 2794 2795 /* Disable RSS. */ 2796 CSR_WRITE_4(sc, ALE_RSS_IDT_TABLE0, 0); 2797 CSR_WRITE_4(sc, ALE_RSS_CPU, 0); 2798 2799 /* Configure RxQ. */ 2800 CSR_WRITE_4(sc, ALE_RXQ_CFG, 2801 RXQ_CFG_ALIGN_32 | RXQ_CFG_CUT_THROUGH_ENB | RXQ_CFG_ENB); 2802 2803 /* Configure DMA parameters. */ 2804 reg = 0; 2805 if ((sc->ale_flags & ALE_FLAG_TXCMB_BUG) == 0) 2806 reg |= DMA_CFG_TXCMB_ENB; 2807 CSR_WRITE_4(sc, ALE_DMA_CFG, 2808 DMA_CFG_OUT_ORDER | DMA_CFG_RD_REQ_PRI | DMA_CFG_RCB_64 | 2809 sc->ale_dma_rd_burst | reg | 2810 sc->ale_dma_wr_burst | DMA_CFG_RXCMB_ENB | 2811 ((DMA_CFG_RD_DELAY_CNT_DEFAULT << DMA_CFG_RD_DELAY_CNT_SHIFT) & 2812 DMA_CFG_RD_DELAY_CNT_MASK) | 2813 ((DMA_CFG_WR_DELAY_CNT_DEFAULT << DMA_CFG_WR_DELAY_CNT_SHIFT) & 2814 DMA_CFG_WR_DELAY_CNT_MASK)); 2815 2816 /* 2817 * Hardware can be configured to issue SMB interrupt based 2818 * on programmed interval. Since there is a callout that is 2819 * invoked for every hz in driver we use that instead of 2820 * relying on periodic SMB interrupt. 2821 */ 2822 CSR_WRITE_4(sc, ALE_SMB_STAT_TIMER, ALE_USECS(0)); 2823 /* Clear MAC statistics. */ 2824 ale_stats_clear(sc); 2825 2826 /* 2827 * Configure Tx/Rx MACs. 2828 * - Auto-padding for short frames. 2829 * - Enable CRC generation. 2830 * Actual reconfiguration of MAC for resolved speed/duplex 2831 * is followed after detection of link establishment. 2832 * AR81xx always does checksum computation regardless of 2833 * MAC_CFG_RXCSUM_ENB bit. In fact, setting the bit will 2834 * cause Rx handling issue for fragmented IP datagrams due 2835 * to silicon bug. 2836 */ 2837 reg = MAC_CFG_TX_CRC_ENB | MAC_CFG_TX_AUTO_PAD | MAC_CFG_FULL_DUPLEX | 2838 ((MAC_CFG_PREAMBLE_DEFAULT << MAC_CFG_PREAMBLE_SHIFT) & 2839 MAC_CFG_PREAMBLE_MASK); 2840 if ((sc->ale_flags & ALE_FLAG_FASTETHER) != 0) 2841 reg |= MAC_CFG_SPEED_10_100; 2842 else 2843 reg |= MAC_CFG_SPEED_1000; 2844 CSR_WRITE_4(sc, ALE_MAC_CFG, reg); 2845 2846 /* Set up the receive filter. */ 2847 ale_rxfilter(sc); 2848 ale_rxvlan(sc); 2849 2850 /* Acknowledge all pending interrupts and clear it. */ 2851 CSR_WRITE_4(sc, ALE_INTR_MASK, ALE_INTRS); 2852 CSR_WRITE_4(sc, ALE_INTR_STATUS, 0xFFFFFFFF); 2853 CSR_WRITE_4(sc, ALE_INTR_STATUS, 0); 2854 2855 ifp->if_drv_flags |= IFF_DRV_RUNNING; 2856 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2857 2858 sc->ale_flags &= ~ALE_FLAG_LINK; 2859 /* Switch to the current media. */ 2860 mii_mediachg(mii); 2861 2862 callout_reset(&sc->ale_tick_ch, hz, ale_tick, sc); 2863} 2864 2865static void 2866ale_stop(struct ale_softc *sc) 2867{ 2868 struct ifnet *ifp; 2869 struct ale_txdesc *txd; 2870 uint32_t reg; 2871 int i; 2872 2873 ALE_LOCK_ASSERT(sc); 2874 /* 2875 * Mark the interface down and cancel the watchdog timer. 2876 */ 2877 ifp = sc->ale_ifp; 2878 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 2879 sc->ale_flags &= ~ALE_FLAG_LINK; 2880 callout_stop(&sc->ale_tick_ch); 2881 sc->ale_watchdog_timer = 0; 2882 ale_stats_update(sc); 2883 /* Disable interrupts. */ 2884 CSR_WRITE_4(sc, ALE_INTR_MASK, 0); 2885 CSR_WRITE_4(sc, ALE_INTR_STATUS, 0xFFFFFFFF); 2886 /* Disable queue processing and DMA. */ 2887 reg = CSR_READ_4(sc, ALE_TXQ_CFG); 2888 reg &= ~TXQ_CFG_ENB; 2889 CSR_WRITE_4(sc, ALE_TXQ_CFG, reg); 2890 reg = CSR_READ_4(sc, ALE_RXQ_CFG); 2891 reg &= ~RXQ_CFG_ENB; 2892 CSR_WRITE_4(sc, ALE_RXQ_CFG, reg); 2893 reg = CSR_READ_4(sc, ALE_DMA_CFG); 2894 reg &= ~(DMA_CFG_TXCMB_ENB | DMA_CFG_RXCMB_ENB); 2895 CSR_WRITE_4(sc, ALE_DMA_CFG, reg); 2896 DELAY(1000); 2897 /* Stop Rx/Tx MACs. */ 2898 ale_stop_mac(sc); 2899 /* Disable interrupts which might be touched in taskq handler. */ 2900 CSR_WRITE_4(sc, ALE_INTR_STATUS, 0xFFFFFFFF); 2901 2902 /* 2903 * Free TX mbufs still in the queues. 2904 */ 2905 for (i = 0; i < ALE_TX_RING_CNT; i++) { 2906 txd = &sc->ale_cdata.ale_txdesc[i]; 2907 if (txd->tx_m != NULL) { 2908 bus_dmamap_sync(sc->ale_cdata.ale_tx_tag, 2909 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 2910 bus_dmamap_unload(sc->ale_cdata.ale_tx_tag, 2911 txd->tx_dmamap); 2912 m_freem(txd->tx_m); 2913 txd->tx_m = NULL; 2914 } 2915 } 2916} 2917 2918static void 2919ale_stop_mac(struct ale_softc *sc) 2920{ 2921 uint32_t reg; 2922 int i; 2923 2924 ALE_LOCK_ASSERT(sc); 2925 2926 reg = CSR_READ_4(sc, ALE_MAC_CFG); 2927 if ((reg & (MAC_CFG_TX_ENB | MAC_CFG_RX_ENB)) != 0) { 2928 reg &= ~(MAC_CFG_TX_ENB | MAC_CFG_RX_ENB); 2929 CSR_WRITE_4(sc, ALE_MAC_CFG, reg); 2930 } 2931 2932 for (i = ALE_TIMEOUT; i > 0; i--) { 2933 reg = CSR_READ_4(sc, ALE_IDLE_STATUS); 2934 if (reg == 0) 2935 break; 2936 DELAY(10); 2937 } 2938 if (i == 0) 2939 device_printf(sc->ale_dev, 2940 "could not disable Tx/Rx MAC(0x%08x)!\n", reg); 2941} 2942 2943static void 2944ale_init_tx_ring(struct ale_softc *sc) 2945{ 2946 struct ale_txdesc *txd; 2947 int i; 2948 2949 ALE_LOCK_ASSERT(sc); 2950 2951 sc->ale_cdata.ale_tx_prod = 0; 2952 sc->ale_cdata.ale_tx_cons = 0; 2953 sc->ale_cdata.ale_tx_cnt = 0; 2954 2955 bzero(sc->ale_cdata.ale_tx_ring, ALE_TX_RING_SZ); 2956 bzero(sc->ale_cdata.ale_tx_cmb, ALE_TX_CMB_SZ); 2957 for (i = 0; i < ALE_TX_RING_CNT; i++) { 2958 txd = &sc->ale_cdata.ale_txdesc[i]; 2959 txd->tx_m = NULL; 2960 } 2961 *sc->ale_cdata.ale_tx_cmb = 0; 2962 bus_dmamap_sync(sc->ale_cdata.ale_tx_cmb_tag, 2963 sc->ale_cdata.ale_tx_cmb_map, 2964 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2965 bus_dmamap_sync(sc->ale_cdata.ale_tx_ring_tag, 2966 sc->ale_cdata.ale_tx_ring_map, 2967 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2968} 2969 2970static void 2971ale_init_rx_pages(struct ale_softc *sc) 2972{ 2973 struct ale_rx_page *rx_page; 2974 int i; 2975 2976 ALE_LOCK_ASSERT(sc); 2977 2978 sc->ale_morework = 0; 2979 sc->ale_cdata.ale_rx_seqno = 0; 2980 sc->ale_cdata.ale_rx_curp = 0; 2981 2982 for (i = 0; i < ALE_RX_PAGES; i++) { 2983 rx_page = &sc->ale_cdata.ale_rx_page[i]; 2984 bzero(rx_page->page_addr, sc->ale_pagesize); 2985 bzero(rx_page->cmb_addr, ALE_RX_CMB_SZ); 2986 rx_page->cons = 0; 2987 *rx_page->cmb_addr = 0; 2988 bus_dmamap_sync(rx_page->page_tag, rx_page->page_map, 2989 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2990 bus_dmamap_sync(rx_page->cmb_tag, rx_page->cmb_map, 2991 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2992 } 2993} 2994 2995static void 2996ale_rxvlan(struct ale_softc *sc) 2997{ 2998 struct ifnet *ifp; 2999 uint32_t reg; 3000 3001 ALE_LOCK_ASSERT(sc); 3002 3003 ifp = sc->ale_ifp; 3004 reg = CSR_READ_4(sc, ALE_MAC_CFG); 3005 reg &= ~MAC_CFG_VLAN_TAG_STRIP; 3006 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) 3007 reg |= MAC_CFG_VLAN_TAG_STRIP; 3008 CSR_WRITE_4(sc, ALE_MAC_CFG, reg); 3009} 3010 3011static void 3012ale_rxfilter(struct ale_softc *sc) 3013{ 3014 struct ifnet *ifp; 3015 struct ifmultiaddr *ifma; 3016 uint32_t crc; 3017 uint32_t mchash[2]; 3018 uint32_t rxcfg; 3019 3020 ALE_LOCK_ASSERT(sc); 3021 3022 ifp = sc->ale_ifp; 3023 3024 rxcfg = CSR_READ_4(sc, ALE_MAC_CFG); 3025 rxcfg &= ~(MAC_CFG_ALLMULTI | MAC_CFG_BCAST | MAC_CFG_PROMISC); 3026 if ((ifp->if_flags & IFF_BROADCAST) != 0) 3027 rxcfg |= MAC_CFG_BCAST; 3028 if ((ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) != 0) { 3029 if ((ifp->if_flags & IFF_PROMISC) != 0) 3030 rxcfg |= MAC_CFG_PROMISC; 3031 if ((ifp->if_flags & IFF_ALLMULTI) != 0) 3032 rxcfg |= MAC_CFG_ALLMULTI; 3033 CSR_WRITE_4(sc, ALE_MAR0, 0xFFFFFFFF); 3034 CSR_WRITE_4(sc, ALE_MAR1, 0xFFFFFFFF); 3035 CSR_WRITE_4(sc, ALE_MAC_CFG, rxcfg); 3036 return; 3037 } 3038 3039 /* Program new filter. */ 3040 bzero(mchash, sizeof(mchash)); 3041 3042 if_maddr_rlock(ifp); 3043 TAILQ_FOREACH(ifma, &sc->ale_ifp->if_multiaddrs, ifma_link) { 3044 if (ifma->ifma_addr->sa_family != AF_LINK) 3045 continue; 3046 crc = ether_crc32_be(LLADDR((struct sockaddr_dl *) 3047 ifma->ifma_addr), ETHER_ADDR_LEN); 3048 mchash[crc >> 31] |= 1 << ((crc >> 26) & 0x1f); 3049 } 3050 if_maddr_runlock(ifp); 3051 3052 CSR_WRITE_4(sc, ALE_MAR0, mchash[0]); 3053 CSR_WRITE_4(sc, ALE_MAR1, mchash[1]); 3054 CSR_WRITE_4(sc, ALE_MAC_CFG, rxcfg); 3055} 3056 3057static int 3058sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high) 3059{ 3060 int error, value; 3061 3062 if (arg1 == NULL) 3063 return (EINVAL); 3064 value = *(int *)arg1; 3065 error = sysctl_handle_int(oidp, &value, 0, req); 3066 if (error || req->newptr == NULL) 3067 return (error); 3068 if (value < low || value > high) 3069 return (EINVAL); 3070 *(int *)arg1 = value; 3071 3072 return (0); 3073} 3074 3075static int 3076sysctl_hw_ale_proc_limit(SYSCTL_HANDLER_ARGS) 3077{ 3078 return (sysctl_int_range(oidp, arg1, arg2, req, 3079 ALE_PROC_MIN, ALE_PROC_MAX)); 3080} 3081 3082static int 3083sysctl_hw_ale_int_mod(SYSCTL_HANDLER_ARGS) 3084{ 3085 3086 return (sysctl_int_range(oidp, arg1, arg2, req, 3087 ALE_IM_TIMER_MIN, ALE_IM_TIMER_MAX)); 3088} 3089