1/*- 2 * SPDX-License-Identifier: BSD-4-Clause 3 * 4 * Copyright (c) 1997, 1998, 1999 5 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35#include <sys/cdefs.h> 36__FBSDID("$FreeBSD: releng/12.0/sys/dev/xl/if_xl.c 338948 2018-09-26 17:12:14Z imp $"); 37 38/* 39 * 3Com 3c90x Etherlink XL PCI NIC driver 40 * 41 * Supports the 3Com "boomerang", "cyclone" and "hurricane" PCI 42 * bus-master chips (3c90x cards and embedded controllers) including 43 * the following: 44 * 45 * 3Com 3c900-TPO 10Mbps/RJ-45 46 * 3Com 3c900-COMBO 10Mbps/RJ-45,AUI,BNC 47 * 3Com 3c905-TX 10/100Mbps/RJ-45 48 * 3Com 3c905-T4 10/100Mbps/RJ-45 49 * 3Com 3c900B-TPO 10Mbps/RJ-45 50 * 3Com 3c900B-COMBO 10Mbps/RJ-45,AUI,BNC 51 * 3Com 3c900B-TPC 10Mbps/RJ-45,BNC 52 * 3Com 3c900B-FL 10Mbps/Fiber-optic 53 * 3Com 3c905B-COMBO 10/100Mbps/RJ-45,AUI,BNC 54 * 3Com 3c905B-TX 10/100Mbps/RJ-45 55 * 3Com 3c905B-FL/FX 10/100Mbps/Fiber-optic 56 * 3Com 3c905C-TX 10/100Mbps/RJ-45 (Tornado ASIC) 57 * 3Com 3c980-TX 10/100Mbps server adapter (Hurricane ASIC) 58 * 3Com 3c980C-TX 10/100Mbps server adapter (Tornado ASIC) 59 * 3Com 3cSOHO100-TX 10/100Mbps/RJ-45 (Hurricane ASIC) 60 * 3Com 3c450-TX 10/100Mbps/RJ-45 (Tornado ASIC) 61 * 3Com 3c555 10/100Mbps/RJ-45 (MiniPCI, Laptop Hurricane) 62 * 3Com 3c556 10/100Mbps/RJ-45 (MiniPCI, Hurricane ASIC) 63 * 3Com 3c556B 10/100Mbps/RJ-45 (MiniPCI, Hurricane ASIC) 64 * 3Com 3c575TX 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC) 65 * 3Com 3c575B 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC) 66 * 3Com 3c575C 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC) 67 * 3Com 3cxfem656 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC) 68 * 3Com 3cxfem656b 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC) 69 * 3Com 3cxfem656c 10/100Mbps/RJ-45 (Cardbus, Tornado ASIC) 70 * Dell Optiplex GX1 on-board 3c918 10/100Mbps/RJ-45 71 * Dell on-board 3c920 10/100Mbps/RJ-45 72 * Dell Precision on-board 3c905B 10/100Mbps/RJ-45 73 * Dell Latitude laptop docking station embedded 3c905-TX 74 * 75 * Written by Bill Paul <wpaul@ctr.columbia.edu> 76 * Electrical Engineering Department 77 * Columbia University, New York City 78 */ 79/* 80 * The 3c90x series chips use a bus-master DMA interface for transferring 81 * packets to and from the controller chip. Some of the "vortex" cards 82 * (3c59x) also supported a bus master mode, however for those chips 83 * you could only DMA packets to/from a contiguous memory buffer. For 84 * transmission this would mean copying the contents of the queued mbuf 85 * chain into an mbuf cluster and then DMAing the cluster. This extra 86 * copy would sort of defeat the purpose of the bus master support for 87 * any packet that doesn't fit into a single mbuf. 88 * 89 * By contrast, the 3c90x cards support a fragment-based bus master 90 * mode where mbuf chains can be encapsulated using TX descriptors. 91 * This is similar to other PCI chips such as the Texas Instruments 92 * ThunderLAN and the Intel 82557/82558. 93 * 94 * The "vortex" driver (if_vx.c) happens to work for the "boomerang" 95 * bus master chips because they maintain the old PIO interface for 96 * backwards compatibility, but starting with the 3c905B and the 97 * "cyclone" chips, the compatibility interface has been dropped. 98 * Since using bus master DMA is a big win, we use this driver to 99 * support the PCI "boomerang" chips even though they work with the 100 * "vortex" driver in order to obtain better performance. 101 */ 102 103#ifdef HAVE_KERNEL_OPTION_HEADERS 104#include "opt_device_polling.h" 105#endif 106 107#include <sys/param.h> 108#include <sys/systm.h> 109#include <sys/sockio.h> 110#include <sys/endian.h> 111#include <sys/kernel.h> 112#include <sys/malloc.h> 113#include <sys/mbuf.h> 114#include <sys/module.h> 115#include <sys/socket.h> 116#include <sys/taskqueue.h> 117 118#include <net/if.h> 119#include <net/if_var.h> 120#include <net/if_arp.h> 121#include <net/ethernet.h> 122#include <net/if_dl.h> 123#include <net/if_media.h> 124#include <net/if_types.h> 125 126#include <net/bpf.h> 127 128#include <machine/bus.h> 129#include <machine/resource.h> 130#include <sys/bus.h> 131#include <sys/rman.h> 132 133#include <dev/mii/mii.h> 134#include <dev/mii/mii_bitbang.h> 135#include <dev/mii/miivar.h> 136 137#include <dev/pci/pcireg.h> 138#include <dev/pci/pcivar.h> 139 140MODULE_DEPEND(xl, pci, 1, 1, 1); 141MODULE_DEPEND(xl, ether, 1, 1, 1); 142MODULE_DEPEND(xl, miibus, 1, 1, 1); 143 144/* "device miibus" required. See GENERIC if you get errors here. */ 145#include "miibus_if.h" 146 147#include <dev/xl/if_xlreg.h> 148 149/* 150 * TX Checksumming is disabled by default for two reasons: 151 * - TX Checksumming will occasionally produce corrupt packets 152 * - TX Checksumming seems to reduce performance 153 * 154 * Only 905B/C cards were reported to have this problem, it is possible 155 * that later chips _may_ be immune. 156 */ 157#define XL905B_TXCSUM_BROKEN 1 158 159#ifdef XL905B_TXCSUM_BROKEN 160#define XL905B_CSUM_FEATURES 0 161#else 162#define XL905B_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 163#endif 164 165/* 166 * Various supported device vendors/types and their names. 167 */ 168static const struct xl_type xl_devs[] = { 169 { TC_VENDORID, TC_DEVICEID_BOOMERANG_10BT, 170 "3Com 3c900-TPO Etherlink XL" }, 171 { TC_VENDORID, TC_DEVICEID_BOOMERANG_10BT_COMBO, 172 "3Com 3c900-COMBO Etherlink XL" }, 173 { TC_VENDORID, TC_DEVICEID_BOOMERANG_10_100BT, 174 "3Com 3c905-TX Fast Etherlink XL" }, 175 { TC_VENDORID, TC_DEVICEID_BOOMERANG_100BT4, 176 "3Com 3c905-T4 Fast Etherlink XL" }, 177 { TC_VENDORID, TC_DEVICEID_KRAKATOA_10BT, 178 "3Com 3c900B-TPO Etherlink XL" }, 179 { TC_VENDORID, TC_DEVICEID_KRAKATOA_10BT_COMBO, 180 "3Com 3c900B-COMBO Etherlink XL" }, 181 { TC_VENDORID, TC_DEVICEID_KRAKATOA_10BT_TPC, 182 "3Com 3c900B-TPC Etherlink XL" }, 183 { TC_VENDORID, TC_DEVICEID_CYCLONE_10FL, 184 "3Com 3c900B-FL Etherlink XL" }, 185 { TC_VENDORID, TC_DEVICEID_HURRICANE_10_100BT, 186 "3Com 3c905B-TX Fast Etherlink XL" }, 187 { TC_VENDORID, TC_DEVICEID_CYCLONE_10_100BT4, 188 "3Com 3c905B-T4 Fast Etherlink XL" }, 189 { TC_VENDORID, TC_DEVICEID_CYCLONE_10_100FX, 190 "3Com 3c905B-FX/SC Fast Etherlink XL" }, 191 { TC_VENDORID, TC_DEVICEID_CYCLONE_10_100_COMBO, 192 "3Com 3c905B-COMBO Fast Etherlink XL" }, 193 { TC_VENDORID, TC_DEVICEID_TORNADO_10_100BT, 194 "3Com 3c905C-TX Fast Etherlink XL" }, 195 { TC_VENDORID, TC_DEVICEID_TORNADO_10_100BT_920B, 196 "3Com 3c920B-EMB Integrated Fast Etherlink XL" }, 197 { TC_VENDORID, TC_DEVICEID_TORNADO_10_100BT_920B_WNM, 198 "3Com 3c920B-EMB-WNM Integrated Fast Etherlink XL" }, 199 { TC_VENDORID, TC_DEVICEID_HURRICANE_10_100BT_SERV, 200 "3Com 3c980 Fast Etherlink XL" }, 201 { TC_VENDORID, TC_DEVICEID_TORNADO_10_100BT_SERV, 202 "3Com 3c980C Fast Etherlink XL" }, 203 { TC_VENDORID, TC_DEVICEID_HURRICANE_SOHO100TX, 204 "3Com 3cSOHO100-TX OfficeConnect" }, 205 { TC_VENDORID, TC_DEVICEID_TORNADO_HOMECONNECT, 206 "3Com 3c450-TX HomeConnect" }, 207 { TC_VENDORID, TC_DEVICEID_HURRICANE_555, 208 "3Com 3c555 Fast Etherlink XL" }, 209 { TC_VENDORID, TC_DEVICEID_HURRICANE_556, 210 "3Com 3c556 Fast Etherlink XL" }, 211 { TC_VENDORID, TC_DEVICEID_HURRICANE_556B, 212 "3Com 3c556B Fast Etherlink XL" }, 213 { TC_VENDORID, TC_DEVICEID_HURRICANE_575A, 214 "3Com 3c575TX Fast Etherlink XL" }, 215 { TC_VENDORID, TC_DEVICEID_HURRICANE_575B, 216 "3Com 3c575B Fast Etherlink XL" }, 217 { TC_VENDORID, TC_DEVICEID_HURRICANE_575C, 218 "3Com 3c575C Fast Etherlink XL" }, 219 { TC_VENDORID, TC_DEVICEID_HURRICANE_656, 220 "3Com 3c656 Fast Etherlink XL" }, 221 { TC_VENDORID, TC_DEVICEID_HURRICANE_656B, 222 "3Com 3c656B Fast Etherlink XL" }, 223 { TC_VENDORID, TC_DEVICEID_TORNADO_656C, 224 "3Com 3c656C Fast Etherlink XL" }, 225 { 0, 0, NULL } 226}; 227 228static int xl_probe(device_t); 229static int xl_attach(device_t); 230static int xl_detach(device_t); 231 232static int xl_newbuf(struct xl_softc *, struct xl_chain_onefrag *); 233static void xl_tick(void *); 234static void xl_stats_update(struct xl_softc *); 235static int xl_encap(struct xl_softc *, struct xl_chain *, struct mbuf **); 236static int xl_rxeof(struct xl_softc *); 237static void xl_rxeof_task(void *, int); 238static int xl_rx_resync(struct xl_softc *); 239static void xl_txeof(struct xl_softc *); 240static void xl_txeof_90xB(struct xl_softc *); 241static void xl_txeoc(struct xl_softc *); 242static void xl_intr(void *); 243static void xl_start(struct ifnet *); 244static void xl_start_locked(struct ifnet *); 245static void xl_start_90xB_locked(struct ifnet *); 246static int xl_ioctl(struct ifnet *, u_long, caddr_t); 247static void xl_init(void *); 248static void xl_init_locked(struct xl_softc *); 249static void xl_stop(struct xl_softc *); 250static int xl_watchdog(struct xl_softc *); 251static int xl_shutdown(device_t); 252static int xl_suspend(device_t); 253static int xl_resume(device_t); 254static void xl_setwol(struct xl_softc *); 255 256#ifdef DEVICE_POLLING 257static int xl_poll(struct ifnet *ifp, enum poll_cmd cmd, int count); 258static int xl_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count); 259#endif 260 261static int xl_ifmedia_upd(struct ifnet *); 262static void xl_ifmedia_sts(struct ifnet *, struct ifmediareq *); 263 264static int xl_eeprom_wait(struct xl_softc *); 265static int xl_read_eeprom(struct xl_softc *, caddr_t, int, int, int); 266 267static void xl_rxfilter(struct xl_softc *); 268static void xl_rxfilter_90x(struct xl_softc *); 269static void xl_rxfilter_90xB(struct xl_softc *); 270static void xl_setcfg(struct xl_softc *); 271static void xl_setmode(struct xl_softc *, int); 272static void xl_reset(struct xl_softc *); 273static int xl_list_rx_init(struct xl_softc *); 274static int xl_list_tx_init(struct xl_softc *); 275static int xl_list_tx_init_90xB(struct xl_softc *); 276static void xl_wait(struct xl_softc *); 277static void xl_mediacheck(struct xl_softc *); 278static void xl_choose_media(struct xl_softc *sc, int *media); 279static void xl_choose_xcvr(struct xl_softc *, int); 280static void xl_dma_map_addr(void *, bus_dma_segment_t *, int, int); 281#ifdef notdef 282static void xl_testpacket(struct xl_softc *); 283#endif 284 285static int xl_miibus_readreg(device_t, int, int); 286static int xl_miibus_writereg(device_t, int, int, int); 287static void xl_miibus_statchg(device_t); 288static void xl_miibus_mediainit(device_t); 289 290/* 291 * MII bit-bang glue 292 */ 293static uint32_t xl_mii_bitbang_read(device_t); 294static void xl_mii_bitbang_write(device_t, uint32_t); 295 296static const struct mii_bitbang_ops xl_mii_bitbang_ops = { 297 xl_mii_bitbang_read, 298 xl_mii_bitbang_write, 299 { 300 XL_MII_DATA, /* MII_BIT_MDO */ 301 XL_MII_DATA, /* MII_BIT_MDI */ 302 XL_MII_CLK, /* MII_BIT_MDC */ 303 XL_MII_DIR, /* MII_BIT_DIR_HOST_PHY */ 304 0, /* MII_BIT_DIR_PHY_HOST */ 305 } 306}; 307 308static device_method_t xl_methods[] = { 309 /* Device interface */ 310 DEVMETHOD(device_probe, xl_probe), 311 DEVMETHOD(device_attach, xl_attach), 312 DEVMETHOD(device_detach, xl_detach), 313 DEVMETHOD(device_shutdown, xl_shutdown), 314 DEVMETHOD(device_suspend, xl_suspend), 315 DEVMETHOD(device_resume, xl_resume), 316 317 /* MII interface */ 318 DEVMETHOD(miibus_readreg, xl_miibus_readreg), 319 DEVMETHOD(miibus_writereg, xl_miibus_writereg), 320 DEVMETHOD(miibus_statchg, xl_miibus_statchg), 321 DEVMETHOD(miibus_mediainit, xl_miibus_mediainit), 322 323 DEVMETHOD_END 324}; 325 326static driver_t xl_driver = { 327 "xl", 328 xl_methods, 329 sizeof(struct xl_softc) 330}; 331 332static devclass_t xl_devclass; 333 334DRIVER_MODULE_ORDERED(xl, pci, xl_driver, xl_devclass, NULL, NULL, 335 SI_ORDER_ANY); 336DRIVER_MODULE(miibus, xl, miibus_driver, miibus_devclass, NULL, NULL); 337MODULE_PNP_INFO("U16:vendor;U16:device;D:#", pci, xl, xl_devs, 338 nitems(xl_devs) - 1); 339 340static void 341xl_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 342{ 343 u_int32_t *paddr; 344 345 paddr = arg; 346 *paddr = segs->ds_addr; 347} 348 349/* 350 * Murphy's law says that it's possible the chip can wedge and 351 * the 'command in progress' bit may never clear. Hence, we wait 352 * only a finite amount of time to avoid getting caught in an 353 * infinite loop. Normally this delay routine would be a macro, 354 * but it isn't called during normal operation so we can afford 355 * to make it a function. Suppress warning when card gone. 356 */ 357static void 358xl_wait(struct xl_softc *sc) 359{ 360 int i; 361 362 for (i = 0; i < XL_TIMEOUT; i++) { 363 if ((CSR_READ_2(sc, XL_STATUS) & XL_STAT_CMDBUSY) == 0) 364 break; 365 } 366 367 if (i == XL_TIMEOUT && bus_child_present(sc->xl_dev)) 368 device_printf(sc->xl_dev, "command never completed!\n"); 369} 370 371/* 372 * MII access routines are provided for adapters with external 373 * PHYs (3c905-TX, 3c905-T4, 3c905B-T4) and those with built-in 374 * autoneg logic that's faked up to look like a PHY (3c905B-TX). 375 * Note: if you don't perform the MDIO operations just right, 376 * it's possible to end up with code that works correctly with 377 * some chips/CPUs/processor speeds/bus speeds/etc but not 378 * with others. 379 */ 380 381/* 382 * Read the MII serial port for the MII bit-bang module. 383 */ 384static uint32_t 385xl_mii_bitbang_read(device_t dev) 386{ 387 struct xl_softc *sc; 388 uint32_t val; 389 390 sc = device_get_softc(dev); 391 392 /* We're already in window 4. */ 393 val = CSR_READ_2(sc, XL_W4_PHY_MGMT); 394 CSR_BARRIER(sc, XL_W4_PHY_MGMT, 2, 395 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 396 397 return (val); 398} 399 400/* 401 * Write the MII serial port for the MII bit-bang module. 402 */ 403static void 404xl_mii_bitbang_write(device_t dev, uint32_t val) 405{ 406 struct xl_softc *sc; 407 408 sc = device_get_softc(dev); 409 410 /* We're already in window 4. */ 411 CSR_WRITE_2(sc, XL_W4_PHY_MGMT, val); 412 CSR_BARRIER(sc, XL_W4_PHY_MGMT, 2, 413 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 414} 415 416static int 417xl_miibus_readreg(device_t dev, int phy, int reg) 418{ 419 struct xl_softc *sc; 420 421 sc = device_get_softc(dev); 422 423 /* Select the window 4. */ 424 XL_SEL_WIN(4); 425 426 return (mii_bitbang_readreg(dev, &xl_mii_bitbang_ops, phy, reg)); 427} 428 429static int 430xl_miibus_writereg(device_t dev, int phy, int reg, int data) 431{ 432 struct xl_softc *sc; 433 434 sc = device_get_softc(dev); 435 436 /* Select the window 4. */ 437 XL_SEL_WIN(4); 438 439 mii_bitbang_writereg(dev, &xl_mii_bitbang_ops, phy, reg, data); 440 441 return (0); 442} 443 444static void 445xl_miibus_statchg(device_t dev) 446{ 447 struct xl_softc *sc; 448 struct mii_data *mii; 449 uint8_t macctl; 450 451 sc = device_get_softc(dev); 452 mii = device_get_softc(sc->xl_miibus); 453 454 xl_setcfg(sc); 455 456 /* Set ASIC's duplex mode to match the PHY. */ 457 XL_SEL_WIN(3); 458 macctl = CSR_READ_1(sc, XL_W3_MAC_CTRL); 459 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 460 macctl |= XL_MACCTRL_DUPLEX; 461 if (sc->xl_type == XL_TYPE_905B) { 462 if ((IFM_OPTIONS(mii->mii_media_active) & 463 IFM_ETH_RXPAUSE) != 0) 464 macctl |= XL_MACCTRL_FLOW_CONTROL_ENB; 465 else 466 macctl &= ~XL_MACCTRL_FLOW_CONTROL_ENB; 467 } 468 } else { 469 macctl &= ~XL_MACCTRL_DUPLEX; 470 if (sc->xl_type == XL_TYPE_905B) 471 macctl &= ~XL_MACCTRL_FLOW_CONTROL_ENB; 472 } 473 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, macctl); 474} 475 476/* 477 * Special support for the 3c905B-COMBO. This card has 10/100 support 478 * plus BNC and AUI ports. This means we will have both an miibus attached 479 * plus some non-MII media settings. In order to allow this, we have to 480 * add the extra media to the miibus's ifmedia struct, but we can't do 481 * that during xl_attach() because the miibus hasn't been attached yet. 482 * So instead, we wait until the miibus probe/attach is done, at which 483 * point we will get a callback telling is that it's safe to add our 484 * extra media. 485 */ 486static void 487xl_miibus_mediainit(device_t dev) 488{ 489 struct xl_softc *sc; 490 struct mii_data *mii; 491 struct ifmedia *ifm; 492 493 sc = device_get_softc(dev); 494 mii = device_get_softc(sc->xl_miibus); 495 ifm = &mii->mii_media; 496 497 if (sc->xl_media & (XL_MEDIAOPT_AUI | XL_MEDIAOPT_10FL)) { 498 /* 499 * Check for a 10baseFL board in disguise. 500 */ 501 if (sc->xl_type == XL_TYPE_905B && 502 sc->xl_media == XL_MEDIAOPT_10FL) { 503 if (bootverbose) 504 device_printf(sc->xl_dev, "found 10baseFL\n"); 505 ifmedia_add(ifm, IFM_ETHER | IFM_10_FL, 0, NULL); 506 ifmedia_add(ifm, IFM_ETHER | IFM_10_FL|IFM_HDX, 0, 507 NULL); 508 if (sc->xl_caps & XL_CAPS_FULL_DUPLEX) 509 ifmedia_add(ifm, 510 IFM_ETHER | IFM_10_FL | IFM_FDX, 0, NULL); 511 } else { 512 if (bootverbose) 513 device_printf(sc->xl_dev, "found AUI\n"); 514 ifmedia_add(ifm, IFM_ETHER | IFM_10_5, 0, NULL); 515 } 516 } 517 518 if (sc->xl_media & XL_MEDIAOPT_BNC) { 519 if (bootverbose) 520 device_printf(sc->xl_dev, "found BNC\n"); 521 ifmedia_add(ifm, IFM_ETHER | IFM_10_2, 0, NULL); 522 } 523} 524 525/* 526 * The EEPROM is slow: give it time to come ready after issuing 527 * it a command. 528 */ 529static int 530xl_eeprom_wait(struct xl_softc *sc) 531{ 532 int i; 533 534 for (i = 0; i < 100; i++) { 535 if (CSR_READ_2(sc, XL_W0_EE_CMD) & XL_EE_BUSY) 536 DELAY(162); 537 else 538 break; 539 } 540 541 if (i == 100) { 542 device_printf(sc->xl_dev, "eeprom failed to come ready\n"); 543 return (1); 544 } 545 546 return (0); 547} 548 549/* 550 * Read a sequence of words from the EEPROM. Note that ethernet address 551 * data is stored in the EEPROM in network byte order. 552 */ 553static int 554xl_read_eeprom(struct xl_softc *sc, caddr_t dest, int off, int cnt, int swap) 555{ 556 int err = 0, i; 557 u_int16_t word = 0, *ptr; 558 559#define EEPROM_5BIT_OFFSET(A) ((((A) << 2) & 0x7F00) | ((A) & 0x003F)) 560#define EEPROM_8BIT_OFFSET(A) ((A) & 0x003F) 561 /* 562 * XXX: WARNING! DANGER! 563 * It's easy to accidentally overwrite the rom content! 564 * Note: the 3c575 uses 8bit EEPROM offsets. 565 */ 566 XL_SEL_WIN(0); 567 568 if (xl_eeprom_wait(sc)) 569 return (1); 570 571 if (sc->xl_flags & XL_FLAG_EEPROM_OFFSET_30) 572 off += 0x30; 573 574 for (i = 0; i < cnt; i++) { 575 if (sc->xl_flags & XL_FLAG_8BITROM) 576 CSR_WRITE_2(sc, XL_W0_EE_CMD, 577 XL_EE_8BIT_READ | EEPROM_8BIT_OFFSET(off + i)); 578 else 579 CSR_WRITE_2(sc, XL_W0_EE_CMD, 580 XL_EE_READ | EEPROM_5BIT_OFFSET(off + i)); 581 err = xl_eeprom_wait(sc); 582 if (err) 583 break; 584 word = CSR_READ_2(sc, XL_W0_EE_DATA); 585 ptr = (u_int16_t *)(dest + (i * 2)); 586 if (swap) 587 *ptr = ntohs(word); 588 else 589 *ptr = word; 590 } 591 592 return (err ? 1 : 0); 593} 594 595static void 596xl_rxfilter(struct xl_softc *sc) 597{ 598 599 if (sc->xl_type == XL_TYPE_905B) 600 xl_rxfilter_90xB(sc); 601 else 602 xl_rxfilter_90x(sc); 603} 604 605/* 606 * NICs older than the 3c905B have only one multicast option, which 607 * is to enable reception of all multicast frames. 608 */ 609static void 610xl_rxfilter_90x(struct xl_softc *sc) 611{ 612 struct ifnet *ifp; 613 struct ifmultiaddr *ifma; 614 u_int8_t rxfilt; 615 616 XL_LOCK_ASSERT(sc); 617 618 ifp = sc->xl_ifp; 619 620 XL_SEL_WIN(5); 621 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER); 622 rxfilt &= ~(XL_RXFILTER_ALLFRAMES | XL_RXFILTER_ALLMULTI | 623 XL_RXFILTER_BROADCAST | XL_RXFILTER_INDIVIDUAL); 624 625 /* Set the individual bit to receive frames for this host only. */ 626 rxfilt |= XL_RXFILTER_INDIVIDUAL; 627 /* Set capture broadcast bit to capture broadcast frames. */ 628 if (ifp->if_flags & IFF_BROADCAST) 629 rxfilt |= XL_RXFILTER_BROADCAST; 630 631 /* If we want promiscuous mode, set the allframes bit. */ 632 if (ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) { 633 if (ifp->if_flags & IFF_PROMISC) 634 rxfilt |= XL_RXFILTER_ALLFRAMES; 635 if (ifp->if_flags & IFF_ALLMULTI) 636 rxfilt |= XL_RXFILTER_ALLMULTI; 637 } else { 638 if_maddr_rlock(ifp); 639 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 640 if (ifma->ifma_addr->sa_family != AF_LINK) 641 continue; 642 rxfilt |= XL_RXFILTER_ALLMULTI; 643 break; 644 } 645 if_maddr_runlock(ifp); 646 } 647 648 CSR_WRITE_2(sc, XL_COMMAND, rxfilt | XL_CMD_RX_SET_FILT); 649 XL_SEL_WIN(7); 650} 651 652/* 653 * 3c905B adapters have a hash filter that we can program. 654 */ 655static void 656xl_rxfilter_90xB(struct xl_softc *sc) 657{ 658 struct ifnet *ifp; 659 struct ifmultiaddr *ifma; 660 int i, mcnt; 661 u_int16_t h; 662 u_int8_t rxfilt; 663 664 XL_LOCK_ASSERT(sc); 665 666 ifp = sc->xl_ifp; 667 668 XL_SEL_WIN(5); 669 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER); 670 rxfilt &= ~(XL_RXFILTER_ALLFRAMES | XL_RXFILTER_ALLMULTI | 671 XL_RXFILTER_BROADCAST | XL_RXFILTER_INDIVIDUAL | 672 XL_RXFILTER_MULTIHASH); 673 674 /* Set the individual bit to receive frames for this host only. */ 675 rxfilt |= XL_RXFILTER_INDIVIDUAL; 676 /* Set capture broadcast bit to capture broadcast frames. */ 677 if (ifp->if_flags & IFF_BROADCAST) 678 rxfilt |= XL_RXFILTER_BROADCAST; 679 680 /* If we want promiscuous mode, set the allframes bit. */ 681 if (ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) { 682 if (ifp->if_flags & IFF_PROMISC) 683 rxfilt |= XL_RXFILTER_ALLFRAMES; 684 if (ifp->if_flags & IFF_ALLMULTI) 685 rxfilt |= XL_RXFILTER_ALLMULTI; 686 } else { 687 /* First, zot all the existing hash bits. */ 688 for (i = 0; i < XL_HASHFILT_SIZE; i++) 689 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_HASH | i); 690 691 /* Now program new ones. */ 692 mcnt = 0; 693 if_maddr_rlock(ifp); 694 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 695 if (ifma->ifma_addr->sa_family != AF_LINK) 696 continue; 697 /* 698 * Note: the 3c905B currently only supports a 64-bit 699 * hash table, which means we really only need 6 bits, 700 * but the manual indicates that future chip revisions 701 * will have a 256-bit hash table, hence the routine 702 * is set up to calculate 8 bits of position info in 703 * case we need it some day. 704 * Note II, The Sequel: _CURRENT_ versions of the 705 * 3c905B have a 256 bit hash table. This means we have 706 * to use all 8 bits regardless. On older cards, the 707 * upper 2 bits will be ignored. Grrrr.... 708 */ 709 h = ether_crc32_be(LLADDR((struct sockaddr_dl *) 710 ifma->ifma_addr), ETHER_ADDR_LEN) & 0xFF; 711 CSR_WRITE_2(sc, XL_COMMAND, 712 h | XL_CMD_RX_SET_HASH | XL_HASH_SET); 713 mcnt++; 714 } 715 if_maddr_runlock(ifp); 716 if (mcnt > 0) 717 rxfilt |= XL_RXFILTER_MULTIHASH; 718 } 719 720 CSR_WRITE_2(sc, XL_COMMAND, rxfilt | XL_CMD_RX_SET_FILT); 721 XL_SEL_WIN(7); 722} 723 724static void 725xl_setcfg(struct xl_softc *sc) 726{ 727 u_int32_t icfg; 728 729 /*XL_LOCK_ASSERT(sc);*/ 730 731 XL_SEL_WIN(3); 732 icfg = CSR_READ_4(sc, XL_W3_INTERNAL_CFG); 733 icfg &= ~XL_ICFG_CONNECTOR_MASK; 734 if (sc->xl_media & XL_MEDIAOPT_MII || 735 sc->xl_media & XL_MEDIAOPT_BT4) 736 icfg |= (XL_XCVR_MII << XL_ICFG_CONNECTOR_BITS); 737 if (sc->xl_media & XL_MEDIAOPT_BTX) 738 icfg |= (XL_XCVR_AUTO << XL_ICFG_CONNECTOR_BITS); 739 740 CSR_WRITE_4(sc, XL_W3_INTERNAL_CFG, icfg); 741 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP); 742} 743 744static void 745xl_setmode(struct xl_softc *sc, int media) 746{ 747 u_int32_t icfg; 748 u_int16_t mediastat; 749 char *pmsg = "", *dmsg = ""; 750 751 XL_LOCK_ASSERT(sc); 752 753 XL_SEL_WIN(4); 754 mediastat = CSR_READ_2(sc, XL_W4_MEDIA_STATUS); 755 XL_SEL_WIN(3); 756 icfg = CSR_READ_4(sc, XL_W3_INTERNAL_CFG); 757 758 if (sc->xl_media & XL_MEDIAOPT_BT) { 759 if (IFM_SUBTYPE(media) == IFM_10_T) { 760 pmsg = "10baseT transceiver"; 761 sc->xl_xcvr = XL_XCVR_10BT; 762 icfg &= ~XL_ICFG_CONNECTOR_MASK; 763 icfg |= (XL_XCVR_10BT << XL_ICFG_CONNECTOR_BITS); 764 mediastat |= XL_MEDIASTAT_LINKBEAT | 765 XL_MEDIASTAT_JABGUARD; 766 mediastat &= ~XL_MEDIASTAT_SQEENB; 767 } 768 } 769 770 if (sc->xl_media & XL_MEDIAOPT_BFX) { 771 if (IFM_SUBTYPE(media) == IFM_100_FX) { 772 pmsg = "100baseFX port"; 773 sc->xl_xcvr = XL_XCVR_100BFX; 774 icfg &= ~XL_ICFG_CONNECTOR_MASK; 775 icfg |= (XL_XCVR_100BFX << XL_ICFG_CONNECTOR_BITS); 776 mediastat |= XL_MEDIASTAT_LINKBEAT; 777 mediastat &= ~XL_MEDIASTAT_SQEENB; 778 } 779 } 780 781 if (sc->xl_media & (XL_MEDIAOPT_AUI|XL_MEDIAOPT_10FL)) { 782 if (IFM_SUBTYPE(media) == IFM_10_5) { 783 pmsg = "AUI port"; 784 sc->xl_xcvr = XL_XCVR_AUI; 785 icfg &= ~XL_ICFG_CONNECTOR_MASK; 786 icfg |= (XL_XCVR_AUI << XL_ICFG_CONNECTOR_BITS); 787 mediastat &= ~(XL_MEDIASTAT_LINKBEAT | 788 XL_MEDIASTAT_JABGUARD); 789 mediastat |= ~XL_MEDIASTAT_SQEENB; 790 } 791 if (IFM_SUBTYPE(media) == IFM_10_FL) { 792 pmsg = "10baseFL transceiver"; 793 sc->xl_xcvr = XL_XCVR_AUI; 794 icfg &= ~XL_ICFG_CONNECTOR_MASK; 795 icfg |= (XL_XCVR_AUI << XL_ICFG_CONNECTOR_BITS); 796 mediastat &= ~(XL_MEDIASTAT_LINKBEAT | 797 XL_MEDIASTAT_JABGUARD); 798 mediastat |= ~XL_MEDIASTAT_SQEENB; 799 } 800 } 801 802 if (sc->xl_media & XL_MEDIAOPT_BNC) { 803 if (IFM_SUBTYPE(media) == IFM_10_2) { 804 pmsg = "AUI port"; 805 sc->xl_xcvr = XL_XCVR_COAX; 806 icfg &= ~XL_ICFG_CONNECTOR_MASK; 807 icfg |= (XL_XCVR_COAX << XL_ICFG_CONNECTOR_BITS); 808 mediastat &= ~(XL_MEDIASTAT_LINKBEAT | 809 XL_MEDIASTAT_JABGUARD | XL_MEDIASTAT_SQEENB); 810 } 811 } 812 813 if ((media & IFM_GMASK) == IFM_FDX || 814 IFM_SUBTYPE(media) == IFM_100_FX) { 815 dmsg = "full"; 816 XL_SEL_WIN(3); 817 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, XL_MACCTRL_DUPLEX); 818 } else { 819 dmsg = "half"; 820 XL_SEL_WIN(3); 821 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, 822 (CSR_READ_1(sc, XL_W3_MAC_CTRL) & ~XL_MACCTRL_DUPLEX)); 823 } 824 825 if (IFM_SUBTYPE(media) == IFM_10_2) 826 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_START); 827 else 828 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP); 829 830 CSR_WRITE_4(sc, XL_W3_INTERNAL_CFG, icfg); 831 XL_SEL_WIN(4); 832 CSR_WRITE_2(sc, XL_W4_MEDIA_STATUS, mediastat); 833 834 DELAY(800); 835 XL_SEL_WIN(7); 836 837 device_printf(sc->xl_dev, "selecting %s, %s duplex\n", pmsg, dmsg); 838} 839 840static void 841xl_reset(struct xl_softc *sc) 842{ 843 int i; 844 845 XL_LOCK_ASSERT(sc); 846 847 XL_SEL_WIN(0); 848 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RESET | 849 ((sc->xl_flags & XL_FLAG_WEIRDRESET) ? 850 XL_RESETOPT_DISADVFD:0)); 851 852 /* 853 * If we're using memory mapped register mode, pause briefly 854 * after issuing the reset command before trying to access any 855 * other registers. With my 3c575C CardBus card, failing to do 856 * this results in the system locking up while trying to poll 857 * the command busy bit in the status register. 858 */ 859 if (sc->xl_flags & XL_FLAG_USE_MMIO) 860 DELAY(100000); 861 862 for (i = 0; i < XL_TIMEOUT; i++) { 863 DELAY(10); 864 if (!(CSR_READ_2(sc, XL_STATUS) & XL_STAT_CMDBUSY)) 865 break; 866 } 867 868 if (i == XL_TIMEOUT) 869 device_printf(sc->xl_dev, "reset didn't complete\n"); 870 871 /* Reset TX and RX. */ 872 /* Note: the RX reset takes an absurd amount of time 873 * on newer versions of the Tornado chips such as those 874 * on the 3c905CX and newer 3c908C cards. We wait an 875 * extra amount of time so that xl_wait() doesn't complain 876 * and annoy the users. 877 */ 878 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET); 879 DELAY(100000); 880 xl_wait(sc); 881 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET); 882 xl_wait(sc); 883 884 if (sc->xl_flags & XL_FLAG_INVERT_LED_PWR || 885 sc->xl_flags & XL_FLAG_INVERT_MII_PWR) { 886 XL_SEL_WIN(2); 887 CSR_WRITE_2(sc, XL_W2_RESET_OPTIONS, 888 CSR_READ_2(sc, XL_W2_RESET_OPTIONS) | 889 ((sc->xl_flags & XL_FLAG_INVERT_LED_PWR) ? 890 XL_RESETOPT_INVERT_LED : 0) | 891 ((sc->xl_flags & XL_FLAG_INVERT_MII_PWR) ? 892 XL_RESETOPT_INVERT_MII : 0)); 893 } 894 895 /* Wait a little while for the chip to get its brains in order. */ 896 DELAY(100000); 897} 898 899/* 900 * Probe for a 3Com Etherlink XL chip. Check the PCI vendor and device 901 * IDs against our list and return a device name if we find a match. 902 */ 903static int 904xl_probe(device_t dev) 905{ 906 const struct xl_type *t; 907 908 t = xl_devs; 909 910 while (t->xl_name != NULL) { 911 if ((pci_get_vendor(dev) == t->xl_vid) && 912 (pci_get_device(dev) == t->xl_did)) { 913 device_set_desc(dev, t->xl_name); 914 return (BUS_PROBE_DEFAULT); 915 } 916 t++; 917 } 918 919 return (ENXIO); 920} 921 922/* 923 * This routine is a kludge to work around possible hardware faults 924 * or manufacturing defects that can cause the media options register 925 * (or reset options register, as it's called for the first generation 926 * 3c90x adapters) to return an incorrect result. I have encountered 927 * one Dell Latitude laptop docking station with an integrated 3c905-TX 928 * which doesn't have any of the 'mediaopt' bits set. This screws up 929 * the attach routine pretty badly because it doesn't know what media 930 * to look for. If we find ourselves in this predicament, this routine 931 * will try to guess the media options values and warn the user of a 932 * possible manufacturing defect with his adapter/system/whatever. 933 */ 934static void 935xl_mediacheck(struct xl_softc *sc) 936{ 937 938 /* 939 * If some of the media options bits are set, assume they are 940 * correct. If not, try to figure it out down below. 941 * XXX I should check for 10baseFL, but I don't have an adapter 942 * to test with. 943 */ 944 if (sc->xl_media & (XL_MEDIAOPT_MASK & ~XL_MEDIAOPT_VCO)) { 945 /* 946 * Check the XCVR value. If it's not in the normal range 947 * of values, we need to fake it up here. 948 */ 949 if (sc->xl_xcvr <= XL_XCVR_AUTO) 950 return; 951 else { 952 device_printf(sc->xl_dev, 953 "bogus xcvr value in EEPROM (%x)\n", sc->xl_xcvr); 954 device_printf(sc->xl_dev, 955 "choosing new default based on card type\n"); 956 } 957 } else { 958 if (sc->xl_type == XL_TYPE_905B && 959 sc->xl_media & XL_MEDIAOPT_10FL) 960 return; 961 device_printf(sc->xl_dev, 962"WARNING: no media options bits set in the media options register!!\n"); 963 device_printf(sc->xl_dev, 964"this could be a manufacturing defect in your adapter or system\n"); 965 device_printf(sc->xl_dev, 966"attempting to guess media type; you should probably consult your vendor\n"); 967 } 968 969 xl_choose_xcvr(sc, 1); 970} 971 972static void 973xl_choose_xcvr(struct xl_softc *sc, int verbose) 974{ 975 u_int16_t devid; 976 977 /* 978 * Read the device ID from the EEPROM. 979 * This is what's loaded into the PCI device ID register, so it has 980 * to be correct otherwise we wouldn't have gotten this far. 981 */ 982 xl_read_eeprom(sc, (caddr_t)&devid, XL_EE_PRODID, 1, 0); 983 984 switch (devid) { 985 case TC_DEVICEID_BOOMERANG_10BT: /* 3c900-TPO */ 986 case TC_DEVICEID_KRAKATOA_10BT: /* 3c900B-TPO */ 987 sc->xl_media = XL_MEDIAOPT_BT; 988 sc->xl_xcvr = XL_XCVR_10BT; 989 if (verbose) 990 device_printf(sc->xl_dev, 991 "guessing 10BaseT transceiver\n"); 992 break; 993 case TC_DEVICEID_BOOMERANG_10BT_COMBO: /* 3c900-COMBO */ 994 case TC_DEVICEID_KRAKATOA_10BT_COMBO: /* 3c900B-COMBO */ 995 sc->xl_media = XL_MEDIAOPT_BT|XL_MEDIAOPT_BNC|XL_MEDIAOPT_AUI; 996 sc->xl_xcvr = XL_XCVR_10BT; 997 if (verbose) 998 device_printf(sc->xl_dev, 999 "guessing COMBO (AUI/BNC/TP)\n"); 1000 break; 1001 case TC_DEVICEID_KRAKATOA_10BT_TPC: /* 3c900B-TPC */ 1002 sc->xl_media = XL_MEDIAOPT_BT|XL_MEDIAOPT_BNC; 1003 sc->xl_xcvr = XL_XCVR_10BT; 1004 if (verbose) 1005 device_printf(sc->xl_dev, "guessing TPC (BNC/TP)\n"); 1006 break; 1007 case TC_DEVICEID_CYCLONE_10FL: /* 3c900B-FL */ 1008 sc->xl_media = XL_MEDIAOPT_10FL; 1009 sc->xl_xcvr = XL_XCVR_AUI; 1010 if (verbose) 1011 device_printf(sc->xl_dev, "guessing 10baseFL\n"); 1012 break; 1013 case TC_DEVICEID_BOOMERANG_10_100BT: /* 3c905-TX */ 1014 case TC_DEVICEID_HURRICANE_555: /* 3c555 */ 1015 case TC_DEVICEID_HURRICANE_556: /* 3c556 */ 1016 case TC_DEVICEID_HURRICANE_556B: /* 3c556B */ 1017 case TC_DEVICEID_HURRICANE_575A: /* 3c575TX */ 1018 case TC_DEVICEID_HURRICANE_575B: /* 3c575B */ 1019 case TC_DEVICEID_HURRICANE_575C: /* 3c575C */ 1020 case TC_DEVICEID_HURRICANE_656: /* 3c656 */ 1021 case TC_DEVICEID_HURRICANE_656B: /* 3c656B */ 1022 case TC_DEVICEID_TORNADO_656C: /* 3c656C */ 1023 case TC_DEVICEID_TORNADO_10_100BT_920B: /* 3c920B-EMB */ 1024 case TC_DEVICEID_TORNADO_10_100BT_920B_WNM: /* 3c920B-EMB-WNM */ 1025 sc->xl_media = XL_MEDIAOPT_MII; 1026 sc->xl_xcvr = XL_XCVR_MII; 1027 if (verbose) 1028 device_printf(sc->xl_dev, "guessing MII\n"); 1029 break; 1030 case TC_DEVICEID_BOOMERANG_100BT4: /* 3c905-T4 */ 1031 case TC_DEVICEID_CYCLONE_10_100BT4: /* 3c905B-T4 */ 1032 sc->xl_media = XL_MEDIAOPT_BT4; 1033 sc->xl_xcvr = XL_XCVR_MII; 1034 if (verbose) 1035 device_printf(sc->xl_dev, "guessing 100baseT4/MII\n"); 1036 break; 1037 case TC_DEVICEID_HURRICANE_10_100BT: /* 3c905B-TX */ 1038 case TC_DEVICEID_HURRICANE_10_100BT_SERV:/*3c980-TX */ 1039 case TC_DEVICEID_TORNADO_10_100BT_SERV: /* 3c980C-TX */ 1040 case TC_DEVICEID_HURRICANE_SOHO100TX: /* 3cSOHO100-TX */ 1041 case TC_DEVICEID_TORNADO_10_100BT: /* 3c905C-TX */ 1042 case TC_DEVICEID_TORNADO_HOMECONNECT: /* 3c450-TX */ 1043 sc->xl_media = XL_MEDIAOPT_BTX; 1044 sc->xl_xcvr = XL_XCVR_AUTO; 1045 if (verbose) 1046 device_printf(sc->xl_dev, "guessing 10/100 internal\n"); 1047 break; 1048 case TC_DEVICEID_CYCLONE_10_100_COMBO: /* 3c905B-COMBO */ 1049 sc->xl_media = XL_MEDIAOPT_BTX|XL_MEDIAOPT_BNC|XL_MEDIAOPT_AUI; 1050 sc->xl_xcvr = XL_XCVR_AUTO; 1051 if (verbose) 1052 device_printf(sc->xl_dev, 1053 "guessing 10/100 plus BNC/AUI\n"); 1054 break; 1055 default: 1056 device_printf(sc->xl_dev, 1057 "unknown device ID: %x -- defaulting to 10baseT\n", devid); 1058 sc->xl_media = XL_MEDIAOPT_BT; 1059 break; 1060 } 1061} 1062 1063/* 1064 * Attach the interface. Allocate softc structures, do ifmedia 1065 * setup and ethernet/BPF attach. 1066 */ 1067static int 1068xl_attach(device_t dev) 1069{ 1070 u_char eaddr[ETHER_ADDR_LEN]; 1071 u_int16_t sinfo2, xcvr[2]; 1072 struct xl_softc *sc; 1073 struct ifnet *ifp; 1074 int media, pmcap; 1075 int error = 0, phy, rid, res, unit; 1076 uint16_t did; 1077 1078 sc = device_get_softc(dev); 1079 sc->xl_dev = dev; 1080 1081 unit = device_get_unit(dev); 1082 1083 mtx_init(&sc->xl_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 1084 MTX_DEF); 1085 ifmedia_init(&sc->ifmedia, 0, xl_ifmedia_upd, xl_ifmedia_sts); 1086 1087 did = pci_get_device(dev); 1088 1089 sc->xl_flags = 0; 1090 if (did == TC_DEVICEID_HURRICANE_555) 1091 sc->xl_flags |= XL_FLAG_EEPROM_OFFSET_30 | XL_FLAG_PHYOK; 1092 if (did == TC_DEVICEID_HURRICANE_556 || 1093 did == TC_DEVICEID_HURRICANE_556B) 1094 sc->xl_flags |= XL_FLAG_FUNCREG | XL_FLAG_PHYOK | 1095 XL_FLAG_EEPROM_OFFSET_30 | XL_FLAG_WEIRDRESET | 1096 XL_FLAG_INVERT_LED_PWR | XL_FLAG_INVERT_MII_PWR; 1097 if (did == TC_DEVICEID_HURRICANE_555 || 1098 did == TC_DEVICEID_HURRICANE_556) 1099 sc->xl_flags |= XL_FLAG_8BITROM; 1100 if (did == TC_DEVICEID_HURRICANE_556B) 1101 sc->xl_flags |= XL_FLAG_NO_XCVR_PWR; 1102 1103 if (did == TC_DEVICEID_HURRICANE_575B || 1104 did == TC_DEVICEID_HURRICANE_575C || 1105 did == TC_DEVICEID_HURRICANE_656B || 1106 did == TC_DEVICEID_TORNADO_656C) 1107 sc->xl_flags |= XL_FLAG_FUNCREG; 1108 if (did == TC_DEVICEID_HURRICANE_575A || 1109 did == TC_DEVICEID_HURRICANE_575B || 1110 did == TC_DEVICEID_HURRICANE_575C || 1111 did == TC_DEVICEID_HURRICANE_656B || 1112 did == TC_DEVICEID_TORNADO_656C) 1113 sc->xl_flags |= XL_FLAG_PHYOK | XL_FLAG_EEPROM_OFFSET_30 | 1114 XL_FLAG_8BITROM; 1115 if (did == TC_DEVICEID_HURRICANE_656) 1116 sc->xl_flags |= XL_FLAG_FUNCREG | XL_FLAG_PHYOK; 1117 if (did == TC_DEVICEID_HURRICANE_575B) 1118 sc->xl_flags |= XL_FLAG_INVERT_LED_PWR; 1119 if (did == TC_DEVICEID_HURRICANE_575C) 1120 sc->xl_flags |= XL_FLAG_INVERT_MII_PWR; 1121 if (did == TC_DEVICEID_TORNADO_656C) 1122 sc->xl_flags |= XL_FLAG_INVERT_MII_PWR; 1123 if (did == TC_DEVICEID_HURRICANE_656 || 1124 did == TC_DEVICEID_HURRICANE_656B) 1125 sc->xl_flags |= XL_FLAG_INVERT_MII_PWR | 1126 XL_FLAG_INVERT_LED_PWR; 1127 if (did == TC_DEVICEID_TORNADO_10_100BT_920B || 1128 did == TC_DEVICEID_TORNADO_10_100BT_920B_WNM) 1129 sc->xl_flags |= XL_FLAG_PHYOK; 1130 1131 switch (did) { 1132#ifdef __HAIKU__ 1133 case TC_DEVICEID_BOOMERANG_10BT_COMBO: 1134#endif 1135 case TC_DEVICEID_BOOMERANG_10_100BT: /* 3c905-TX */ 1136 case TC_DEVICEID_HURRICANE_575A: 1137 case TC_DEVICEID_HURRICANE_575B: 1138 case TC_DEVICEID_HURRICANE_575C: 1139 sc->xl_flags |= XL_FLAG_NO_MMIO; 1140 break; 1141 default: 1142 break; 1143 } 1144 1145 /* 1146 * Map control/status registers. 1147 */ 1148 pci_enable_busmaster(dev); 1149 1150 if ((sc->xl_flags & XL_FLAG_NO_MMIO) == 0) { 1151 rid = XL_PCI_LOMEM; 1152 res = SYS_RES_MEMORY; 1153 1154 sc->xl_res = bus_alloc_resource_any(dev, res, &rid, RF_ACTIVE); 1155 } 1156 1157 if (sc->xl_res != NULL) { 1158 sc->xl_flags |= XL_FLAG_USE_MMIO; 1159 if (bootverbose) 1160 device_printf(dev, "using memory mapped I/O\n"); 1161 } else { 1162 rid = XL_PCI_LOIO; 1163 res = SYS_RES_IOPORT; 1164 sc->xl_res = bus_alloc_resource_any(dev, res, &rid, RF_ACTIVE); 1165 if (sc->xl_res == NULL) { 1166 device_printf(dev, "couldn't map ports/memory\n"); 1167 error = ENXIO; 1168 goto fail; 1169 } 1170 if (bootverbose) 1171 device_printf(dev, "using port I/O\n"); 1172 } 1173 1174 sc->xl_btag = rman_get_bustag(sc->xl_res); 1175 sc->xl_bhandle = rman_get_bushandle(sc->xl_res); 1176 1177 if (sc->xl_flags & XL_FLAG_FUNCREG) { 1178 rid = XL_PCI_FUNCMEM; 1179 sc->xl_fres = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 1180 RF_ACTIVE); 1181 1182 if (sc->xl_fres == NULL) { 1183 device_printf(dev, "couldn't map funcreg memory\n"); 1184 error = ENXIO; 1185 goto fail; 1186 } 1187 1188 sc->xl_ftag = rman_get_bustag(sc->xl_fres); 1189 sc->xl_fhandle = rman_get_bushandle(sc->xl_fres); 1190 } 1191 1192 /* Allocate interrupt */ 1193 rid = 0; 1194 sc->xl_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1195 RF_SHAREABLE | RF_ACTIVE); 1196 if (sc->xl_irq == NULL) { 1197 device_printf(dev, "couldn't map interrupt\n"); 1198 error = ENXIO; 1199 goto fail; 1200 } 1201 1202 /* Initialize interface name. */ 1203 ifp = sc->xl_ifp = if_alloc(IFT_ETHER); 1204 if (ifp == NULL) { 1205 device_printf(dev, "can not if_alloc()\n"); 1206 error = ENOSPC; 1207 goto fail; 1208 } 1209 ifp->if_softc = sc; 1210 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1211 1212 /* Reset the adapter. */ 1213 XL_LOCK(sc); 1214 xl_reset(sc); 1215 XL_UNLOCK(sc); 1216 1217 /* 1218 * Get station address from the EEPROM. 1219 */ 1220 if (xl_read_eeprom(sc, (caddr_t)&eaddr, XL_EE_OEM_ADR0, 3, 1)) { 1221 device_printf(dev, "failed to read station address\n"); 1222 error = ENXIO; 1223 goto fail; 1224 } 1225 1226 callout_init_mtx(&sc->xl_tick_callout, &sc->xl_mtx, 0); 1227 TASK_INIT(&sc->xl_task, 0, xl_rxeof_task, sc); 1228 1229 /* 1230 * Now allocate a tag for the DMA descriptor lists and a chunk 1231 * of DMA-able memory based on the tag. Also obtain the DMA 1232 * addresses of the RX and TX ring, which we'll need later. 1233 * All of our lists are allocated as a contiguous block 1234 * of memory. 1235 */ 1236 error = bus_dma_tag_create(bus_get_dma_tag(dev), 8, 0, 1237 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 1238 XL_RX_LIST_SZ, 1, XL_RX_LIST_SZ, 0, NULL, NULL, 1239 &sc->xl_ldata.xl_rx_tag); 1240 if (error) { 1241 device_printf(dev, "failed to allocate rx dma tag\n"); 1242 goto fail; 1243 } 1244 1245 error = bus_dmamem_alloc(sc->xl_ldata.xl_rx_tag, 1246 (void **)&sc->xl_ldata.xl_rx_list, BUS_DMA_NOWAIT | 1247 BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc->xl_ldata.xl_rx_dmamap); 1248 if (error) { 1249 device_printf(dev, "no memory for rx list buffers!\n"); 1250 bus_dma_tag_destroy(sc->xl_ldata.xl_rx_tag); 1251 sc->xl_ldata.xl_rx_tag = NULL; 1252 goto fail; 1253 } 1254 1255 error = bus_dmamap_load(sc->xl_ldata.xl_rx_tag, 1256 sc->xl_ldata.xl_rx_dmamap, sc->xl_ldata.xl_rx_list, 1257 XL_RX_LIST_SZ, xl_dma_map_addr, 1258 &sc->xl_ldata.xl_rx_dmaaddr, BUS_DMA_NOWAIT); 1259 if (error) { 1260 device_printf(dev, "cannot get dma address of the rx ring!\n"); 1261 bus_dmamem_free(sc->xl_ldata.xl_rx_tag, sc->xl_ldata.xl_rx_list, 1262 sc->xl_ldata.xl_rx_dmamap); 1263 bus_dma_tag_destroy(sc->xl_ldata.xl_rx_tag); 1264 sc->xl_ldata.xl_rx_tag = NULL; 1265 goto fail; 1266 } 1267 1268 error = bus_dma_tag_create(bus_get_dma_tag(dev), 8, 0, 1269 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 1270 XL_TX_LIST_SZ, 1, XL_TX_LIST_SZ, 0, NULL, NULL, 1271 &sc->xl_ldata.xl_tx_tag); 1272 if (error) { 1273 device_printf(dev, "failed to allocate tx dma tag\n"); 1274 goto fail; 1275 } 1276 1277 error = bus_dmamem_alloc(sc->xl_ldata.xl_tx_tag, 1278 (void **)&sc->xl_ldata.xl_tx_list, BUS_DMA_NOWAIT | 1279 BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc->xl_ldata.xl_tx_dmamap); 1280 if (error) { 1281 device_printf(dev, "no memory for list buffers!\n"); 1282 bus_dma_tag_destroy(sc->xl_ldata.xl_tx_tag); 1283 sc->xl_ldata.xl_tx_tag = NULL; 1284 goto fail; 1285 } 1286 1287 error = bus_dmamap_load(sc->xl_ldata.xl_tx_tag, 1288 sc->xl_ldata.xl_tx_dmamap, sc->xl_ldata.xl_tx_list, 1289 XL_TX_LIST_SZ, xl_dma_map_addr, 1290 &sc->xl_ldata.xl_tx_dmaaddr, BUS_DMA_NOWAIT); 1291 if (error) { 1292 device_printf(dev, "cannot get dma address of the tx ring!\n"); 1293 bus_dmamem_free(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_list, 1294 sc->xl_ldata.xl_tx_dmamap); 1295 bus_dma_tag_destroy(sc->xl_ldata.xl_tx_tag); 1296 sc->xl_ldata.xl_tx_tag = NULL; 1297 goto fail; 1298 } 1299 1300 /* 1301 * Allocate a DMA tag for the mapping of mbufs. 1302 */ 1303 error = bus_dma_tag_create(bus_get_dma_tag(dev), 1, 0, 1304 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 1305 MCLBYTES * XL_MAXFRAGS, XL_MAXFRAGS, MCLBYTES, 0, NULL, 1306 NULL, &sc->xl_mtag); 1307 if (error) { 1308 device_printf(dev, "failed to allocate mbuf dma tag\n"); 1309 goto fail; 1310 } 1311 1312 /* We need a spare DMA map for the RX ring. */ 1313 error = bus_dmamap_create(sc->xl_mtag, 0, &sc->xl_tmpmap); 1314 if (error) 1315 goto fail; 1316 1317 /* 1318 * Figure out the card type. 3c905B adapters have the 1319 * 'supportsNoTxLength' bit set in the capabilities 1320 * word in the EEPROM. 1321 * Note: my 3c575C CardBus card lies. It returns a value 1322 * of 0x1578 for its capabilities word, which is somewhat 1323 * nonsensical. Another way to distinguish a 3c90x chip 1324 * from a 3c90xB/C chip is to check for the 'supportsLargePackets' 1325 * bit. This will only be set for 3c90x boomerage chips. 1326 */ 1327 xl_read_eeprom(sc, (caddr_t)&sc->xl_caps, XL_EE_CAPS, 1, 0); 1328 if (sc->xl_caps & XL_CAPS_NO_TXLENGTH || 1329 !(sc->xl_caps & XL_CAPS_LARGE_PKTS)) 1330 sc->xl_type = XL_TYPE_905B; 1331 else 1332 sc->xl_type = XL_TYPE_90X; 1333 1334 /* Check availability of WOL. */ 1335 if ((sc->xl_caps & XL_CAPS_PWRMGMT) != 0 && 1336 pci_find_cap(dev, PCIY_PMG, &pmcap) == 0) { 1337 sc->xl_pmcap = pmcap; 1338 sc->xl_flags |= XL_FLAG_WOL; 1339 sinfo2 = 0; 1340 xl_read_eeprom(sc, (caddr_t)&sinfo2, XL_EE_SOFTINFO2, 1, 0); 1341 if ((sinfo2 & XL_SINFO2_AUX_WOL_CON) == 0 && bootverbose) 1342 device_printf(dev, 1343 "No auxiliary remote wakeup connector!\n"); 1344 } 1345 1346 /* Set the TX start threshold for best performance. */ 1347 sc->xl_tx_thresh = XL_MIN_FRAMELEN; 1348 1349 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1350 ifp->if_ioctl = xl_ioctl; 1351 ifp->if_capabilities = IFCAP_VLAN_MTU; 1352 if (sc->xl_type == XL_TYPE_905B) { 1353 ifp->if_hwassist = XL905B_CSUM_FEATURES; 1354#ifdef XL905B_TXCSUM_BROKEN 1355 ifp->if_capabilities |= IFCAP_RXCSUM; 1356#else 1357 ifp->if_capabilities |= IFCAP_HWCSUM; 1358#endif 1359 } 1360 if ((sc->xl_flags & XL_FLAG_WOL) != 0) 1361 ifp->if_capabilities |= IFCAP_WOL_MAGIC; 1362 ifp->if_capenable = ifp->if_capabilities; 1363#ifdef DEVICE_POLLING 1364 ifp->if_capabilities |= IFCAP_POLLING; 1365#endif 1366 ifp->if_start = xl_start; 1367 ifp->if_init = xl_init; 1368 IFQ_SET_MAXLEN(&ifp->if_snd, XL_TX_LIST_CNT - 1); 1369 ifp->if_snd.ifq_drv_maxlen = XL_TX_LIST_CNT - 1; 1370 IFQ_SET_READY(&ifp->if_snd); 1371 1372 /* 1373 * Now we have to see what sort of media we have. 1374 * This includes probing for an MII interace and a 1375 * possible PHY. 1376 */ 1377 XL_SEL_WIN(3); 1378 sc->xl_media = CSR_READ_2(sc, XL_W3_MEDIA_OPT); 1379 if (bootverbose) 1380 device_printf(dev, "media options word: %x\n", sc->xl_media); 1381 1382 xl_read_eeprom(sc, (char *)&xcvr, XL_EE_ICFG_0, 2, 0); 1383 sc->xl_xcvr = xcvr[0] | xcvr[1] << 16; 1384 sc->xl_xcvr &= XL_ICFG_CONNECTOR_MASK; 1385 sc->xl_xcvr >>= XL_ICFG_CONNECTOR_BITS; 1386 1387#ifdef __HAIKU__ 1388 if (did == TC_DEVICEID_BOOMERANG_10BT_COMBO) 1389 sc->xl_xcvr = XL_XCVR_10BT; 1390#endif 1391 1392 xl_mediacheck(sc); 1393 1394 if (sc->xl_media & XL_MEDIAOPT_MII || 1395 sc->xl_media & XL_MEDIAOPT_BTX || 1396 sc->xl_media & XL_MEDIAOPT_BT4) { 1397 if (bootverbose) 1398 device_printf(dev, "found MII/AUTO\n"); 1399 xl_setcfg(sc); 1400 /* 1401 * Attach PHYs only at MII address 24 if !XL_FLAG_PHYOK. 1402 * This is to guard against problems with certain 3Com ASIC 1403 * revisions that incorrectly map the internal transceiver 1404 * control registers at all MII addresses. 1405 */ 1406 phy = MII_PHY_ANY; 1407 if ((sc->xl_flags & XL_FLAG_PHYOK) == 0) 1408 phy = 24; 1409 error = mii_attach(dev, &sc->xl_miibus, ifp, xl_ifmedia_upd, 1410 xl_ifmedia_sts, BMSR_DEFCAPMASK, phy, MII_OFFSET_ANY, 1411 sc->xl_type == XL_TYPE_905B ? MIIF_DOPAUSE : 0); 1412 if (error != 0) { 1413 device_printf(dev, "attaching PHYs failed\n"); 1414 goto fail; 1415 } 1416 goto done; 1417 } 1418 1419 /* 1420 * Sanity check. If the user has selected "auto" and this isn't 1421 * a 10/100 card of some kind, we need to force the transceiver 1422 * type to something sane. 1423 */ 1424 if (sc->xl_xcvr == XL_XCVR_AUTO) 1425 xl_choose_xcvr(sc, bootverbose); 1426 1427 /* 1428 * Do ifmedia setup. 1429 */ 1430 if (sc->xl_media & XL_MEDIAOPT_BT) { 1431 if (bootverbose) 1432 device_printf(dev, "found 10baseT\n"); 1433 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T, 0, NULL); 1434 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T|IFM_HDX, 0, NULL); 1435 if (sc->xl_caps & XL_CAPS_FULL_DUPLEX) 1436 ifmedia_add(&sc->ifmedia, 1437 IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL); 1438 } 1439 1440 if (sc->xl_media & (XL_MEDIAOPT_AUI|XL_MEDIAOPT_10FL)) { 1441 /* 1442 * Check for a 10baseFL board in disguise. 1443 */ 1444 if (sc->xl_type == XL_TYPE_905B && 1445 sc->xl_media == XL_MEDIAOPT_10FL) { 1446 if (bootverbose) 1447 device_printf(dev, "found 10baseFL\n"); 1448 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_FL, 0, NULL); 1449 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_FL|IFM_HDX, 1450 0, NULL); 1451 if (sc->xl_caps & XL_CAPS_FULL_DUPLEX) 1452 ifmedia_add(&sc->ifmedia, 1453 IFM_ETHER|IFM_10_FL|IFM_FDX, 0, NULL); 1454 } else { 1455 if (bootverbose) 1456 device_printf(dev, "found AUI\n"); 1457 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_5, 0, NULL); 1458 } 1459 } 1460 1461 if (sc->xl_media & XL_MEDIAOPT_BNC) { 1462 if (bootverbose) 1463 device_printf(dev, "found BNC\n"); 1464 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_2, 0, NULL); 1465 } 1466 1467 if (sc->xl_media & XL_MEDIAOPT_BFX) { 1468 if (bootverbose) 1469 device_printf(dev, "found 100baseFX\n"); 1470 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_FX, 0, NULL); 1471 } 1472 1473 media = IFM_ETHER|IFM_100_TX|IFM_FDX; 1474 xl_choose_media(sc, &media); 1475 1476 if (sc->xl_miibus == NULL) 1477 ifmedia_set(&sc->ifmedia, media); 1478 1479done: 1480 if (sc->xl_flags & XL_FLAG_NO_XCVR_PWR) { 1481 XL_SEL_WIN(0); 1482 CSR_WRITE_2(sc, XL_W0_MFG_ID, XL_NO_XCVR_PWR_MAGICBITS); 1483 } 1484 1485 /* 1486 * Call MI attach routine. 1487 */ 1488 ether_ifattach(ifp, eaddr); 1489 1490 error = bus_setup_intr(dev, sc->xl_irq, INTR_TYPE_NET | INTR_MPSAFE, 1491 NULL, xl_intr, sc, &sc->xl_intrhand); 1492 if (error) { 1493 device_printf(dev, "couldn't set up irq\n"); 1494 ether_ifdetach(ifp); 1495 goto fail; 1496 } 1497 1498fail: 1499 if (error) 1500 xl_detach(dev); 1501 1502 return (error); 1503} 1504 1505/* 1506 * Choose a default media. 1507 * XXX This is a leaf function only called by xl_attach() and 1508 * acquires/releases the non-recursible driver mutex to 1509 * satisfy lock assertions. 1510 */ 1511static void 1512xl_choose_media(struct xl_softc *sc, int *media) 1513{ 1514 1515 XL_LOCK(sc); 1516 1517 switch (sc->xl_xcvr) { 1518 case XL_XCVR_10BT: 1519 *media = IFM_ETHER|IFM_10_T; 1520 xl_setmode(sc, *media); 1521 break; 1522 case XL_XCVR_AUI: 1523 if (sc->xl_type == XL_TYPE_905B && 1524 sc->xl_media == XL_MEDIAOPT_10FL) { 1525 *media = IFM_ETHER|IFM_10_FL; 1526 xl_setmode(sc, *media); 1527 } else { 1528 *media = IFM_ETHER|IFM_10_5; 1529 xl_setmode(sc, *media); 1530 } 1531 break; 1532 case XL_XCVR_COAX: 1533 *media = IFM_ETHER|IFM_10_2; 1534 xl_setmode(sc, *media); 1535 break; 1536 case XL_XCVR_AUTO: 1537 case XL_XCVR_100BTX: 1538 case XL_XCVR_MII: 1539 /* Chosen by miibus */ 1540 break; 1541 case XL_XCVR_100BFX: 1542 *media = IFM_ETHER|IFM_100_FX; 1543 break; 1544 default: 1545 device_printf(sc->xl_dev, "unknown XCVR type: %d\n", 1546 sc->xl_xcvr); 1547 /* 1548 * This will probably be wrong, but it prevents 1549 * the ifmedia code from panicking. 1550 */ 1551 *media = IFM_ETHER|IFM_10_T; 1552 break; 1553 } 1554 1555 XL_UNLOCK(sc); 1556} 1557 1558/* 1559 * Shutdown hardware and free up resources. This can be called any 1560 * time after the mutex has been initialized. It is called in both 1561 * the error case in attach and the normal detach case so it needs 1562 * to be careful about only freeing resources that have actually been 1563 * allocated. 1564 */ 1565static int 1566xl_detach(device_t dev) 1567{ 1568 struct xl_softc *sc; 1569 struct ifnet *ifp; 1570 int rid, res; 1571 1572 sc = device_get_softc(dev); 1573 ifp = sc->xl_ifp; 1574 1575 KASSERT(mtx_initialized(&sc->xl_mtx), ("xl mutex not initialized")); 1576 1577#ifdef DEVICE_POLLING 1578 if (ifp && ifp->if_capenable & IFCAP_POLLING) 1579 ether_poll_deregister(ifp); 1580#endif 1581 1582 if (sc->xl_flags & XL_FLAG_USE_MMIO) { 1583 rid = XL_PCI_LOMEM; 1584 res = SYS_RES_MEMORY; 1585 } else { 1586 rid = XL_PCI_LOIO; 1587 res = SYS_RES_IOPORT; 1588 } 1589 1590 /* These should only be active if attach succeeded */ 1591 if (device_is_attached(dev)) { 1592 XL_LOCK(sc); 1593 xl_stop(sc); 1594 XL_UNLOCK(sc); 1595 taskqueue_drain(taskqueue_swi, &sc->xl_task); 1596 callout_drain(&sc->xl_tick_callout); 1597 ether_ifdetach(ifp); 1598 } 1599 if (sc->xl_miibus) 1600 device_delete_child(dev, sc->xl_miibus); 1601 bus_generic_detach(dev); 1602 ifmedia_removeall(&sc->ifmedia); 1603 1604 if (sc->xl_intrhand) 1605 bus_teardown_intr(dev, sc->xl_irq, sc->xl_intrhand); 1606 if (sc->xl_irq) 1607 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->xl_irq); 1608 if (sc->xl_fres != NULL) 1609 bus_release_resource(dev, SYS_RES_MEMORY, 1610 XL_PCI_FUNCMEM, sc->xl_fres); 1611 if (sc->xl_res) 1612 bus_release_resource(dev, res, rid, sc->xl_res); 1613 1614 if (ifp) 1615 if_free(ifp); 1616 1617 if (sc->xl_mtag) { 1618 bus_dmamap_destroy(sc->xl_mtag, sc->xl_tmpmap); 1619 bus_dma_tag_destroy(sc->xl_mtag); 1620 } 1621 if (sc->xl_ldata.xl_rx_tag) { 1622 bus_dmamap_unload(sc->xl_ldata.xl_rx_tag, 1623 sc->xl_ldata.xl_rx_dmamap); 1624 bus_dmamem_free(sc->xl_ldata.xl_rx_tag, sc->xl_ldata.xl_rx_list, 1625 sc->xl_ldata.xl_rx_dmamap); 1626 bus_dma_tag_destroy(sc->xl_ldata.xl_rx_tag); 1627 } 1628 if (sc->xl_ldata.xl_tx_tag) { 1629 bus_dmamap_unload(sc->xl_ldata.xl_tx_tag, 1630 sc->xl_ldata.xl_tx_dmamap); 1631 bus_dmamem_free(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_list, 1632 sc->xl_ldata.xl_tx_dmamap); 1633 bus_dma_tag_destroy(sc->xl_ldata.xl_tx_tag); 1634 } 1635 1636 mtx_destroy(&sc->xl_mtx); 1637 1638 return (0); 1639} 1640 1641/* 1642 * Initialize the transmit descriptors. 1643 */ 1644static int 1645xl_list_tx_init(struct xl_softc *sc) 1646{ 1647 struct xl_chain_data *cd; 1648 struct xl_list_data *ld; 1649 int error, i; 1650 1651 XL_LOCK_ASSERT(sc); 1652 1653 cd = &sc->xl_cdata; 1654 ld = &sc->xl_ldata; 1655 for (i = 0; i < XL_TX_LIST_CNT; i++) { 1656 cd->xl_tx_chain[i].xl_ptr = &ld->xl_tx_list[i]; 1657 error = bus_dmamap_create(sc->xl_mtag, 0, 1658 &cd->xl_tx_chain[i].xl_map); 1659 if (error) 1660 return (error); 1661 cd->xl_tx_chain[i].xl_phys = ld->xl_tx_dmaaddr + 1662 i * sizeof(struct xl_list); 1663 if (i == (XL_TX_LIST_CNT - 1)) 1664 cd->xl_tx_chain[i].xl_next = NULL; 1665 else 1666 cd->xl_tx_chain[i].xl_next = &cd->xl_tx_chain[i + 1]; 1667 } 1668 1669 cd->xl_tx_free = &cd->xl_tx_chain[0]; 1670 cd->xl_tx_tail = cd->xl_tx_head = NULL; 1671 1672 bus_dmamap_sync(ld->xl_tx_tag, ld->xl_tx_dmamap, BUS_DMASYNC_PREWRITE); 1673 return (0); 1674} 1675 1676/* 1677 * Initialize the transmit descriptors. 1678 */ 1679static int 1680xl_list_tx_init_90xB(struct xl_softc *sc) 1681{ 1682 struct xl_chain_data *cd; 1683 struct xl_list_data *ld; 1684 int error, i; 1685 1686 XL_LOCK_ASSERT(sc); 1687 1688 cd = &sc->xl_cdata; 1689 ld = &sc->xl_ldata; 1690 for (i = 0; i < XL_TX_LIST_CNT; i++) { 1691 cd->xl_tx_chain[i].xl_ptr = &ld->xl_tx_list[i]; 1692 error = bus_dmamap_create(sc->xl_mtag, 0, 1693 &cd->xl_tx_chain[i].xl_map); 1694 if (error) 1695 return (error); 1696 cd->xl_tx_chain[i].xl_phys = ld->xl_tx_dmaaddr + 1697 i * sizeof(struct xl_list); 1698 if (i == (XL_TX_LIST_CNT - 1)) 1699 cd->xl_tx_chain[i].xl_next = &cd->xl_tx_chain[0]; 1700 else 1701 cd->xl_tx_chain[i].xl_next = &cd->xl_tx_chain[i + 1]; 1702 if (i == 0) 1703 cd->xl_tx_chain[i].xl_prev = 1704 &cd->xl_tx_chain[XL_TX_LIST_CNT - 1]; 1705 else 1706 cd->xl_tx_chain[i].xl_prev = 1707 &cd->xl_tx_chain[i - 1]; 1708 } 1709 1710 bzero(ld->xl_tx_list, XL_TX_LIST_SZ); 1711 ld->xl_tx_list[0].xl_status = htole32(XL_TXSTAT_EMPTY); 1712 1713 cd->xl_tx_prod = 1; 1714 cd->xl_tx_cons = 1; 1715 cd->xl_tx_cnt = 0; 1716 1717 bus_dmamap_sync(ld->xl_tx_tag, ld->xl_tx_dmamap, BUS_DMASYNC_PREWRITE); 1718 return (0); 1719} 1720 1721/* 1722 * Initialize the RX descriptors and allocate mbufs for them. Note that 1723 * we arrange the descriptors in a closed ring, so that the last descriptor 1724 * points back to the first. 1725 */ 1726static int 1727xl_list_rx_init(struct xl_softc *sc) 1728{ 1729 struct xl_chain_data *cd; 1730 struct xl_list_data *ld; 1731 int error, i, next; 1732 u_int32_t nextptr; 1733 1734 XL_LOCK_ASSERT(sc); 1735 1736 cd = &sc->xl_cdata; 1737 ld = &sc->xl_ldata; 1738 1739 for (i = 0; i < XL_RX_LIST_CNT; i++) { 1740 cd->xl_rx_chain[i].xl_ptr = &ld->xl_rx_list[i]; 1741 error = bus_dmamap_create(sc->xl_mtag, 0, 1742 &cd->xl_rx_chain[i].xl_map); 1743 if (error) 1744 return (error); 1745 error = xl_newbuf(sc, &cd->xl_rx_chain[i]); 1746 if (error) 1747 return (error); 1748 if (i == (XL_RX_LIST_CNT - 1)) 1749 next = 0; 1750 else 1751 next = i + 1; 1752 nextptr = ld->xl_rx_dmaaddr + 1753 next * sizeof(struct xl_list_onefrag); 1754 cd->xl_rx_chain[i].xl_next = &cd->xl_rx_chain[next]; 1755 ld->xl_rx_list[i].xl_next = htole32(nextptr); 1756 } 1757 1758 bus_dmamap_sync(ld->xl_rx_tag, ld->xl_rx_dmamap, BUS_DMASYNC_PREWRITE); 1759 cd->xl_rx_head = &cd->xl_rx_chain[0]; 1760 1761 return (0); 1762} 1763 1764/* 1765 * Initialize an RX descriptor and attach an MBUF cluster. 1766 * If we fail to do so, we need to leave the old mbuf and 1767 * the old DMA map untouched so that it can be reused. 1768 */ 1769static int 1770xl_newbuf(struct xl_softc *sc, struct xl_chain_onefrag *c) 1771{ 1772 struct mbuf *m_new = NULL; 1773 bus_dmamap_t map; 1774 bus_dma_segment_t segs[1]; 1775 int error, nseg; 1776 1777 XL_LOCK_ASSERT(sc); 1778 1779 m_new = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 1780 if (m_new == NULL) 1781 return (ENOBUFS); 1782 1783 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1784 1785 /* Force longword alignment for packet payload. */ 1786 m_adj(m_new, ETHER_ALIGN); 1787 1788 error = bus_dmamap_load_mbuf_sg(sc->xl_mtag, sc->xl_tmpmap, m_new, 1789 segs, &nseg, BUS_DMA_NOWAIT); 1790 if (error) { 1791 m_freem(m_new); 1792 device_printf(sc->xl_dev, "can't map mbuf (error %d)\n", 1793 error); 1794 return (error); 1795 } 1796 KASSERT(nseg == 1, 1797 ("%s: too many DMA segments (%d)", __func__, nseg)); 1798 1799 bus_dmamap_unload(sc->xl_mtag, c->xl_map); 1800 map = c->xl_map; 1801 c->xl_map = sc->xl_tmpmap; 1802 sc->xl_tmpmap = map; 1803 c->xl_mbuf = m_new; 1804 c->xl_ptr->xl_frag.xl_len = htole32(m_new->m_len | XL_LAST_FRAG); 1805 c->xl_ptr->xl_frag.xl_addr = htole32(segs->ds_addr); 1806 c->xl_ptr->xl_status = 0; 1807 bus_dmamap_sync(sc->xl_mtag, c->xl_map, BUS_DMASYNC_PREREAD); 1808 return (0); 1809} 1810 1811static int 1812xl_rx_resync(struct xl_softc *sc) 1813{ 1814 struct xl_chain_onefrag *pos; 1815 int i; 1816 1817 XL_LOCK_ASSERT(sc); 1818 1819 pos = sc->xl_cdata.xl_rx_head; 1820 1821 for (i = 0; i < XL_RX_LIST_CNT; i++) { 1822 if (pos->xl_ptr->xl_status) 1823 break; 1824 pos = pos->xl_next; 1825 } 1826 1827 if (i == XL_RX_LIST_CNT) 1828 return (0); 1829 1830 sc->xl_cdata.xl_rx_head = pos; 1831 1832 return (EAGAIN); 1833} 1834 1835/* 1836 * A frame has been uploaded: pass the resulting mbuf chain up to 1837 * the higher level protocols. 1838 */ 1839static int 1840xl_rxeof(struct xl_softc *sc) 1841{ 1842 struct mbuf *m; 1843 struct ifnet *ifp = sc->xl_ifp; 1844 struct xl_chain_onefrag *cur_rx; 1845 int total_len; 1846 int rx_npkts = 0; 1847 u_int32_t rxstat; 1848 1849 XL_LOCK_ASSERT(sc); 1850again: 1851 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag, sc->xl_ldata.xl_rx_dmamap, 1852 BUS_DMASYNC_POSTREAD); 1853 while ((rxstat = le32toh(sc->xl_cdata.xl_rx_head->xl_ptr->xl_status))) { 1854#ifdef DEVICE_POLLING 1855 if (ifp->if_capenable & IFCAP_POLLING) { 1856 if (sc->rxcycles <= 0) 1857 break; 1858 sc->rxcycles--; 1859 } 1860#endif 1861 cur_rx = sc->xl_cdata.xl_rx_head; 1862 sc->xl_cdata.xl_rx_head = cur_rx->xl_next; 1863 total_len = rxstat & XL_RXSTAT_LENMASK; 1864 rx_npkts++; 1865 1866 /* 1867 * Since we have told the chip to allow large frames, 1868 * we need to trap giant frame errors in software. We allow 1869 * a little more than the normal frame size to account for 1870 * frames with VLAN tags. 1871 */ 1872 if (total_len > XL_MAX_FRAMELEN) 1873 rxstat |= (XL_RXSTAT_UP_ERROR|XL_RXSTAT_OVERSIZE); 1874 1875 /* 1876 * If an error occurs, update stats, clear the 1877 * status word and leave the mbuf cluster in place: 1878 * it should simply get re-used next time this descriptor 1879 * comes up in the ring. 1880 */ 1881 if (rxstat & XL_RXSTAT_UP_ERROR) { 1882 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 1883 cur_rx->xl_ptr->xl_status = 0; 1884 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag, 1885 sc->xl_ldata.xl_rx_dmamap, BUS_DMASYNC_PREWRITE); 1886 continue; 1887 } 1888 1889 /* 1890 * If the error bit was not set, the upload complete 1891 * bit should be set which means we have a valid packet. 1892 * If not, something truly strange has happened. 1893 */ 1894 if (!(rxstat & XL_RXSTAT_UP_CMPLT)) { 1895 device_printf(sc->xl_dev, 1896 "bad receive status -- packet dropped\n"); 1897 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 1898 cur_rx->xl_ptr->xl_status = 0; 1899 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag, 1900 sc->xl_ldata.xl_rx_dmamap, BUS_DMASYNC_PREWRITE); 1901 continue; 1902 } 1903 1904 /* No errors; receive the packet. */ 1905 bus_dmamap_sync(sc->xl_mtag, cur_rx->xl_map, 1906 BUS_DMASYNC_POSTREAD); 1907 m = cur_rx->xl_mbuf; 1908 1909 /* 1910 * Try to conjure up a new mbuf cluster. If that 1911 * fails, it means we have an out of memory condition and 1912 * should leave the buffer in place and continue. This will 1913 * result in a lost packet, but there's little else we 1914 * can do in this situation. 1915 */ 1916 if (xl_newbuf(sc, cur_rx)) { 1917 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 1918 cur_rx->xl_ptr->xl_status = 0; 1919 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag, 1920 sc->xl_ldata.xl_rx_dmamap, BUS_DMASYNC_PREWRITE); 1921 continue; 1922 } 1923 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag, 1924 sc->xl_ldata.xl_rx_dmamap, BUS_DMASYNC_PREWRITE); 1925 1926 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1); 1927 m->m_pkthdr.rcvif = ifp; 1928 m->m_pkthdr.len = m->m_len = total_len; 1929 1930 if (ifp->if_capenable & IFCAP_RXCSUM) { 1931 /* Do IP checksum checking. */ 1932 if (rxstat & XL_RXSTAT_IPCKOK) 1933 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 1934 if (!(rxstat & XL_RXSTAT_IPCKERR)) 1935 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 1936 if ((rxstat & XL_RXSTAT_TCPCOK && 1937 !(rxstat & XL_RXSTAT_TCPCKERR)) || 1938 (rxstat & XL_RXSTAT_UDPCKOK && 1939 !(rxstat & XL_RXSTAT_UDPCKERR))) { 1940 m->m_pkthdr.csum_flags |= 1941 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 1942 m->m_pkthdr.csum_data = 0xffff; 1943 } 1944 } 1945 1946 XL_UNLOCK(sc); 1947 (*ifp->if_input)(ifp, m); 1948 XL_LOCK(sc); 1949 1950 /* 1951 * If we are running from the taskqueue, the interface 1952 * might have been stopped while we were passing the last 1953 * packet up the network stack. 1954 */ 1955 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) 1956 return (rx_npkts); 1957 } 1958 1959 /* 1960 * Handle the 'end of channel' condition. When the upload 1961 * engine hits the end of the RX ring, it will stall. This 1962 * is our cue to flush the RX ring, reload the uplist pointer 1963 * register and unstall the engine. 1964 * XXX This is actually a little goofy. With the ThunderLAN 1965 * chip, you get an interrupt when the receiver hits the end 1966 * of the receive ring, which tells you exactly when you 1967 * you need to reload the ring pointer. Here we have to 1968 * fake it. I'm mad at myself for not being clever enough 1969 * to avoid the use of a goto here. 1970 */ 1971 if (CSR_READ_4(sc, XL_UPLIST_PTR) == 0 || 1972 CSR_READ_4(sc, XL_UPLIST_STATUS) & XL_PKTSTAT_UP_STALLED) { 1973 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_STALL); 1974 xl_wait(sc); 1975 CSR_WRITE_4(sc, XL_UPLIST_PTR, sc->xl_ldata.xl_rx_dmaaddr); 1976 sc->xl_cdata.xl_rx_head = &sc->xl_cdata.xl_rx_chain[0]; 1977 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_UNSTALL); 1978 goto again; 1979 } 1980 return (rx_npkts); 1981} 1982 1983/* 1984 * Taskqueue wrapper for xl_rxeof(). 1985 */ 1986static void 1987xl_rxeof_task(void *arg, int pending) 1988{ 1989 struct xl_softc *sc = (struct xl_softc *)arg; 1990 1991 XL_LOCK(sc); 1992 if (sc->xl_ifp->if_drv_flags & IFF_DRV_RUNNING) 1993 xl_rxeof(sc); 1994 XL_UNLOCK(sc); 1995} 1996 1997/* 1998 * A frame was downloaded to the chip. It's safe for us to clean up 1999 * the list buffers. 2000 */ 2001static void 2002xl_txeof(struct xl_softc *sc) 2003{ 2004 struct xl_chain *cur_tx; 2005 struct ifnet *ifp = sc->xl_ifp; 2006 2007 XL_LOCK_ASSERT(sc); 2008 2009 /* 2010 * Go through our tx list and free mbufs for those 2011 * frames that have been uploaded. Note: the 3c905B 2012 * sets a special bit in the status word to let us 2013 * know that a frame has been downloaded, but the 2014 * original 3c900/3c905 adapters don't do that. 2015 * Consequently, we have to use a different test if 2016 * xl_type != XL_TYPE_905B. 2017 */ 2018 while (sc->xl_cdata.xl_tx_head != NULL) { 2019 cur_tx = sc->xl_cdata.xl_tx_head; 2020 2021 if (CSR_READ_4(sc, XL_DOWNLIST_PTR)) 2022 break; 2023 2024 sc->xl_cdata.xl_tx_head = cur_tx->xl_next; 2025 bus_dmamap_sync(sc->xl_mtag, cur_tx->xl_map, 2026 BUS_DMASYNC_POSTWRITE); 2027 bus_dmamap_unload(sc->xl_mtag, cur_tx->xl_map); 2028 m_freem(cur_tx->xl_mbuf); 2029 cur_tx->xl_mbuf = NULL; 2030 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1); 2031 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2032 2033 cur_tx->xl_next = sc->xl_cdata.xl_tx_free; 2034 sc->xl_cdata.xl_tx_free = cur_tx; 2035 } 2036 2037 if (sc->xl_cdata.xl_tx_head == NULL) { 2038 sc->xl_wdog_timer = 0; 2039 sc->xl_cdata.xl_tx_tail = NULL; 2040 } else { 2041 if (CSR_READ_4(sc, XL_DMACTL) & XL_DMACTL_DOWN_STALLED || 2042 !CSR_READ_4(sc, XL_DOWNLIST_PTR)) { 2043 CSR_WRITE_4(sc, XL_DOWNLIST_PTR, 2044 sc->xl_cdata.xl_tx_head->xl_phys); 2045 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL); 2046 } 2047 } 2048} 2049 2050static void 2051xl_txeof_90xB(struct xl_softc *sc) 2052{ 2053 struct xl_chain *cur_tx = NULL; 2054 struct ifnet *ifp = sc->xl_ifp; 2055 int idx; 2056 2057 XL_LOCK_ASSERT(sc); 2058 2059 bus_dmamap_sync(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_dmamap, 2060 BUS_DMASYNC_POSTREAD); 2061 idx = sc->xl_cdata.xl_tx_cons; 2062 while (idx != sc->xl_cdata.xl_tx_prod) { 2063 cur_tx = &sc->xl_cdata.xl_tx_chain[idx]; 2064 2065 if (!(le32toh(cur_tx->xl_ptr->xl_status) & 2066 XL_TXSTAT_DL_COMPLETE)) 2067 break; 2068 2069 if (cur_tx->xl_mbuf != NULL) { 2070 bus_dmamap_sync(sc->xl_mtag, cur_tx->xl_map, 2071 BUS_DMASYNC_POSTWRITE); 2072 bus_dmamap_unload(sc->xl_mtag, cur_tx->xl_map); 2073 m_freem(cur_tx->xl_mbuf); 2074 cur_tx->xl_mbuf = NULL; 2075 } 2076 2077 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1); 2078 2079 sc->xl_cdata.xl_tx_cnt--; 2080 XL_INC(idx, XL_TX_LIST_CNT); 2081 } 2082 2083 if (sc->xl_cdata.xl_tx_cnt == 0) 2084 sc->xl_wdog_timer = 0; 2085 sc->xl_cdata.xl_tx_cons = idx; 2086 2087 if (cur_tx != NULL) 2088 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2089} 2090 2091/* 2092 * TX 'end of channel' interrupt handler. Actually, we should 2093 * only get a 'TX complete' interrupt if there's a transmit error, 2094 * so this is really TX error handler. 2095 */ 2096static void 2097xl_txeoc(struct xl_softc *sc) 2098{ 2099 u_int8_t txstat; 2100 2101 XL_LOCK_ASSERT(sc); 2102 2103 while ((txstat = CSR_READ_1(sc, XL_TX_STATUS))) { 2104 if (txstat & XL_TXSTATUS_UNDERRUN || 2105 txstat & XL_TXSTATUS_JABBER || 2106 txstat & XL_TXSTATUS_RECLAIM) { 2107 device_printf(sc->xl_dev, 2108 "transmission error: 0x%02x\n", txstat); 2109 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET); 2110 xl_wait(sc); 2111 if (sc->xl_type == XL_TYPE_905B) { 2112 if (sc->xl_cdata.xl_tx_cnt) { 2113 int i; 2114 struct xl_chain *c; 2115 2116 i = sc->xl_cdata.xl_tx_cons; 2117 c = &sc->xl_cdata.xl_tx_chain[i]; 2118 CSR_WRITE_4(sc, XL_DOWNLIST_PTR, 2119 c->xl_phys); 2120 CSR_WRITE_1(sc, XL_DOWN_POLL, 64); 2121 sc->xl_wdog_timer = 5; 2122 } 2123 } else { 2124 if (sc->xl_cdata.xl_tx_head != NULL) { 2125 CSR_WRITE_4(sc, XL_DOWNLIST_PTR, 2126 sc->xl_cdata.xl_tx_head->xl_phys); 2127 sc->xl_wdog_timer = 5; 2128 } 2129 } 2130 /* 2131 * Remember to set this for the 2132 * first generation 3c90X chips. 2133 */ 2134 CSR_WRITE_1(sc, XL_TX_FREETHRESH, XL_PACKET_SIZE >> 8); 2135 if (txstat & XL_TXSTATUS_UNDERRUN && 2136 sc->xl_tx_thresh < XL_PACKET_SIZE) { 2137 sc->xl_tx_thresh += XL_MIN_FRAMELEN; 2138 device_printf(sc->xl_dev, 2139"tx underrun, increasing tx start threshold to %d bytes\n", sc->xl_tx_thresh); 2140 } 2141 CSR_WRITE_2(sc, XL_COMMAND, 2142 XL_CMD_TX_SET_START|sc->xl_tx_thresh); 2143 if (sc->xl_type == XL_TYPE_905B) { 2144 CSR_WRITE_2(sc, XL_COMMAND, 2145 XL_CMD_SET_TX_RECLAIM|(XL_PACKET_SIZE >> 4)); 2146 } 2147 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_ENABLE); 2148 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL); 2149 } else { 2150 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_ENABLE); 2151 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL); 2152 } 2153 /* 2154 * Write an arbitrary byte to the TX_STATUS register 2155 * to clear this interrupt/error and advance to the next. 2156 */ 2157 CSR_WRITE_1(sc, XL_TX_STATUS, 0x01); 2158 } 2159} 2160 2161static void 2162xl_intr(void *arg) 2163{ 2164 struct xl_softc *sc = arg; 2165 struct ifnet *ifp = sc->xl_ifp; 2166 u_int16_t status; 2167 2168 XL_LOCK(sc); 2169 2170#ifdef DEVICE_POLLING 2171 if (ifp->if_capenable & IFCAP_POLLING) { 2172 XL_UNLOCK(sc); 2173 return; 2174 } 2175#endif 2176 2177 2178#ifndef __HAIKU__ 2179 for (;;) { 2180 status = CSR_READ_2(sc, XL_STATUS); 2181 if ((status & XL_INTRS) == 0 || status == 0xFFFF) 2182 break; 2183 CSR_WRITE_2(sc, XL_COMMAND, 2184 XL_CMD_INTR_ACK|(status & XL_INTRS)); 2185#else 2186 status = atomic_get((int32 *)&sc->xl_intr_status); 2187 for (;;) { 2188#endif 2189 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 2190 break; 2191 2192 if (status & XL_STAT_UP_COMPLETE) { 2193 if (xl_rxeof(sc) == 0) { 2194 while (xl_rx_resync(sc)) 2195 xl_rxeof(sc); 2196 } 2197 } 2198 2199 if (status & XL_STAT_DOWN_COMPLETE) { 2200 if (sc->xl_type == XL_TYPE_905B) 2201 xl_txeof_90xB(sc); 2202 else 2203 xl_txeof(sc); 2204 } 2205 2206 if (status & XL_STAT_TX_COMPLETE) { 2207 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 2208 xl_txeoc(sc); 2209 } 2210 2211 if (status & XL_STAT_ADFAIL) { 2212 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2213 xl_init_locked(sc); 2214 break; 2215 } 2216 2217 if (status & XL_STAT_STATSOFLOW) 2218 xl_stats_update(sc); 2219#ifdef __HAIKU__ 2220 status = CSR_READ_2(sc, XL_STATUS); 2221 if ((status & XL_INTRS) == 0 || status == 0xFFFF) 2222 break; 2223 CSR_WRITE_2(sc, XL_COMMAND, 2224 XL_CMD_INTR_ACK|(status & XL_INTRS)); 2225#endif 2226 } 2227 2228 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd) && 2229 ifp->if_drv_flags & IFF_DRV_RUNNING) { 2230 if (sc->xl_type == XL_TYPE_905B) 2231 xl_start_90xB_locked(ifp); 2232 else 2233 xl_start_locked(ifp); 2234 } 2235 2236 XL_UNLOCK(sc); 2237} 2238 2239#ifdef DEVICE_POLLING 2240static int 2241xl_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 2242{ 2243 struct xl_softc *sc = ifp->if_softc; 2244 int rx_npkts = 0; 2245 2246 XL_LOCK(sc); 2247 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 2248 rx_npkts = xl_poll_locked(ifp, cmd, count); 2249 XL_UNLOCK(sc); 2250 return (rx_npkts); 2251} 2252 2253static int 2254xl_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count) 2255{ 2256 struct xl_softc *sc = ifp->if_softc; 2257 int rx_npkts; 2258 2259 XL_LOCK_ASSERT(sc); 2260 2261 sc->rxcycles = count; 2262 rx_npkts = xl_rxeof(sc); 2263 if (sc->xl_type == XL_TYPE_905B) 2264 xl_txeof_90xB(sc); 2265 else 2266 xl_txeof(sc); 2267 2268 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) { 2269 if (sc->xl_type == XL_TYPE_905B) 2270 xl_start_90xB_locked(ifp); 2271 else 2272 xl_start_locked(ifp); 2273 } 2274 2275 if (cmd == POLL_AND_CHECK_STATUS) { 2276 u_int16_t status; 2277 2278 status = CSR_READ_2(sc, XL_STATUS); 2279 if (status & XL_INTRS && status != 0xFFFF) { 2280 CSR_WRITE_2(sc, XL_COMMAND, 2281 XL_CMD_INTR_ACK|(status & XL_INTRS)); 2282 2283 if (status & XL_STAT_TX_COMPLETE) { 2284 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 2285 xl_txeoc(sc); 2286 } 2287 2288 if (status & XL_STAT_ADFAIL) { 2289 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2290 xl_init_locked(sc); 2291 } 2292 2293 if (status & XL_STAT_STATSOFLOW) 2294 xl_stats_update(sc); 2295 } 2296 } 2297 return (rx_npkts); 2298} 2299#endif /* DEVICE_POLLING */ 2300 2301static void 2302xl_tick(void *xsc) 2303{ 2304 struct xl_softc *sc = xsc; 2305 struct mii_data *mii; 2306 2307 XL_LOCK_ASSERT(sc); 2308 2309 if (sc->xl_miibus != NULL) { 2310 mii = device_get_softc(sc->xl_miibus); 2311 mii_tick(mii); 2312 } 2313 2314 xl_stats_update(sc); 2315 if (xl_watchdog(sc) == EJUSTRETURN) 2316 return; 2317 2318 callout_reset(&sc->xl_tick_callout, hz, xl_tick, sc); 2319} 2320 2321static void 2322xl_stats_update(struct xl_softc *sc) 2323{ 2324 struct ifnet *ifp = sc->xl_ifp; 2325 struct xl_stats xl_stats; 2326 u_int8_t *p; 2327 int i; 2328 2329 XL_LOCK_ASSERT(sc); 2330 2331 bzero((char *)&xl_stats, sizeof(struct xl_stats)); 2332 2333 p = (u_int8_t *)&xl_stats; 2334 2335 /* Read all the stats registers. */ 2336 XL_SEL_WIN(6); 2337 2338 for (i = 0; i < 16; i++) 2339 *p++ = CSR_READ_1(sc, XL_W6_CARRIER_LOST + i); 2340 2341 if_inc_counter(ifp, IFCOUNTER_IERRORS, xl_stats.xl_rx_overrun); 2342 2343 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, 2344 xl_stats.xl_tx_multi_collision + 2345 xl_stats.xl_tx_single_collision + 2346 xl_stats.xl_tx_late_collision); 2347 2348 /* 2349 * Boomerang and cyclone chips have an extra stats counter 2350 * in window 4 (BadSSD). We have to read this too in order 2351 * to clear out all the stats registers and avoid a statsoflow 2352 * interrupt. 2353 */ 2354 XL_SEL_WIN(4); 2355 CSR_READ_1(sc, XL_W4_BADSSD); 2356 XL_SEL_WIN(7); 2357} 2358 2359/* 2360 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 2361 * pointers to the fragment pointers. 2362 */ 2363static int 2364xl_encap(struct xl_softc *sc, struct xl_chain *c, struct mbuf **m_head) 2365{ 2366 struct mbuf *m_new; 2367 struct ifnet *ifp = sc->xl_ifp; 2368 int error, i, nseg, total_len; 2369 u_int32_t status; 2370 2371 XL_LOCK_ASSERT(sc); 2372 2373 error = bus_dmamap_load_mbuf_sg(sc->xl_mtag, c->xl_map, *m_head, 2374 sc->xl_cdata.xl_tx_segs, &nseg, BUS_DMA_NOWAIT); 2375 2376 if (error && error != EFBIG) { 2377 if_printf(ifp, "can't map mbuf (error %d)\n", error); 2378 return (error); 2379 } 2380 2381 /* 2382 * Handle special case: we used up all 63 fragments, 2383 * but we have more mbufs left in the chain. Copy the 2384 * data into an mbuf cluster. Note that we don't 2385 * bother clearing the values in the other fragment 2386 * pointers/counters; it wouldn't gain us anything, 2387 * and would waste cycles. 2388 */ 2389 if (error) { 2390 m_new = m_collapse(*m_head, M_NOWAIT, XL_MAXFRAGS); 2391 if (m_new == NULL) { 2392 m_freem(*m_head); 2393 *m_head = NULL; 2394 return (ENOBUFS); 2395 } 2396 *m_head = m_new; 2397 2398 error = bus_dmamap_load_mbuf_sg(sc->xl_mtag, c->xl_map, 2399 *m_head, sc->xl_cdata.xl_tx_segs, &nseg, BUS_DMA_NOWAIT); 2400 if (error) { 2401 m_freem(*m_head); 2402 *m_head = NULL; 2403 if_printf(ifp, "can't map mbuf (error %d)\n", error); 2404 return (error); 2405 } 2406 } 2407 2408 KASSERT(nseg <= XL_MAXFRAGS, 2409 ("%s: too many DMA segments (%d)", __func__, nseg)); 2410 if (nseg == 0) { 2411 m_freem(*m_head); 2412 *m_head = NULL; 2413 return (EIO); 2414 } 2415 bus_dmamap_sync(sc->xl_mtag, c->xl_map, BUS_DMASYNC_PREWRITE); 2416 2417 total_len = 0; 2418 for (i = 0; i < nseg; i++) { 2419 KASSERT(sc->xl_cdata.xl_tx_segs[i].ds_len <= MCLBYTES, 2420 ("segment size too large")); 2421 c->xl_ptr->xl_frag[i].xl_addr = 2422 htole32(sc->xl_cdata.xl_tx_segs[i].ds_addr); 2423 c->xl_ptr->xl_frag[i].xl_len = 2424 htole32(sc->xl_cdata.xl_tx_segs[i].ds_len); 2425 total_len += sc->xl_cdata.xl_tx_segs[i].ds_len; 2426 } 2427 c->xl_ptr->xl_frag[nseg - 1].xl_len |= htole32(XL_LAST_FRAG); 2428 2429 if (sc->xl_type == XL_TYPE_905B) { 2430 status = XL_TXSTAT_RND_DEFEAT; 2431 2432#ifndef XL905B_TXCSUM_BROKEN 2433 if ((*m_head)->m_pkthdr.csum_flags) { 2434 if ((*m_head)->m_pkthdr.csum_flags & CSUM_IP) 2435 status |= XL_TXSTAT_IPCKSUM; 2436 if ((*m_head)->m_pkthdr.csum_flags & CSUM_TCP) 2437 status |= XL_TXSTAT_TCPCKSUM; 2438 if ((*m_head)->m_pkthdr.csum_flags & CSUM_UDP) 2439 status |= XL_TXSTAT_UDPCKSUM; 2440 } 2441#endif 2442 } else 2443 status = total_len; 2444 c->xl_ptr->xl_status = htole32(status); 2445 c->xl_ptr->xl_next = 0; 2446 2447 c->xl_mbuf = *m_head; 2448 return (0); 2449} 2450 2451/* 2452 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 2453 * to the mbuf data regions directly in the transmit lists. We also save a 2454 * copy of the pointers since the transmit list fragment pointers are 2455 * physical addresses. 2456 */ 2457 2458static void 2459xl_start(struct ifnet *ifp) 2460{ 2461 struct xl_softc *sc = ifp->if_softc; 2462 2463 XL_LOCK(sc); 2464 2465 if (sc->xl_type == XL_TYPE_905B) 2466 xl_start_90xB_locked(ifp); 2467 else 2468 xl_start_locked(ifp); 2469 2470 XL_UNLOCK(sc); 2471} 2472 2473static void 2474xl_start_locked(struct ifnet *ifp) 2475{ 2476 struct xl_softc *sc = ifp->if_softc; 2477 struct mbuf *m_head; 2478 struct xl_chain *prev = NULL, *cur_tx = NULL, *start_tx; 2479 struct xl_chain *prev_tx; 2480 int error; 2481 2482 XL_LOCK_ASSERT(sc); 2483 2484 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 2485 IFF_DRV_RUNNING) 2486 return; 2487 /* 2488 * Check for an available queue slot. If there are none, 2489 * punt. 2490 */ 2491 if (sc->xl_cdata.xl_tx_free == NULL) { 2492 xl_txeoc(sc); 2493 xl_txeof(sc); 2494 if (sc->xl_cdata.xl_tx_free == NULL) { 2495 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 2496 return; 2497 } 2498 } 2499 2500 start_tx = sc->xl_cdata.xl_tx_free; 2501 2502 for (; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) && 2503 sc->xl_cdata.xl_tx_free != NULL;) { 2504 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 2505 if (m_head == NULL) 2506 break; 2507 2508 /* Pick a descriptor off the free list. */ 2509 prev_tx = cur_tx; 2510 cur_tx = sc->xl_cdata.xl_tx_free; 2511 2512 /* Pack the data into the descriptor. */ 2513 error = xl_encap(sc, cur_tx, &m_head); 2514 if (error) { 2515 cur_tx = prev_tx; 2516 if (m_head == NULL) 2517 break; 2518 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 2519 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 2520 break; 2521 } 2522 2523 sc->xl_cdata.xl_tx_free = cur_tx->xl_next; 2524 cur_tx->xl_next = NULL; 2525 2526 /* Chain it together. */ 2527 if (prev != NULL) { 2528 prev->xl_next = cur_tx; 2529 prev->xl_ptr->xl_next = htole32(cur_tx->xl_phys); 2530 } 2531 prev = cur_tx; 2532 2533 /* 2534 * If there's a BPF listener, bounce a copy of this frame 2535 * to him. 2536 */ 2537 BPF_MTAP(ifp, cur_tx->xl_mbuf); 2538 } 2539 2540 /* 2541 * If there are no packets queued, bail. 2542 */ 2543 if (cur_tx == NULL) 2544 return; 2545 2546 /* 2547 * Place the request for the upload interrupt 2548 * in the last descriptor in the chain. This way, if 2549 * we're chaining several packets at once, we'll only 2550 * get an interrupt once for the whole chain rather than 2551 * once for each packet. 2552 */ 2553 cur_tx->xl_ptr->xl_status |= htole32(XL_TXSTAT_DL_INTR); 2554 2555 /* 2556 * Queue the packets. If the TX channel is clear, update 2557 * the downlist pointer register. 2558 */ 2559 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_STALL); 2560 xl_wait(sc); 2561 2562 if (sc->xl_cdata.xl_tx_head != NULL) { 2563 sc->xl_cdata.xl_tx_tail->xl_next = start_tx; 2564 sc->xl_cdata.xl_tx_tail->xl_ptr->xl_next = 2565 htole32(start_tx->xl_phys); 2566 sc->xl_cdata.xl_tx_tail->xl_ptr->xl_status &= 2567 htole32(~XL_TXSTAT_DL_INTR); 2568 sc->xl_cdata.xl_tx_tail = cur_tx; 2569 } else { 2570 sc->xl_cdata.xl_tx_head = start_tx; 2571 sc->xl_cdata.xl_tx_tail = cur_tx; 2572 } 2573 bus_dmamap_sync(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_dmamap, 2574 BUS_DMASYNC_PREWRITE); 2575 if (!CSR_READ_4(sc, XL_DOWNLIST_PTR)) 2576 CSR_WRITE_4(sc, XL_DOWNLIST_PTR, start_tx->xl_phys); 2577 2578 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL); 2579 2580 XL_SEL_WIN(7); 2581 2582 /* 2583 * Set a timeout in case the chip goes out to lunch. 2584 */ 2585 sc->xl_wdog_timer = 5; 2586 2587 /* 2588 * XXX Under certain conditions, usually on slower machines 2589 * where interrupts may be dropped, it's possible for the 2590 * adapter to chew up all the buffers in the receive ring 2591 * and stall, without us being able to do anything about it. 2592 * To guard against this, we need to make a pass over the 2593 * RX queue to make sure there aren't any packets pending. 2594 * Doing it here means we can flush the receive ring at the 2595 * same time the chip is DMAing the transmit descriptors we 2596 * just gave it. 2597 * 2598 * 3Com goes to some lengths to emphasize the Parallel Tasking (tm) 2599 * nature of their chips in all their marketing literature; 2600 * we may as well take advantage of it. :) 2601 */ 2602 taskqueue_enqueue(taskqueue_swi, &sc->xl_task); 2603} 2604 2605static void 2606xl_start_90xB_locked(struct ifnet *ifp) 2607{ 2608 struct xl_softc *sc = ifp->if_softc; 2609 struct mbuf *m_head; 2610 struct xl_chain *prev = NULL, *cur_tx = NULL, *start_tx; 2611 struct xl_chain *prev_tx; 2612 int error, idx; 2613 2614 XL_LOCK_ASSERT(sc); 2615 2616 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 2617 IFF_DRV_RUNNING) 2618 return; 2619 2620 idx = sc->xl_cdata.xl_tx_prod; 2621 start_tx = &sc->xl_cdata.xl_tx_chain[idx]; 2622 2623 for (; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) && 2624 sc->xl_cdata.xl_tx_chain[idx].xl_mbuf == NULL;) { 2625 if ((XL_TX_LIST_CNT - sc->xl_cdata.xl_tx_cnt) < 3) { 2626 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 2627 break; 2628 } 2629 2630 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 2631 if (m_head == NULL) 2632 break; 2633 2634 prev_tx = cur_tx; 2635 cur_tx = &sc->xl_cdata.xl_tx_chain[idx]; 2636 2637 /* Pack the data into the descriptor. */ 2638 error = xl_encap(sc, cur_tx, &m_head); 2639 if (error) { 2640 cur_tx = prev_tx; 2641 if (m_head == NULL) 2642 break; 2643 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 2644 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 2645 break; 2646 } 2647 2648 /* Chain it together. */ 2649 if (prev != NULL) 2650 prev->xl_ptr->xl_next = htole32(cur_tx->xl_phys); 2651 prev = cur_tx; 2652 2653 /* 2654 * If there's a BPF listener, bounce a copy of this frame 2655 * to him. 2656 */ 2657 BPF_MTAP(ifp, cur_tx->xl_mbuf); 2658 2659 XL_INC(idx, XL_TX_LIST_CNT); 2660 sc->xl_cdata.xl_tx_cnt++; 2661 } 2662 2663 /* 2664 * If there are no packets queued, bail. 2665 */ 2666 if (cur_tx == NULL) 2667 return; 2668 2669 /* 2670 * Place the request for the upload interrupt 2671 * in the last descriptor in the chain. This way, if 2672 * we're chaining several packets at once, we'll only 2673 * get an interrupt once for the whole chain rather than 2674 * once for each packet. 2675 */ 2676 cur_tx->xl_ptr->xl_status |= htole32(XL_TXSTAT_DL_INTR); 2677 2678 /* Start transmission */ 2679 sc->xl_cdata.xl_tx_prod = idx; 2680 start_tx->xl_prev->xl_ptr->xl_next = htole32(start_tx->xl_phys); 2681 bus_dmamap_sync(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_dmamap, 2682 BUS_DMASYNC_PREWRITE); 2683 2684 /* 2685 * Set a timeout in case the chip goes out to lunch. 2686 */ 2687 sc->xl_wdog_timer = 5; 2688} 2689 2690static void 2691xl_init(void *xsc) 2692{ 2693 struct xl_softc *sc = xsc; 2694 2695 XL_LOCK(sc); 2696 xl_init_locked(sc); 2697 XL_UNLOCK(sc); 2698} 2699 2700static void 2701xl_init_locked(struct xl_softc *sc) 2702{ 2703 struct ifnet *ifp = sc->xl_ifp; 2704 int error, i; 2705 struct mii_data *mii = NULL; 2706 2707 XL_LOCK_ASSERT(sc); 2708 2709 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 2710 return; 2711 /* 2712 * Cancel pending I/O and free all RX/TX buffers. 2713 */ 2714 xl_stop(sc); 2715 2716 /* Reset the chip to a known state. */ 2717 xl_reset(sc); 2718 2719 if (sc->xl_miibus == NULL) { 2720 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET); 2721 xl_wait(sc); 2722 } 2723 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET); 2724 xl_wait(sc); 2725 DELAY(10000); 2726 2727 if (sc->xl_miibus != NULL) 2728 mii = device_get_softc(sc->xl_miibus); 2729 2730 /* 2731 * Clear WOL status and disable all WOL feature as WOL 2732 * would interfere Rx operation under normal environments. 2733 */ 2734 if ((sc->xl_flags & XL_FLAG_WOL) != 0) { 2735 XL_SEL_WIN(7); 2736 CSR_READ_2(sc, XL_W7_BM_PME); 2737 CSR_WRITE_2(sc, XL_W7_BM_PME, 0); 2738 } 2739 /* Init our MAC address */ 2740 XL_SEL_WIN(2); 2741 for (i = 0; i < ETHER_ADDR_LEN; i++) { 2742 CSR_WRITE_1(sc, XL_W2_STATION_ADDR_LO + i, 2743 IF_LLADDR(sc->xl_ifp)[i]); 2744 } 2745 2746 /* Clear the station mask. */ 2747 for (i = 0; i < 3; i++) 2748 CSR_WRITE_2(sc, XL_W2_STATION_MASK_LO + (i * 2), 0); 2749#ifdef notdef 2750 /* Reset TX and RX. */ 2751 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET); 2752 xl_wait(sc); 2753 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET); 2754 xl_wait(sc); 2755#endif 2756 /* Init circular RX list. */ 2757 error = xl_list_rx_init(sc); 2758 if (error) { 2759 device_printf(sc->xl_dev, "initialization of the rx ring failed (%d)\n", 2760 error); 2761 xl_stop(sc); 2762 return; 2763 } 2764 2765 /* Init TX descriptors. */ 2766 if (sc->xl_type == XL_TYPE_905B) 2767 error = xl_list_tx_init_90xB(sc); 2768 else 2769 error = xl_list_tx_init(sc); 2770 if (error) { 2771 device_printf(sc->xl_dev, "initialization of the tx ring failed (%d)\n", 2772 error); 2773 xl_stop(sc); 2774 return; 2775 } 2776 2777 /* 2778 * Set the TX freethresh value. 2779 * Note that this has no effect on 3c905B "cyclone" 2780 * cards but is required for 3c900/3c905 "boomerang" 2781 * cards in order to enable the download engine. 2782 */ 2783 CSR_WRITE_1(sc, XL_TX_FREETHRESH, XL_PACKET_SIZE >> 8); 2784 2785 /* Set the TX start threshold for best performance. */ 2786 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_SET_START|sc->xl_tx_thresh); 2787 2788 /* 2789 * If this is a 3c905B, also set the tx reclaim threshold. 2790 * This helps cut down on the number of tx reclaim errors 2791 * that could happen on a busy network. The chip multiplies 2792 * the register value by 16 to obtain the actual threshold 2793 * in bytes, so we divide by 16 when setting the value here. 2794 * The existing threshold value can be examined by reading 2795 * the register at offset 9 in window 5. 2796 */ 2797 if (sc->xl_type == XL_TYPE_905B) { 2798 CSR_WRITE_2(sc, XL_COMMAND, 2799 XL_CMD_SET_TX_RECLAIM|(XL_PACKET_SIZE >> 4)); 2800 } 2801 2802 /* Set RX filter bits. */ 2803 xl_rxfilter(sc); 2804 2805 /* 2806 * Load the address of the RX list. We have to 2807 * stall the upload engine before we can manipulate 2808 * the uplist pointer register, then unstall it when 2809 * we're finished. We also have to wait for the 2810 * stall command to complete before proceeding. 2811 * Note that we have to do this after any RX resets 2812 * have completed since the uplist register is cleared 2813 * by a reset. 2814 */ 2815 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_STALL); 2816 xl_wait(sc); 2817 CSR_WRITE_4(sc, XL_UPLIST_PTR, sc->xl_ldata.xl_rx_dmaaddr); 2818 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_UNSTALL); 2819 xl_wait(sc); 2820 2821 if (sc->xl_type == XL_TYPE_905B) { 2822 /* Set polling interval */ 2823 CSR_WRITE_1(sc, XL_DOWN_POLL, 64); 2824 /* Load the address of the TX list */ 2825 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_STALL); 2826 xl_wait(sc); 2827 CSR_WRITE_4(sc, XL_DOWNLIST_PTR, 2828 sc->xl_cdata.xl_tx_chain[0].xl_phys); 2829 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL); 2830 xl_wait(sc); 2831 } 2832 2833 /* 2834 * If the coax transceiver is on, make sure to enable 2835 * the DC-DC converter. 2836 */ 2837 XL_SEL_WIN(3); 2838 if (sc->xl_xcvr == XL_XCVR_COAX) 2839 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_START); 2840 else 2841 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP); 2842 2843 /* 2844 * increase packet size to allow reception of 802.1q or ISL packets. 2845 * For the 3c90x chip, set the 'allow large packets' bit in the MAC 2846 * control register. For 3c90xB/C chips, use the RX packet size 2847 * register. 2848 */ 2849 2850 if (sc->xl_type == XL_TYPE_905B) 2851 CSR_WRITE_2(sc, XL_W3_MAXPKTSIZE, XL_PACKET_SIZE); 2852 else { 2853 u_int8_t macctl; 2854 macctl = CSR_READ_1(sc, XL_W3_MAC_CTRL); 2855 macctl |= XL_MACCTRL_ALLOW_LARGE_PACK; 2856 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, macctl); 2857 } 2858 2859 /* Clear out the stats counters. */ 2860 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STATS_DISABLE); 2861 xl_stats_update(sc); 2862 XL_SEL_WIN(4); 2863 CSR_WRITE_2(sc, XL_W4_NET_DIAG, XL_NETDIAG_UPPER_BYTES_ENABLE); 2864 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STATS_ENABLE); 2865 2866 /* 2867 * Enable interrupts. 2868 */ 2869 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ACK|0xFF); 2870 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STAT_ENB|XL_INTRS); 2871#ifdef DEVICE_POLLING 2872 /* Disable interrupts if we are polling. */ 2873 if (ifp->if_capenable & IFCAP_POLLING) 2874 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB|0); 2875 else 2876#endif 2877 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB|XL_INTRS); 2878 if (sc->xl_flags & XL_FLAG_FUNCREG) 2879 bus_space_write_4(sc->xl_ftag, sc->xl_fhandle, 4, 0x8000); 2880 2881 /* Set the RX early threshold */ 2882 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_THRESH|(XL_PACKET_SIZE >>2)); 2883 CSR_WRITE_4(sc, XL_DMACTL, XL_DMACTL_UP_RX_EARLY); 2884 2885 /* Enable receiver and transmitter. */ 2886 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_ENABLE); 2887 xl_wait(sc); 2888 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_ENABLE); 2889 xl_wait(sc); 2890 2891 /* XXX Downcall to miibus. */ 2892 if (mii != NULL) 2893 mii_mediachg(mii); 2894 2895 /* Select window 7 for normal operations. */ 2896 XL_SEL_WIN(7); 2897 2898 ifp->if_drv_flags |= IFF_DRV_RUNNING; 2899 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2900 2901 sc->xl_wdog_timer = 0; 2902 callout_reset(&sc->xl_tick_callout, hz, xl_tick, sc); 2903} 2904 2905/* 2906 * Set media options. 2907 */ 2908static int 2909xl_ifmedia_upd(struct ifnet *ifp) 2910{ 2911 struct xl_softc *sc = ifp->if_softc; 2912 struct ifmedia *ifm = NULL; 2913 struct mii_data *mii = NULL; 2914 2915 XL_LOCK(sc); 2916 2917 if (sc->xl_miibus != NULL) 2918 mii = device_get_softc(sc->xl_miibus); 2919 if (mii == NULL) 2920 ifm = &sc->ifmedia; 2921 else 2922 ifm = &mii->mii_media; 2923 2924 switch (IFM_SUBTYPE(ifm->ifm_media)) { 2925 case IFM_100_FX: 2926 case IFM_10_FL: 2927 case IFM_10_2: 2928 case IFM_10_5: 2929 xl_setmode(sc, ifm->ifm_media); 2930 XL_UNLOCK(sc); 2931 return (0); 2932 } 2933 2934 if (sc->xl_media & XL_MEDIAOPT_MII || 2935 sc->xl_media & XL_MEDIAOPT_BTX || 2936 sc->xl_media & XL_MEDIAOPT_BT4) { 2937 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2938 xl_init_locked(sc); 2939 } else { 2940 xl_setmode(sc, ifm->ifm_media); 2941 } 2942 2943 XL_UNLOCK(sc); 2944 2945 return (0); 2946} 2947 2948/* 2949 * Report current media status. 2950 */ 2951static void 2952xl_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 2953{ 2954 struct xl_softc *sc = ifp->if_softc; 2955 u_int32_t icfg; 2956 u_int16_t status = 0; 2957 struct mii_data *mii = NULL; 2958 2959 XL_LOCK(sc); 2960 2961 if (sc->xl_miibus != NULL) 2962 mii = device_get_softc(sc->xl_miibus); 2963 2964 XL_SEL_WIN(4); 2965 status = CSR_READ_2(sc, XL_W4_MEDIA_STATUS); 2966 2967 XL_SEL_WIN(3); 2968 icfg = CSR_READ_4(sc, XL_W3_INTERNAL_CFG) & XL_ICFG_CONNECTOR_MASK; 2969 icfg >>= XL_ICFG_CONNECTOR_BITS; 2970 2971 ifmr->ifm_active = IFM_ETHER; 2972 ifmr->ifm_status = IFM_AVALID; 2973 2974 if ((status & XL_MEDIASTAT_CARRIER) == 0) 2975 ifmr->ifm_status |= IFM_ACTIVE; 2976 2977 switch (icfg) { 2978 case XL_XCVR_10BT: 2979 ifmr->ifm_active = IFM_ETHER|IFM_10_T; 2980 if (CSR_READ_1(sc, XL_W3_MAC_CTRL) & XL_MACCTRL_DUPLEX) 2981 ifmr->ifm_active |= IFM_FDX; 2982 else 2983 ifmr->ifm_active |= IFM_HDX; 2984 break; 2985 case XL_XCVR_AUI: 2986 if (sc->xl_type == XL_TYPE_905B && 2987 sc->xl_media == XL_MEDIAOPT_10FL) { 2988 ifmr->ifm_active = IFM_ETHER|IFM_10_FL; 2989 if (CSR_READ_1(sc, XL_W3_MAC_CTRL) & XL_MACCTRL_DUPLEX) 2990 ifmr->ifm_active |= IFM_FDX; 2991 else 2992 ifmr->ifm_active |= IFM_HDX; 2993 } else 2994 ifmr->ifm_active = IFM_ETHER|IFM_10_5; 2995 break; 2996 case XL_XCVR_COAX: 2997 ifmr->ifm_active = IFM_ETHER|IFM_10_2; 2998 break; 2999 /* 3000 * XXX MII and BTX/AUTO should be separate cases. 3001 */ 3002 3003 case XL_XCVR_100BTX: 3004 case XL_XCVR_AUTO: 3005 case XL_XCVR_MII: 3006 if (mii != NULL) { 3007 mii_pollstat(mii); 3008 ifmr->ifm_active = mii->mii_media_active; 3009 ifmr->ifm_status = mii->mii_media_status; 3010 } 3011 break; 3012 case XL_XCVR_100BFX: 3013 ifmr->ifm_active = IFM_ETHER|IFM_100_FX; 3014 break; 3015 default: 3016 if_printf(ifp, "unknown XCVR type: %d\n", icfg); 3017 break; 3018 } 3019 3020 XL_UNLOCK(sc); 3021} 3022 3023static int 3024xl_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 3025{ 3026 struct xl_softc *sc = ifp->if_softc; 3027 struct ifreq *ifr = (struct ifreq *) data; 3028 int error = 0, mask; 3029 struct mii_data *mii = NULL; 3030 3031 switch (command) { 3032 case SIOCSIFFLAGS: 3033 XL_LOCK(sc); 3034 if (ifp->if_flags & IFF_UP) { 3035 if (ifp->if_drv_flags & IFF_DRV_RUNNING && 3036 (ifp->if_flags ^ sc->xl_if_flags) & 3037 (IFF_PROMISC | IFF_ALLMULTI)) 3038 xl_rxfilter(sc); 3039 else 3040 xl_init_locked(sc); 3041 } else { 3042 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 3043 xl_stop(sc); 3044 } 3045 sc->xl_if_flags = ifp->if_flags; 3046 XL_UNLOCK(sc); 3047 break; 3048 case SIOCADDMULTI: 3049 case SIOCDELMULTI: 3050 /* XXX Downcall from if_addmulti() possibly with locks held. */ 3051 XL_LOCK(sc); 3052 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 3053 xl_rxfilter(sc); 3054 XL_UNLOCK(sc); 3055 break; 3056 case SIOCGIFMEDIA: 3057 case SIOCSIFMEDIA: 3058 if (sc->xl_miibus != NULL) 3059 mii = device_get_softc(sc->xl_miibus); 3060 if (mii == NULL) 3061 error = ifmedia_ioctl(ifp, ifr, 3062 &sc->ifmedia, command); 3063 else 3064 error = ifmedia_ioctl(ifp, ifr, 3065 &mii->mii_media, command); 3066 break; 3067 case SIOCSIFCAP: 3068 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 3069#ifdef DEVICE_POLLING 3070 if ((mask & IFCAP_POLLING) != 0 && 3071 (ifp->if_capabilities & IFCAP_POLLING) != 0) { 3072 ifp->if_capenable ^= IFCAP_POLLING; 3073 if ((ifp->if_capenable & IFCAP_POLLING) != 0) { 3074 error = ether_poll_register(xl_poll, ifp); 3075 if (error) 3076 break; 3077 XL_LOCK(sc); 3078 /* Disable interrupts */ 3079 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB|0); 3080 ifp->if_capenable |= IFCAP_POLLING; 3081 XL_UNLOCK(sc); 3082 } else { 3083 error = ether_poll_deregister(ifp); 3084 /* Enable interrupts. */ 3085 XL_LOCK(sc); 3086 CSR_WRITE_2(sc, XL_COMMAND, 3087 XL_CMD_INTR_ACK | 0xFF); 3088 CSR_WRITE_2(sc, XL_COMMAND, 3089 XL_CMD_INTR_ENB | XL_INTRS); 3090 if (sc->xl_flags & XL_FLAG_FUNCREG) 3091 bus_space_write_4(sc->xl_ftag, 3092 sc->xl_fhandle, 4, 0x8000); 3093 XL_UNLOCK(sc); 3094 } 3095 } 3096#endif /* DEVICE_POLLING */ 3097 XL_LOCK(sc); 3098 if ((mask & IFCAP_TXCSUM) != 0 && 3099 (ifp->if_capabilities & IFCAP_TXCSUM) != 0) { 3100 ifp->if_capenable ^= IFCAP_TXCSUM; 3101 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0) 3102 ifp->if_hwassist |= XL905B_CSUM_FEATURES; 3103 else 3104 ifp->if_hwassist &= ~XL905B_CSUM_FEATURES; 3105 } 3106 if ((mask & IFCAP_RXCSUM) != 0 && 3107 (ifp->if_capabilities & IFCAP_RXCSUM) != 0) 3108 ifp->if_capenable ^= IFCAP_RXCSUM; 3109 if ((mask & IFCAP_WOL_MAGIC) != 0 && 3110 (ifp->if_capabilities & IFCAP_WOL_MAGIC) != 0) 3111 ifp->if_capenable ^= IFCAP_WOL_MAGIC; 3112 XL_UNLOCK(sc); 3113 break; 3114 default: 3115 error = ether_ioctl(ifp, command, data); 3116 break; 3117 } 3118 3119 return (error); 3120} 3121 3122static int 3123xl_watchdog(struct xl_softc *sc) 3124{ 3125 struct ifnet *ifp = sc->xl_ifp; 3126 u_int16_t status = 0; 3127 int misintr; 3128 3129 XL_LOCK_ASSERT(sc); 3130 3131 if (sc->xl_wdog_timer == 0 || --sc->xl_wdog_timer != 0) 3132 return (0); 3133 3134 xl_rxeof(sc); 3135 xl_txeoc(sc); 3136 misintr = 0; 3137 if (sc->xl_type == XL_TYPE_905B) { 3138 xl_txeof_90xB(sc); 3139 if (sc->xl_cdata.xl_tx_cnt == 0) 3140 misintr++; 3141 } else { 3142 xl_txeof(sc); 3143 if (sc->xl_cdata.xl_tx_head == NULL) 3144 misintr++; 3145 } 3146 if (misintr != 0) { 3147 device_printf(sc->xl_dev, 3148 "watchdog timeout (missed Tx interrupts) -- recovering\n"); 3149 return (0); 3150 } 3151 3152 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 3153 XL_SEL_WIN(4); 3154 status = CSR_READ_2(sc, XL_W4_MEDIA_STATUS); 3155 device_printf(sc->xl_dev, "watchdog timeout\n"); 3156 3157 if (status & XL_MEDIASTAT_CARRIER) 3158 device_printf(sc->xl_dev, 3159 "no carrier - transceiver cable problem?\n"); 3160 3161 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 3162 xl_init_locked(sc); 3163 3164 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) { 3165 if (sc->xl_type == XL_TYPE_905B) 3166 xl_start_90xB_locked(ifp); 3167 else 3168 xl_start_locked(ifp); 3169 } 3170 3171 return (EJUSTRETURN); 3172} 3173 3174/* 3175 * Stop the adapter and free any mbufs allocated to the 3176 * RX and TX lists. 3177 */ 3178static void 3179xl_stop(struct xl_softc *sc) 3180{ 3181 int i; 3182 struct ifnet *ifp = sc->xl_ifp; 3183 3184 XL_LOCK_ASSERT(sc); 3185 3186 sc->xl_wdog_timer = 0; 3187 3188 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_DISABLE); 3189 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STATS_DISABLE); 3190 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB); 3191 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_DISCARD); 3192 xl_wait(sc); 3193 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_DISABLE); 3194 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP); 3195 DELAY(800); 3196 3197#ifdef foo 3198 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET); 3199 xl_wait(sc); 3200 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET); 3201 xl_wait(sc); 3202#endif 3203 3204 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ACK|XL_STAT_INTLATCH); 3205 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STAT_ENB|0); 3206 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB|0); 3207 if (sc->xl_flags & XL_FLAG_FUNCREG) 3208 bus_space_write_4(sc->xl_ftag, sc->xl_fhandle, 4, 0x8000); 3209 3210 /* Stop the stats updater. */ 3211 callout_stop(&sc->xl_tick_callout); 3212 3213 /* 3214 * Free data in the RX lists. 3215 */ 3216 for (i = 0; i < XL_RX_LIST_CNT; i++) { 3217 if (sc->xl_cdata.xl_rx_chain[i].xl_mbuf != NULL) { 3218 bus_dmamap_unload(sc->xl_mtag, 3219 sc->xl_cdata.xl_rx_chain[i].xl_map); 3220 bus_dmamap_destroy(sc->xl_mtag, 3221 sc->xl_cdata.xl_rx_chain[i].xl_map); 3222 m_freem(sc->xl_cdata.xl_rx_chain[i].xl_mbuf); 3223 sc->xl_cdata.xl_rx_chain[i].xl_mbuf = NULL; 3224 } 3225 } 3226 if (sc->xl_ldata.xl_rx_list != NULL) 3227 bzero(sc->xl_ldata.xl_rx_list, XL_RX_LIST_SZ); 3228 /* 3229 * Free the TX list buffers. 3230 */ 3231 for (i = 0; i < XL_TX_LIST_CNT; i++) { 3232 if (sc->xl_cdata.xl_tx_chain[i].xl_mbuf != NULL) { 3233 bus_dmamap_unload(sc->xl_mtag, 3234 sc->xl_cdata.xl_tx_chain[i].xl_map); 3235 bus_dmamap_destroy(sc->xl_mtag, 3236 sc->xl_cdata.xl_tx_chain[i].xl_map); 3237 m_freem(sc->xl_cdata.xl_tx_chain[i].xl_mbuf); 3238 sc->xl_cdata.xl_tx_chain[i].xl_mbuf = NULL; 3239 } 3240 } 3241 if (sc->xl_ldata.xl_tx_list != NULL) 3242 bzero(sc->xl_ldata.xl_tx_list, XL_TX_LIST_SZ); 3243 3244 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 3245} 3246 3247/* 3248 * Stop all chip I/O so that the kernel's probe routines don't 3249 * get confused by errant DMAs when rebooting. 3250 */ 3251static int 3252xl_shutdown(device_t dev) 3253{ 3254 3255 return (xl_suspend(dev)); 3256} 3257 3258static int 3259xl_suspend(device_t dev) 3260{ 3261 struct xl_softc *sc; 3262 3263 sc = device_get_softc(dev); 3264 3265 XL_LOCK(sc); 3266 xl_stop(sc); 3267 xl_setwol(sc); 3268 XL_UNLOCK(sc); 3269 3270 return (0); 3271} 3272 3273static int 3274xl_resume(device_t dev) 3275{ 3276 struct xl_softc *sc; 3277 struct ifnet *ifp; 3278 3279 sc = device_get_softc(dev); 3280 ifp = sc->xl_ifp; 3281 3282 XL_LOCK(sc); 3283 3284 if (ifp->if_flags & IFF_UP) { 3285 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 3286 xl_init_locked(sc); 3287 } 3288 3289 XL_UNLOCK(sc); 3290 3291 return (0); 3292} 3293 3294static void 3295xl_setwol(struct xl_softc *sc) 3296{ 3297 struct ifnet *ifp; 3298 u_int16_t cfg, pmstat; 3299 3300 if ((sc->xl_flags & XL_FLAG_WOL) == 0) 3301 return; 3302 3303 ifp = sc->xl_ifp; 3304 XL_SEL_WIN(7); 3305 /* Clear any pending PME events. */ 3306 CSR_READ_2(sc, XL_W7_BM_PME); 3307 cfg = 0; 3308 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) 3309 cfg |= XL_BM_PME_MAGIC; 3310 CSR_WRITE_2(sc, XL_W7_BM_PME, cfg); 3311 /* Enable RX. */ 3312 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) 3313 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_ENABLE); 3314 /* Request PME. */ 3315 pmstat = pci_read_config(sc->xl_dev, 3316 sc->xl_pmcap + PCIR_POWER_STATUS, 2); 3317 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) 3318 pmstat |= PCIM_PSTAT_PMEENABLE; 3319 else 3320 pmstat &= ~PCIM_PSTAT_PMEENABLE; 3321 pci_write_config(sc->xl_dev, 3322 sc->xl_pmcap + PCIR_POWER_STATUS, pmstat, 2); 3323} 3324