1/*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2008, Pyun YongHyeon <yongari@FreeBSD.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice unmodified, this list of conditions, and the following 12 * disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30/* Driver for Attansic Technology Corp. L1 Gigabit Ethernet. */ 31 32#include <sys/cdefs.h> 33__FBSDID("$FreeBSD: releng/12.0/sys/dev/age/if_age.c 338948 2018-09-26 17:12:14Z imp $"); 34 35#include <sys/param.h> 36#include <sys/systm.h> 37#include <sys/bus.h> 38#include <sys/endian.h> 39#include <sys/kernel.h> 40#include <sys/malloc.h> 41#include <sys/mbuf.h> 42#include <sys/rman.h> 43#include <sys/module.h> 44#include <sys/queue.h> 45#include <sys/socket.h> 46#include <sys/sockio.h> 47#include <sys/sysctl.h> 48#include <sys/taskqueue.h> 49 50#include <net/bpf.h> 51#include <net/if.h> 52#include <net/if_var.h> 53#include <net/if_arp.h> 54#include <net/ethernet.h> 55#include <net/if_dl.h> 56#include <net/if_media.h> 57#include <net/if_types.h> 58#include <net/if_vlan_var.h> 59 60#include <netinet/in.h> 61#include <netinet/in_systm.h> 62#include <netinet/ip.h> 63#include <netinet/tcp.h> 64 65#include <dev/mii/mii.h> 66#include <dev/mii/miivar.h> 67 68#include <dev/pci/pcireg.h> 69#include <dev/pci/pcivar.h> 70 71#include <machine/bus.h> 72#include <machine/in_cksum.h> 73 74#include <dev/age/if_agereg.h> 75#include <dev/age/if_agevar.h> 76 77/* "device miibus" required. See GENERIC if you get errors here. */ 78#include "miibus_if.h" 79 80#define AGE_CSUM_FEATURES (CSUM_TCP | CSUM_UDP) 81 82MODULE_DEPEND(age, pci, 1, 1, 1); 83MODULE_DEPEND(age, ether, 1, 1, 1); 84MODULE_DEPEND(age, miibus, 1, 1, 1); 85 86/* Tunables. */ 87static int msi_disable = 0; 88static int msix_disable = 0; 89TUNABLE_INT("hw.age.msi_disable", &msi_disable); 90TUNABLE_INT("hw.age.msix_disable", &msix_disable); 91 92/* 93 * Devices supported by this driver. 94 */ 95static struct age_dev { 96 uint16_t age_vendorid; 97 uint16_t age_deviceid; 98 const char *age_name; 99} age_devs[] = { 100 { VENDORID_ATTANSIC, DEVICEID_ATTANSIC_L1, 101 "Attansic Technology Corp, L1 Gigabit Ethernet" }, 102}; 103 104static int age_miibus_readreg(device_t, int, int); 105static int age_miibus_writereg(device_t, int, int, int); 106static void age_miibus_statchg(device_t); 107static void age_mediastatus(struct ifnet *, struct ifmediareq *); 108static int age_mediachange(struct ifnet *); 109static int age_probe(device_t); 110static void age_get_macaddr(struct age_softc *); 111static void age_phy_reset(struct age_softc *); 112static int age_attach(device_t); 113static int age_detach(device_t); 114static void age_sysctl_node(struct age_softc *); 115static void age_dmamap_cb(void *, bus_dma_segment_t *, int, int); 116static int age_check_boundary(struct age_softc *); 117static int age_dma_alloc(struct age_softc *); 118static void age_dma_free(struct age_softc *); 119static int age_shutdown(device_t); 120static void age_setwol(struct age_softc *); 121static int age_suspend(device_t); 122static int age_resume(device_t); 123static int age_encap(struct age_softc *, struct mbuf **); 124static void age_start(struct ifnet *); 125static void age_start_locked(struct ifnet *); 126static void age_watchdog(struct age_softc *); 127static int age_ioctl(struct ifnet *, u_long, caddr_t); 128static void age_mac_config(struct age_softc *); 129static void age_link_task(void *, int); 130static void age_stats_update(struct age_softc *); 131static int age_intr(void *); 132static void age_int_task(void *, int); 133static void age_txintr(struct age_softc *, int); 134static void age_rxeof(struct age_softc *sc, struct rx_rdesc *); 135static int age_rxintr(struct age_softc *, int, int); 136static void age_tick(void *); 137static void age_reset(struct age_softc *); 138static void age_init(void *); 139static void age_init_locked(struct age_softc *); 140static void age_stop(struct age_softc *); 141static void age_stop_txmac(struct age_softc *); 142static void age_stop_rxmac(struct age_softc *); 143static void age_init_tx_ring(struct age_softc *); 144static int age_init_rx_ring(struct age_softc *); 145static void age_init_rr_ring(struct age_softc *); 146static void age_init_cmb_block(struct age_softc *); 147static void age_init_smb_block(struct age_softc *); 148#ifndef __NO_STRICT_ALIGNMENT 149static struct mbuf *age_fixup_rx(struct ifnet *, struct mbuf *); 150#endif 151static int age_newbuf(struct age_softc *, struct age_rxdesc *); 152static void age_rxvlan(struct age_softc *); 153static void age_rxfilter(struct age_softc *); 154static int sysctl_age_stats(SYSCTL_HANDLER_ARGS); 155static int sysctl_int_range(SYSCTL_HANDLER_ARGS, int, int); 156static int sysctl_hw_age_proc_limit(SYSCTL_HANDLER_ARGS); 157static int sysctl_hw_age_int_mod(SYSCTL_HANDLER_ARGS); 158 159 160static device_method_t age_methods[] = { 161 /* Device interface. */ 162 DEVMETHOD(device_probe, age_probe), 163 DEVMETHOD(device_attach, age_attach), 164 DEVMETHOD(device_detach, age_detach), 165 DEVMETHOD(device_shutdown, age_shutdown), 166 DEVMETHOD(device_suspend, age_suspend), 167 DEVMETHOD(device_resume, age_resume), 168 169 /* MII interface. */ 170 DEVMETHOD(miibus_readreg, age_miibus_readreg), 171 DEVMETHOD(miibus_writereg, age_miibus_writereg), 172 DEVMETHOD(miibus_statchg, age_miibus_statchg), 173 174 { NULL, NULL } 175}; 176 177static driver_t age_driver = { 178 "age", 179 age_methods, 180 sizeof(struct age_softc) 181}; 182 183static devclass_t age_devclass; 184 185DRIVER_MODULE(age, pci, age_driver, age_devclass, 0, 0); 186MODULE_PNP_INFO("U16:vendor;U16:device;D:#", pci, age, age_devs, 187 nitems(age_devs)); 188DRIVER_MODULE(miibus, age, miibus_driver, miibus_devclass, 0, 0); 189 190static struct resource_spec age_res_spec_mem[] = { 191 { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE }, 192 { -1, 0, 0 } 193}; 194 195static struct resource_spec age_irq_spec_legacy[] = { 196 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE }, 197 { -1, 0, 0 } 198}; 199 200static struct resource_spec age_irq_spec_msi[] = { 201 { SYS_RES_IRQ, 1, RF_ACTIVE }, 202 { -1, 0, 0 } 203}; 204 205static struct resource_spec age_irq_spec_msix[] = { 206 { SYS_RES_IRQ, 1, RF_ACTIVE }, 207 { -1, 0, 0 } 208}; 209 210/* 211 * Read a PHY register on the MII of the L1. 212 */ 213static int 214age_miibus_readreg(device_t dev, int phy, int reg) 215{ 216 struct age_softc *sc; 217 uint32_t v; 218 int i; 219 220 sc = device_get_softc(dev); 221 222 CSR_WRITE_4(sc, AGE_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ | 223 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); 224 for (i = AGE_PHY_TIMEOUT; i > 0; i--) { 225 DELAY(1); 226 v = CSR_READ_4(sc, AGE_MDIO); 227 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) 228 break; 229 } 230 231 if (i == 0) { 232 device_printf(sc->age_dev, "phy read timeout : %d\n", reg); 233 return (0); 234 } 235 236 return ((v & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT); 237} 238 239/* 240 * Write a PHY register on the MII of the L1. 241 */ 242static int 243age_miibus_writereg(device_t dev, int phy, int reg, int val) 244{ 245 struct age_softc *sc; 246 uint32_t v; 247 int i; 248 249 sc = device_get_softc(dev); 250 251 CSR_WRITE_4(sc, AGE_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE | 252 (val & MDIO_DATA_MASK) << MDIO_DATA_SHIFT | 253 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); 254 for (i = AGE_PHY_TIMEOUT; i > 0; i--) { 255 DELAY(1); 256 v = CSR_READ_4(sc, AGE_MDIO); 257 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) 258 break; 259 } 260 261 if (i == 0) 262 device_printf(sc->age_dev, "phy write timeout : %d\n", reg); 263 264 return (0); 265} 266 267/* 268 * Callback from MII layer when media changes. 269 */ 270static void 271age_miibus_statchg(device_t dev) 272{ 273 struct age_softc *sc; 274 275 sc = device_get_softc(dev); 276 taskqueue_enqueue(taskqueue_swi, &sc->age_link_task); 277} 278 279/* 280 * Get the current interface media status. 281 */ 282static void 283age_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 284{ 285 struct age_softc *sc; 286 struct mii_data *mii; 287 288 sc = ifp->if_softc; 289 AGE_LOCK(sc); 290 mii = device_get_softc(sc->age_miibus); 291 292 mii_pollstat(mii); 293 ifmr->ifm_status = mii->mii_media_status; 294 ifmr->ifm_active = mii->mii_media_active; 295 AGE_UNLOCK(sc); 296} 297 298/* 299 * Set hardware to newly-selected media. 300 */ 301static int 302age_mediachange(struct ifnet *ifp) 303{ 304 struct age_softc *sc; 305 struct mii_data *mii; 306 struct mii_softc *miisc; 307 int error; 308 309 sc = ifp->if_softc; 310 AGE_LOCK(sc); 311 mii = device_get_softc(sc->age_miibus); 312 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 313 PHY_RESET(miisc); 314 error = mii_mediachg(mii); 315 AGE_UNLOCK(sc); 316 317 return (error); 318} 319 320static int 321age_probe(device_t dev) 322{ 323 struct age_dev *sp; 324 int i; 325 uint16_t vendor, devid; 326 327 vendor = pci_get_vendor(dev); 328 devid = pci_get_device(dev); 329 sp = age_devs; 330 for (i = 0; i < nitems(age_devs); i++, sp++) { 331 if (vendor == sp->age_vendorid && 332 devid == sp->age_deviceid) { 333 device_set_desc(dev, sp->age_name); 334 return (BUS_PROBE_DEFAULT); 335 } 336 } 337 338 return (ENXIO); 339} 340 341static void 342age_get_macaddr(struct age_softc *sc) 343{ 344 uint32_t ea[2], reg; 345 int i, vpdc; 346 347 reg = CSR_READ_4(sc, AGE_SPI_CTRL); 348 if ((reg & SPI_VPD_ENB) != 0) { 349 /* Get VPD stored in TWSI EEPROM. */ 350 reg &= ~SPI_VPD_ENB; 351 CSR_WRITE_4(sc, AGE_SPI_CTRL, reg); 352 } 353 354 if (pci_find_cap(sc->age_dev, PCIY_VPD, &vpdc) == 0) { 355 /* 356 * PCI VPD capability found, let TWSI reload EEPROM. 357 * This will set ethernet address of controller. 358 */ 359 CSR_WRITE_4(sc, AGE_TWSI_CTRL, CSR_READ_4(sc, AGE_TWSI_CTRL) | 360 TWSI_CTRL_SW_LD_START); 361 for (i = 100; i > 0; i--) { 362 DELAY(1000); 363 reg = CSR_READ_4(sc, AGE_TWSI_CTRL); 364 if ((reg & TWSI_CTRL_SW_LD_START) == 0) 365 break; 366 } 367 if (i == 0) 368 device_printf(sc->age_dev, 369 "reloading EEPROM timeout!\n"); 370 } else { 371 if (bootverbose) 372 device_printf(sc->age_dev, 373 "PCI VPD capability not found!\n"); 374 } 375 376 ea[0] = CSR_READ_4(sc, AGE_PAR0); 377 ea[1] = CSR_READ_4(sc, AGE_PAR1); 378 sc->age_eaddr[0] = (ea[1] >> 8) & 0xFF; 379 sc->age_eaddr[1] = (ea[1] >> 0) & 0xFF; 380 sc->age_eaddr[2] = (ea[0] >> 24) & 0xFF; 381 sc->age_eaddr[3] = (ea[0] >> 16) & 0xFF; 382 sc->age_eaddr[4] = (ea[0] >> 8) & 0xFF; 383 sc->age_eaddr[5] = (ea[0] >> 0) & 0xFF; 384} 385 386static void 387age_phy_reset(struct age_softc *sc) 388{ 389 uint16_t reg, pn; 390 int i, linkup; 391 392 /* Reset PHY. */ 393 CSR_WRITE_4(sc, AGE_GPHY_CTRL, GPHY_CTRL_RST); 394 DELAY(2000); 395 CSR_WRITE_4(sc, AGE_GPHY_CTRL, GPHY_CTRL_CLR); 396 DELAY(2000); 397 398#define ATPHY_DBG_ADDR 0x1D 399#define ATPHY_DBG_DATA 0x1E 400#define ATPHY_CDTC 0x16 401#define PHY_CDTC_ENB 0x0001 402#define PHY_CDTC_POFF 8 403#define ATPHY_CDTS 0x1C 404#define PHY_CDTS_STAT_OK 0x0000 405#define PHY_CDTS_STAT_SHORT 0x0100 406#define PHY_CDTS_STAT_OPEN 0x0200 407#define PHY_CDTS_STAT_INVAL 0x0300 408#define PHY_CDTS_STAT_MASK 0x0300 409 410 /* Check power saving mode. Magic from Linux. */ 411 age_miibus_writereg(sc->age_dev, sc->age_phyaddr, MII_BMCR, BMCR_RESET); 412 for (linkup = 0, pn = 0; pn < 4; pn++) { 413 age_miibus_writereg(sc->age_dev, sc->age_phyaddr, ATPHY_CDTC, 414 (pn << PHY_CDTC_POFF) | PHY_CDTC_ENB); 415 for (i = 200; i > 0; i--) { 416 DELAY(1000); 417 reg = age_miibus_readreg(sc->age_dev, sc->age_phyaddr, 418 ATPHY_CDTC); 419 if ((reg & PHY_CDTC_ENB) == 0) 420 break; 421 } 422 DELAY(1000); 423 reg = age_miibus_readreg(sc->age_dev, sc->age_phyaddr, 424 ATPHY_CDTS); 425 if ((reg & PHY_CDTS_STAT_MASK) != PHY_CDTS_STAT_OPEN) { 426 linkup++; 427 break; 428 } 429 } 430 age_miibus_writereg(sc->age_dev, sc->age_phyaddr, MII_BMCR, 431 BMCR_RESET | BMCR_AUTOEN | BMCR_STARTNEG); 432 if (linkup == 0) { 433 age_miibus_writereg(sc->age_dev, sc->age_phyaddr, 434 ATPHY_DBG_ADDR, 0); 435 age_miibus_writereg(sc->age_dev, sc->age_phyaddr, 436 ATPHY_DBG_DATA, 0x124E); 437 age_miibus_writereg(sc->age_dev, sc->age_phyaddr, 438 ATPHY_DBG_ADDR, 1); 439 reg = age_miibus_readreg(sc->age_dev, sc->age_phyaddr, 440 ATPHY_DBG_DATA); 441 age_miibus_writereg(sc->age_dev, sc->age_phyaddr, 442 ATPHY_DBG_DATA, reg | 0x03); 443 /* XXX */ 444 DELAY(1500 * 1000); 445 age_miibus_writereg(sc->age_dev, sc->age_phyaddr, 446 ATPHY_DBG_ADDR, 0); 447 age_miibus_writereg(sc->age_dev, sc->age_phyaddr, 448 ATPHY_DBG_DATA, 0x024E); 449 } 450 451#undef ATPHY_DBG_ADDR 452#undef ATPHY_DBG_DATA 453#undef ATPHY_CDTC 454#undef PHY_CDTC_ENB 455#undef PHY_CDTC_POFF 456#undef ATPHY_CDTS 457#undef PHY_CDTS_STAT_OK 458#undef PHY_CDTS_STAT_SHORT 459#undef PHY_CDTS_STAT_OPEN 460#undef PHY_CDTS_STAT_INVAL 461#undef PHY_CDTS_STAT_MASK 462} 463 464static int 465age_attach(device_t dev) 466{ 467 struct age_softc *sc; 468 struct ifnet *ifp; 469 uint16_t burst; 470 int error, i, msic, msixc, pmc; 471 472 error = 0; 473 sc = device_get_softc(dev); 474 sc->age_dev = dev; 475 476 mtx_init(&sc->age_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 477 MTX_DEF); 478 callout_init_mtx(&sc->age_tick_ch, &sc->age_mtx, 0); 479 TASK_INIT(&sc->age_int_task, 0, age_int_task, sc); 480 TASK_INIT(&sc->age_link_task, 0, age_link_task, sc); 481 482 /* Map the device. */ 483 pci_enable_busmaster(dev); 484 sc->age_res_spec = age_res_spec_mem; 485 sc->age_irq_spec = age_irq_spec_legacy; 486 error = bus_alloc_resources(dev, sc->age_res_spec, sc->age_res); 487 if (error != 0) { 488 device_printf(dev, "cannot allocate memory resources.\n"); 489 goto fail; 490 } 491 492 /* Set PHY address. */ 493 sc->age_phyaddr = AGE_PHY_ADDR; 494 495 /* Reset PHY. */ 496 age_phy_reset(sc); 497 498 /* Reset the ethernet controller. */ 499 age_reset(sc); 500 501 /* Get PCI and chip id/revision. */ 502 sc->age_rev = pci_get_revid(dev); 503 sc->age_chip_rev = CSR_READ_4(sc, AGE_MASTER_CFG) >> 504 MASTER_CHIP_REV_SHIFT; 505 if (bootverbose) { 506 device_printf(dev, "PCI device revision : 0x%04x\n", 507 sc->age_rev); 508 device_printf(dev, "Chip id/revision : 0x%04x\n", 509 sc->age_chip_rev); 510 } 511 512 /* 513 * XXX 514 * Unintialized hardware returns an invalid chip id/revision 515 * as well as 0xFFFFFFFF for Tx/Rx fifo length. It seems that 516 * unplugged cable results in putting hardware into automatic 517 * power down mode which in turn returns invalld chip revision. 518 */ 519 if (sc->age_chip_rev == 0xFFFF) { 520 device_printf(dev,"invalid chip revision : 0x%04x -- " 521 "not initialized?\n", sc->age_chip_rev); 522 error = ENXIO; 523 goto fail; 524 } 525 526 device_printf(dev, "%d Tx FIFO, %d Rx FIFO\n", 527 CSR_READ_4(sc, AGE_SRAM_TX_FIFO_LEN), 528 CSR_READ_4(sc, AGE_SRAM_RX_FIFO_LEN)); 529 530 /* Allocate IRQ resources. */ 531 msixc = pci_msix_count(dev); 532 msic = pci_msi_count(dev); 533 if (bootverbose) { 534 device_printf(dev, "MSIX count : %d\n", msixc); 535 device_printf(dev, "MSI count : %d\n", msic); 536 } 537 538 /* Prefer MSIX over MSI. */ 539 if (msix_disable == 0 || msi_disable == 0) { 540 if (msix_disable == 0 && msixc == AGE_MSIX_MESSAGES && 541 pci_alloc_msix(dev, &msixc) == 0) { 542 if (msic == AGE_MSIX_MESSAGES) { 543 device_printf(dev, "Using %d MSIX messages.\n", 544 msixc); 545 sc->age_flags |= AGE_FLAG_MSIX; 546 sc->age_irq_spec = age_irq_spec_msix; 547 } else 548 pci_release_msi(dev); 549 } 550 if (msi_disable == 0 && (sc->age_flags & AGE_FLAG_MSIX) == 0 && 551 msic == AGE_MSI_MESSAGES && 552 pci_alloc_msi(dev, &msic) == 0) { 553 if (msic == AGE_MSI_MESSAGES) { 554 device_printf(dev, "Using %d MSI messages.\n", 555 msic); 556 sc->age_flags |= AGE_FLAG_MSI; 557 sc->age_irq_spec = age_irq_spec_msi; 558 } else 559 pci_release_msi(dev); 560 } 561 } 562 563 error = bus_alloc_resources(dev, sc->age_irq_spec, sc->age_irq); 564 if (error != 0) { 565 device_printf(dev, "cannot allocate IRQ resources.\n"); 566 goto fail; 567 } 568 569 570 /* Get DMA parameters from PCIe device control register. */ 571 if (pci_find_cap(dev, PCIY_EXPRESS, &i) == 0) { 572 sc->age_flags |= AGE_FLAG_PCIE; 573 burst = pci_read_config(dev, i + 0x08, 2); 574 /* Max read request size. */ 575 sc->age_dma_rd_burst = ((burst >> 12) & 0x07) << 576 DMA_CFG_RD_BURST_SHIFT; 577 /* Max payload size. */ 578 sc->age_dma_wr_burst = ((burst >> 5) & 0x07) << 579 DMA_CFG_WR_BURST_SHIFT; 580 if (bootverbose) { 581 device_printf(dev, "Read request size : %d bytes.\n", 582 128 << ((burst >> 12) & 0x07)); 583 device_printf(dev, "TLP payload size : %d bytes.\n", 584 128 << ((burst >> 5) & 0x07)); 585 } 586 } else { 587 sc->age_dma_rd_burst = DMA_CFG_RD_BURST_128; 588 sc->age_dma_wr_burst = DMA_CFG_WR_BURST_128; 589 } 590 591 /* Create device sysctl node. */ 592 age_sysctl_node(sc); 593 594 if ((error = age_dma_alloc(sc)) != 0) 595 goto fail; 596 597 /* Load station address. */ 598 age_get_macaddr(sc); 599 600 ifp = sc->age_ifp = if_alloc(IFT_ETHER); 601 if (ifp == NULL) { 602 device_printf(dev, "cannot allocate ifnet structure.\n"); 603 error = ENXIO; 604 goto fail; 605 } 606 607 ifp->if_softc = sc; 608 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 609 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 610 ifp->if_ioctl = age_ioctl; 611 ifp->if_start = age_start; 612 ifp->if_init = age_init; 613 ifp->if_snd.ifq_drv_maxlen = AGE_TX_RING_CNT - 1; 614 IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen); 615 IFQ_SET_READY(&ifp->if_snd); 616 ifp->if_capabilities = IFCAP_HWCSUM | IFCAP_TSO4; 617 ifp->if_hwassist = AGE_CSUM_FEATURES | CSUM_TSO; 618 if (pci_find_cap(dev, PCIY_PMG, &pmc) == 0) { 619 sc->age_flags |= AGE_FLAG_PMCAP; 620 ifp->if_capabilities |= IFCAP_WOL_MAGIC | IFCAP_WOL_MCAST; 621 } 622 ifp->if_capenable = ifp->if_capabilities; 623 624 /* Set up MII bus. */ 625 error = mii_attach(dev, &sc->age_miibus, ifp, age_mediachange, 626 age_mediastatus, BMSR_DEFCAPMASK, sc->age_phyaddr, MII_OFFSET_ANY, 627 0); 628 if (error != 0) { 629 device_printf(dev, "attaching PHYs failed\n"); 630 goto fail; 631 } 632 633 ether_ifattach(ifp, sc->age_eaddr); 634 635 /* VLAN capability setup. */ 636 ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING | 637 IFCAP_VLAN_HWCSUM | IFCAP_VLAN_HWTSO; 638 ifp->if_capenable = ifp->if_capabilities; 639 640 /* Tell the upper layer(s) we support long frames. */ 641 ifp->if_hdrlen = sizeof(struct ether_vlan_header); 642 643 /* Create local taskq. */ 644 sc->age_tq = taskqueue_create_fast("age_taskq", M_WAITOK, 645 taskqueue_thread_enqueue, &sc->age_tq); 646 if (sc->age_tq == NULL) { 647 device_printf(dev, "could not create taskqueue.\n"); 648 ether_ifdetach(ifp); 649 error = ENXIO; 650 goto fail; 651 } 652 taskqueue_start_threads(&sc->age_tq, 1, PI_NET, "%s taskq", 653 device_get_nameunit(sc->age_dev)); 654 655 if ((sc->age_flags & AGE_FLAG_MSIX) != 0) 656 msic = AGE_MSIX_MESSAGES; 657 else if ((sc->age_flags & AGE_FLAG_MSI) != 0) 658 msic = AGE_MSI_MESSAGES; 659 else 660 msic = 1; 661 for (i = 0; i < msic; i++) { 662 error = bus_setup_intr(dev, sc->age_irq[i], 663 INTR_TYPE_NET | INTR_MPSAFE, age_intr, NULL, sc, 664 &sc->age_intrhand[i]); 665 if (error != 0) 666 break; 667 } 668 if (error != 0) { 669 device_printf(dev, "could not set up interrupt handler.\n"); 670 taskqueue_free(sc->age_tq); 671 sc->age_tq = NULL; 672 ether_ifdetach(ifp); 673 goto fail; 674 } 675 676fail: 677 if (error != 0) 678 age_detach(dev); 679 680 return (error); 681} 682 683static int 684age_detach(device_t dev) 685{ 686 struct age_softc *sc; 687 struct ifnet *ifp; 688 int i, msic; 689 690 sc = device_get_softc(dev); 691 692 ifp = sc->age_ifp; 693 if (device_is_attached(dev)) { 694 AGE_LOCK(sc); 695 sc->age_flags |= AGE_FLAG_DETACH; 696 age_stop(sc); 697 AGE_UNLOCK(sc); 698 callout_drain(&sc->age_tick_ch); 699 taskqueue_drain(sc->age_tq, &sc->age_int_task); 700 taskqueue_drain(taskqueue_swi, &sc->age_link_task); 701 ether_ifdetach(ifp); 702 } 703 704 if (sc->age_tq != NULL) { 705 taskqueue_drain(sc->age_tq, &sc->age_int_task); 706 taskqueue_free(sc->age_tq); 707 sc->age_tq = NULL; 708 } 709 710 if (sc->age_miibus != NULL) { 711 device_delete_child(dev, sc->age_miibus); 712 sc->age_miibus = NULL; 713 } 714 bus_generic_detach(dev); 715 age_dma_free(sc); 716 717 if (ifp != NULL) { 718 if_free(ifp); 719 sc->age_ifp = NULL; 720 } 721 722 if ((sc->age_flags & AGE_FLAG_MSIX) != 0) 723 msic = AGE_MSIX_MESSAGES; 724 else if ((sc->age_flags & AGE_FLAG_MSI) != 0) 725 msic = AGE_MSI_MESSAGES; 726 else 727 msic = 1; 728 for (i = 0; i < msic; i++) { 729 if (sc->age_intrhand[i] != NULL) { 730 bus_teardown_intr(dev, sc->age_irq[i], 731 sc->age_intrhand[i]); 732 sc->age_intrhand[i] = NULL; 733 } 734 } 735 736 bus_release_resources(dev, sc->age_irq_spec, sc->age_irq); 737 if ((sc->age_flags & (AGE_FLAG_MSI | AGE_FLAG_MSIX)) != 0) 738 pci_release_msi(dev); 739 bus_release_resources(dev, sc->age_res_spec, sc->age_res); 740 mtx_destroy(&sc->age_mtx); 741 742 return (0); 743} 744 745static void 746age_sysctl_node(struct age_softc *sc) 747{ 748 int error; 749 750 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->age_dev), 751 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->age_dev)), OID_AUTO, 752 "stats", CTLTYPE_INT | CTLFLAG_RW, sc, 0, sysctl_age_stats, 753 "I", "Statistics"); 754 755 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->age_dev), 756 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->age_dev)), OID_AUTO, 757 "int_mod", CTLTYPE_INT | CTLFLAG_RW, &sc->age_int_mod, 0, 758 sysctl_hw_age_int_mod, "I", "age interrupt moderation"); 759 760 /* Pull in device tunables. */ 761 sc->age_int_mod = AGE_IM_TIMER_DEFAULT; 762 error = resource_int_value(device_get_name(sc->age_dev), 763 device_get_unit(sc->age_dev), "int_mod", &sc->age_int_mod); 764 if (error == 0) { 765 if (sc->age_int_mod < AGE_IM_TIMER_MIN || 766 sc->age_int_mod > AGE_IM_TIMER_MAX) { 767 device_printf(sc->age_dev, 768 "int_mod value out of range; using default: %d\n", 769 AGE_IM_TIMER_DEFAULT); 770 sc->age_int_mod = AGE_IM_TIMER_DEFAULT; 771 } 772 } 773 774 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->age_dev), 775 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->age_dev)), OID_AUTO, 776 "process_limit", CTLTYPE_INT | CTLFLAG_RW, &sc->age_process_limit, 777 0, sysctl_hw_age_proc_limit, "I", 778 "max number of Rx events to process"); 779 780 /* Pull in device tunables. */ 781 sc->age_process_limit = AGE_PROC_DEFAULT; 782 error = resource_int_value(device_get_name(sc->age_dev), 783 device_get_unit(sc->age_dev), "process_limit", 784 &sc->age_process_limit); 785 if (error == 0) { 786 if (sc->age_process_limit < AGE_PROC_MIN || 787 sc->age_process_limit > AGE_PROC_MAX) { 788 device_printf(sc->age_dev, 789 "process_limit value out of range; " 790 "using default: %d\n", AGE_PROC_DEFAULT); 791 sc->age_process_limit = AGE_PROC_DEFAULT; 792 } 793 } 794} 795 796struct age_dmamap_arg { 797 bus_addr_t age_busaddr; 798}; 799 800static void 801age_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 802{ 803 struct age_dmamap_arg *ctx; 804 805 if (error != 0) 806 return; 807 808 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 809 810 ctx = (struct age_dmamap_arg *)arg; 811 ctx->age_busaddr = segs[0].ds_addr; 812} 813 814/* 815 * Attansic L1 controller have single register to specify high 816 * address part of DMA blocks. So all descriptor structures and 817 * DMA memory blocks should have the same high address of given 818 * 4GB address space(i.e. crossing 4GB boundary is not allowed). 819 */ 820static int 821age_check_boundary(struct age_softc *sc) 822{ 823 bus_addr_t rx_ring_end, rr_ring_end, tx_ring_end; 824 bus_addr_t cmb_block_end, smb_block_end; 825 826 /* Tx/Rx descriptor queue should reside within 4GB boundary. */ 827 tx_ring_end = sc->age_rdata.age_tx_ring_paddr + AGE_TX_RING_SZ; 828 rx_ring_end = sc->age_rdata.age_rx_ring_paddr + AGE_RX_RING_SZ; 829 rr_ring_end = sc->age_rdata.age_rr_ring_paddr + AGE_RR_RING_SZ; 830 cmb_block_end = sc->age_rdata.age_cmb_block_paddr + AGE_CMB_BLOCK_SZ; 831 smb_block_end = sc->age_rdata.age_smb_block_paddr + AGE_SMB_BLOCK_SZ; 832 833 if ((AGE_ADDR_HI(tx_ring_end) != 834 AGE_ADDR_HI(sc->age_rdata.age_tx_ring_paddr)) || 835 (AGE_ADDR_HI(rx_ring_end) != 836 AGE_ADDR_HI(sc->age_rdata.age_rx_ring_paddr)) || 837 (AGE_ADDR_HI(rr_ring_end) != 838 AGE_ADDR_HI(sc->age_rdata.age_rr_ring_paddr)) || 839 (AGE_ADDR_HI(cmb_block_end) != 840 AGE_ADDR_HI(sc->age_rdata.age_cmb_block_paddr)) || 841 (AGE_ADDR_HI(smb_block_end) != 842 AGE_ADDR_HI(sc->age_rdata.age_smb_block_paddr))) 843 return (EFBIG); 844 845 if ((AGE_ADDR_HI(tx_ring_end) != AGE_ADDR_HI(rx_ring_end)) || 846 (AGE_ADDR_HI(tx_ring_end) != AGE_ADDR_HI(rr_ring_end)) || 847 (AGE_ADDR_HI(tx_ring_end) != AGE_ADDR_HI(cmb_block_end)) || 848 (AGE_ADDR_HI(tx_ring_end) != AGE_ADDR_HI(smb_block_end))) 849 return (EFBIG); 850 851 return (0); 852} 853 854static int 855age_dma_alloc(struct age_softc *sc) 856{ 857 struct age_txdesc *txd; 858 struct age_rxdesc *rxd; 859 bus_addr_t lowaddr; 860 struct age_dmamap_arg ctx; 861 int error, i; 862 863 lowaddr = BUS_SPACE_MAXADDR; 864 865again: 866 /* Create parent ring/DMA block tag. */ 867 error = bus_dma_tag_create( 868 bus_get_dma_tag(sc->age_dev), /* parent */ 869 1, 0, /* alignment, boundary */ 870 lowaddr, /* lowaddr */ 871 BUS_SPACE_MAXADDR, /* highaddr */ 872 NULL, NULL, /* filter, filterarg */ 873 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 874 0, /* nsegments */ 875 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 876 0, /* flags */ 877 NULL, NULL, /* lockfunc, lockarg */ 878 &sc->age_cdata.age_parent_tag); 879 if (error != 0) { 880 device_printf(sc->age_dev, 881 "could not create parent DMA tag.\n"); 882 goto fail; 883 } 884 885 /* Create tag for Tx ring. */ 886 error = bus_dma_tag_create( 887 sc->age_cdata.age_parent_tag, /* parent */ 888 AGE_TX_RING_ALIGN, 0, /* alignment, boundary */ 889 BUS_SPACE_MAXADDR, /* lowaddr */ 890 BUS_SPACE_MAXADDR, /* highaddr */ 891 NULL, NULL, /* filter, filterarg */ 892 AGE_TX_RING_SZ, /* maxsize */ 893 1, /* nsegments */ 894 AGE_TX_RING_SZ, /* maxsegsize */ 895 0, /* flags */ 896 NULL, NULL, /* lockfunc, lockarg */ 897 &sc->age_cdata.age_tx_ring_tag); 898 if (error != 0) { 899 device_printf(sc->age_dev, 900 "could not create Tx ring DMA tag.\n"); 901 goto fail; 902 } 903 904 /* Create tag for Rx ring. */ 905 error = bus_dma_tag_create( 906 sc->age_cdata.age_parent_tag, /* parent */ 907 AGE_RX_RING_ALIGN, 0, /* alignment, boundary */ 908 BUS_SPACE_MAXADDR, /* lowaddr */ 909 BUS_SPACE_MAXADDR, /* highaddr */ 910 NULL, NULL, /* filter, filterarg */ 911 AGE_RX_RING_SZ, /* maxsize */ 912 1, /* nsegments */ 913 AGE_RX_RING_SZ, /* maxsegsize */ 914 0, /* flags */ 915 NULL, NULL, /* lockfunc, lockarg */ 916 &sc->age_cdata.age_rx_ring_tag); 917 if (error != 0) { 918 device_printf(sc->age_dev, 919 "could not create Rx ring DMA tag.\n"); 920 goto fail; 921 } 922 923 /* Create tag for Rx return ring. */ 924 error = bus_dma_tag_create( 925 sc->age_cdata.age_parent_tag, /* parent */ 926 AGE_RR_RING_ALIGN, 0, /* alignment, boundary */ 927 BUS_SPACE_MAXADDR, /* lowaddr */ 928 BUS_SPACE_MAXADDR, /* highaddr */ 929 NULL, NULL, /* filter, filterarg */ 930 AGE_RR_RING_SZ, /* maxsize */ 931 1, /* nsegments */ 932 AGE_RR_RING_SZ, /* maxsegsize */ 933 0, /* flags */ 934 NULL, NULL, /* lockfunc, lockarg */ 935 &sc->age_cdata.age_rr_ring_tag); 936 if (error != 0) { 937 device_printf(sc->age_dev, 938 "could not create Rx return ring DMA tag.\n"); 939 goto fail; 940 } 941 942 /* Create tag for coalesing message block. */ 943 error = bus_dma_tag_create( 944 sc->age_cdata.age_parent_tag, /* parent */ 945 AGE_CMB_ALIGN, 0, /* alignment, boundary */ 946 BUS_SPACE_MAXADDR, /* lowaddr */ 947 BUS_SPACE_MAXADDR, /* highaddr */ 948 NULL, NULL, /* filter, filterarg */ 949 AGE_CMB_BLOCK_SZ, /* maxsize */ 950 1, /* nsegments */ 951 AGE_CMB_BLOCK_SZ, /* maxsegsize */ 952 0, /* flags */ 953 NULL, NULL, /* lockfunc, lockarg */ 954 &sc->age_cdata.age_cmb_block_tag); 955 if (error != 0) { 956 device_printf(sc->age_dev, 957 "could not create CMB DMA tag.\n"); 958 goto fail; 959 } 960 961 /* Create tag for statistics message block. */ 962 error = bus_dma_tag_create( 963 sc->age_cdata.age_parent_tag, /* parent */ 964 AGE_SMB_ALIGN, 0, /* alignment, boundary */ 965 BUS_SPACE_MAXADDR, /* lowaddr */ 966 BUS_SPACE_MAXADDR, /* highaddr */ 967 NULL, NULL, /* filter, filterarg */ 968 AGE_SMB_BLOCK_SZ, /* maxsize */ 969 1, /* nsegments */ 970 AGE_SMB_BLOCK_SZ, /* maxsegsize */ 971 0, /* flags */ 972 NULL, NULL, /* lockfunc, lockarg */ 973 &sc->age_cdata.age_smb_block_tag); 974 if (error != 0) { 975 device_printf(sc->age_dev, 976 "could not create SMB DMA tag.\n"); 977 goto fail; 978 } 979 980 /* Allocate DMA'able memory and load the DMA map. */ 981 error = bus_dmamem_alloc(sc->age_cdata.age_tx_ring_tag, 982 (void **)&sc->age_rdata.age_tx_ring, 983 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 984 &sc->age_cdata.age_tx_ring_map); 985 if (error != 0) { 986 device_printf(sc->age_dev, 987 "could not allocate DMA'able memory for Tx ring.\n"); 988 goto fail; 989 } 990 ctx.age_busaddr = 0; 991 error = bus_dmamap_load(sc->age_cdata.age_tx_ring_tag, 992 sc->age_cdata.age_tx_ring_map, sc->age_rdata.age_tx_ring, 993 AGE_TX_RING_SZ, age_dmamap_cb, &ctx, 0); 994 if (error != 0 || ctx.age_busaddr == 0) { 995 device_printf(sc->age_dev, 996 "could not load DMA'able memory for Tx ring.\n"); 997 goto fail; 998 } 999 sc->age_rdata.age_tx_ring_paddr = ctx.age_busaddr; 1000 /* Rx ring */ 1001 error = bus_dmamem_alloc(sc->age_cdata.age_rx_ring_tag, 1002 (void **)&sc->age_rdata.age_rx_ring, 1003 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1004 &sc->age_cdata.age_rx_ring_map); 1005 if (error != 0) { 1006 device_printf(sc->age_dev, 1007 "could not allocate DMA'able memory for Rx ring.\n"); 1008 goto fail; 1009 } 1010 ctx.age_busaddr = 0; 1011 error = bus_dmamap_load(sc->age_cdata.age_rx_ring_tag, 1012 sc->age_cdata.age_rx_ring_map, sc->age_rdata.age_rx_ring, 1013 AGE_RX_RING_SZ, age_dmamap_cb, &ctx, 0); 1014 if (error != 0 || ctx.age_busaddr == 0) { 1015 device_printf(sc->age_dev, 1016 "could not load DMA'able memory for Rx ring.\n"); 1017 goto fail; 1018 } 1019 sc->age_rdata.age_rx_ring_paddr = ctx.age_busaddr; 1020 /* Rx return ring */ 1021 error = bus_dmamem_alloc(sc->age_cdata.age_rr_ring_tag, 1022 (void **)&sc->age_rdata.age_rr_ring, 1023 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1024 &sc->age_cdata.age_rr_ring_map); 1025 if (error != 0) { 1026 device_printf(sc->age_dev, 1027 "could not allocate DMA'able memory for Rx return ring.\n"); 1028 goto fail; 1029 } 1030 ctx.age_busaddr = 0; 1031 error = bus_dmamap_load(sc->age_cdata.age_rr_ring_tag, 1032 sc->age_cdata.age_rr_ring_map, sc->age_rdata.age_rr_ring, 1033 AGE_RR_RING_SZ, age_dmamap_cb, 1034 &ctx, 0); 1035 if (error != 0 || ctx.age_busaddr == 0) { 1036 device_printf(sc->age_dev, 1037 "could not load DMA'able memory for Rx return ring.\n"); 1038 goto fail; 1039 } 1040 sc->age_rdata.age_rr_ring_paddr = ctx.age_busaddr; 1041 /* CMB block */ 1042 error = bus_dmamem_alloc(sc->age_cdata.age_cmb_block_tag, 1043 (void **)&sc->age_rdata.age_cmb_block, 1044 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1045 &sc->age_cdata.age_cmb_block_map); 1046 if (error != 0) { 1047 device_printf(sc->age_dev, 1048 "could not allocate DMA'able memory for CMB block.\n"); 1049 goto fail; 1050 } 1051 ctx.age_busaddr = 0; 1052 error = bus_dmamap_load(sc->age_cdata.age_cmb_block_tag, 1053 sc->age_cdata.age_cmb_block_map, sc->age_rdata.age_cmb_block, 1054 AGE_CMB_BLOCK_SZ, age_dmamap_cb, &ctx, 0); 1055 if (error != 0 || ctx.age_busaddr == 0) { 1056 device_printf(sc->age_dev, 1057 "could not load DMA'able memory for CMB block.\n"); 1058 goto fail; 1059 } 1060 sc->age_rdata.age_cmb_block_paddr = ctx.age_busaddr; 1061 /* SMB block */ 1062 error = bus_dmamem_alloc(sc->age_cdata.age_smb_block_tag, 1063 (void **)&sc->age_rdata.age_smb_block, 1064 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1065 &sc->age_cdata.age_smb_block_map); 1066 if (error != 0) { 1067 device_printf(sc->age_dev, 1068 "could not allocate DMA'able memory for SMB block.\n"); 1069 goto fail; 1070 } 1071 ctx.age_busaddr = 0; 1072 error = bus_dmamap_load(sc->age_cdata.age_smb_block_tag, 1073 sc->age_cdata.age_smb_block_map, sc->age_rdata.age_smb_block, 1074 AGE_SMB_BLOCK_SZ, age_dmamap_cb, &ctx, 0); 1075 if (error != 0 || ctx.age_busaddr == 0) { 1076 device_printf(sc->age_dev, 1077 "could not load DMA'able memory for SMB block.\n"); 1078 goto fail; 1079 } 1080 sc->age_rdata.age_smb_block_paddr = ctx.age_busaddr; 1081 1082 /* 1083 * All ring buffer and DMA blocks should have the same 1084 * high address part of 64bit DMA address space. 1085 */ 1086 if (lowaddr != BUS_SPACE_MAXADDR_32BIT && 1087 (error = age_check_boundary(sc)) != 0) { 1088 device_printf(sc->age_dev, "4GB boundary crossed, " 1089 "switching to 32bit DMA addressing mode.\n"); 1090 age_dma_free(sc); 1091 /* Limit DMA address space to 32bit and try again. */ 1092 lowaddr = BUS_SPACE_MAXADDR_32BIT; 1093 goto again; 1094 } 1095 1096 /* 1097 * Create Tx/Rx buffer parent tag. 1098 * L1 supports full 64bit DMA addressing in Tx/Rx buffers 1099 * so it needs separate parent DMA tag. 1100 * XXX 1101 * It seems enabling 64bit DMA causes data corruption. Limit 1102 * DMA address space to 32bit. 1103 */ 1104 error = bus_dma_tag_create( 1105 bus_get_dma_tag(sc->age_dev), /* parent */ 1106 1, 0, /* alignment, boundary */ 1107 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 1108 BUS_SPACE_MAXADDR, /* highaddr */ 1109 NULL, NULL, /* filter, filterarg */ 1110 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 1111 0, /* nsegments */ 1112 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 1113 0, /* flags */ 1114 NULL, NULL, /* lockfunc, lockarg */ 1115 &sc->age_cdata.age_buffer_tag); 1116 if (error != 0) { 1117 device_printf(sc->age_dev, 1118 "could not create parent buffer DMA tag.\n"); 1119 goto fail; 1120 } 1121 1122 /* Create tag for Tx buffers. */ 1123 error = bus_dma_tag_create( 1124 sc->age_cdata.age_buffer_tag, /* parent */ 1125 1, 0, /* alignment, boundary */ 1126 BUS_SPACE_MAXADDR, /* lowaddr */ 1127 BUS_SPACE_MAXADDR, /* highaddr */ 1128 NULL, NULL, /* filter, filterarg */ 1129 AGE_TSO_MAXSIZE, /* maxsize */ 1130 AGE_MAXTXSEGS, /* nsegments */ 1131 AGE_TSO_MAXSEGSIZE, /* maxsegsize */ 1132 0, /* flags */ 1133 NULL, NULL, /* lockfunc, lockarg */ 1134 &sc->age_cdata.age_tx_tag); 1135 if (error != 0) { 1136 device_printf(sc->age_dev, "could not create Tx DMA tag.\n"); 1137 goto fail; 1138 } 1139 1140 /* Create tag for Rx buffers. */ 1141 error = bus_dma_tag_create( 1142 sc->age_cdata.age_buffer_tag, /* parent */ 1143 AGE_RX_BUF_ALIGN, 0, /* alignment, boundary */ 1144 BUS_SPACE_MAXADDR, /* lowaddr */ 1145 BUS_SPACE_MAXADDR, /* highaddr */ 1146 NULL, NULL, /* filter, filterarg */ 1147 MCLBYTES, /* maxsize */ 1148 1, /* nsegments */ 1149 MCLBYTES, /* maxsegsize */ 1150 0, /* flags */ 1151 NULL, NULL, /* lockfunc, lockarg */ 1152 &sc->age_cdata.age_rx_tag); 1153 if (error != 0) { 1154 device_printf(sc->age_dev, "could not create Rx DMA tag.\n"); 1155 goto fail; 1156 } 1157 1158 /* Create DMA maps for Tx buffers. */ 1159 for (i = 0; i < AGE_TX_RING_CNT; i++) { 1160 txd = &sc->age_cdata.age_txdesc[i]; 1161 txd->tx_m = NULL; 1162 txd->tx_dmamap = NULL; 1163 error = bus_dmamap_create(sc->age_cdata.age_tx_tag, 0, 1164 &txd->tx_dmamap); 1165 if (error != 0) { 1166 device_printf(sc->age_dev, 1167 "could not create Tx dmamap.\n"); 1168 goto fail; 1169 } 1170 } 1171 /* Create DMA maps for Rx buffers. */ 1172 if ((error = bus_dmamap_create(sc->age_cdata.age_rx_tag, 0, 1173 &sc->age_cdata.age_rx_sparemap)) != 0) { 1174 device_printf(sc->age_dev, 1175 "could not create spare Rx dmamap.\n"); 1176 goto fail; 1177 } 1178 for (i = 0; i < AGE_RX_RING_CNT; i++) { 1179 rxd = &sc->age_cdata.age_rxdesc[i]; 1180 rxd->rx_m = NULL; 1181 rxd->rx_dmamap = NULL; 1182 error = bus_dmamap_create(sc->age_cdata.age_rx_tag, 0, 1183 &rxd->rx_dmamap); 1184 if (error != 0) { 1185 device_printf(sc->age_dev, 1186 "could not create Rx dmamap.\n"); 1187 goto fail; 1188 } 1189 } 1190 1191fail: 1192 return (error); 1193} 1194 1195static void 1196age_dma_free(struct age_softc *sc) 1197{ 1198 struct age_txdesc *txd; 1199 struct age_rxdesc *rxd; 1200 int i; 1201 1202 /* Tx buffers */ 1203 if (sc->age_cdata.age_tx_tag != NULL) { 1204 for (i = 0; i < AGE_TX_RING_CNT; i++) { 1205 txd = &sc->age_cdata.age_txdesc[i]; 1206 if (txd->tx_dmamap != NULL) { 1207 bus_dmamap_destroy(sc->age_cdata.age_tx_tag, 1208 txd->tx_dmamap); 1209 txd->tx_dmamap = NULL; 1210 } 1211 } 1212 bus_dma_tag_destroy(sc->age_cdata.age_tx_tag); 1213 sc->age_cdata.age_tx_tag = NULL; 1214 } 1215 /* Rx buffers */ 1216 if (sc->age_cdata.age_rx_tag != NULL) { 1217 for (i = 0; i < AGE_RX_RING_CNT; i++) { 1218 rxd = &sc->age_cdata.age_rxdesc[i]; 1219 if (rxd->rx_dmamap != NULL) { 1220 bus_dmamap_destroy(sc->age_cdata.age_rx_tag, 1221 rxd->rx_dmamap); 1222 rxd->rx_dmamap = NULL; 1223 } 1224 } 1225 if (sc->age_cdata.age_rx_sparemap != NULL) { 1226 bus_dmamap_destroy(sc->age_cdata.age_rx_tag, 1227 sc->age_cdata.age_rx_sparemap); 1228 sc->age_cdata.age_rx_sparemap = NULL; 1229 } 1230 bus_dma_tag_destroy(sc->age_cdata.age_rx_tag); 1231 sc->age_cdata.age_rx_tag = NULL; 1232 } 1233 /* Tx ring. */ 1234 if (sc->age_cdata.age_tx_ring_tag != NULL) { 1235 if (sc->age_rdata.age_tx_ring_paddr != 0) 1236 bus_dmamap_unload(sc->age_cdata.age_tx_ring_tag, 1237 sc->age_cdata.age_tx_ring_map); 1238 if (sc->age_rdata.age_tx_ring != NULL) 1239 bus_dmamem_free(sc->age_cdata.age_tx_ring_tag, 1240 sc->age_rdata.age_tx_ring, 1241 sc->age_cdata.age_tx_ring_map); 1242 sc->age_rdata.age_tx_ring_paddr = 0; 1243 sc->age_rdata.age_tx_ring = NULL; 1244 bus_dma_tag_destroy(sc->age_cdata.age_tx_ring_tag); 1245 sc->age_cdata.age_tx_ring_tag = NULL; 1246 } 1247 /* Rx ring. */ 1248 if (sc->age_cdata.age_rx_ring_tag != NULL) { 1249 if (sc->age_rdata.age_rx_ring_paddr != 0) 1250 bus_dmamap_unload(sc->age_cdata.age_rx_ring_tag, 1251 sc->age_cdata.age_rx_ring_map); 1252 if (sc->age_rdata.age_rx_ring != NULL) 1253 bus_dmamem_free(sc->age_cdata.age_rx_ring_tag, 1254 sc->age_rdata.age_rx_ring, 1255 sc->age_cdata.age_rx_ring_map); 1256 sc->age_rdata.age_rx_ring_paddr = 0; 1257 sc->age_rdata.age_rx_ring = NULL; 1258 bus_dma_tag_destroy(sc->age_cdata.age_rx_ring_tag); 1259 sc->age_cdata.age_rx_ring_tag = NULL; 1260 } 1261 /* Rx return ring. */ 1262 if (sc->age_cdata.age_rr_ring_tag != NULL) { 1263 if (sc->age_rdata.age_rr_ring_paddr != 0) 1264 bus_dmamap_unload(sc->age_cdata.age_rr_ring_tag, 1265 sc->age_cdata.age_rr_ring_map); 1266 if (sc->age_rdata.age_rr_ring != NULL) 1267 bus_dmamem_free(sc->age_cdata.age_rr_ring_tag, 1268 sc->age_rdata.age_rr_ring, 1269 sc->age_cdata.age_rr_ring_map); 1270 sc->age_rdata.age_rr_ring_paddr = 0; 1271 sc->age_rdata.age_rr_ring = NULL; 1272 bus_dma_tag_destroy(sc->age_cdata.age_rr_ring_tag); 1273 sc->age_cdata.age_rr_ring_tag = NULL; 1274 } 1275 /* CMB block */ 1276 if (sc->age_cdata.age_cmb_block_tag != NULL) { 1277 if (sc->age_rdata.age_cmb_block_paddr != 0) 1278 bus_dmamap_unload(sc->age_cdata.age_cmb_block_tag, 1279 sc->age_cdata.age_cmb_block_map); 1280 if (sc->age_rdata.age_cmb_block != NULL) 1281 bus_dmamem_free(sc->age_cdata.age_cmb_block_tag, 1282 sc->age_rdata.age_cmb_block, 1283 sc->age_cdata.age_cmb_block_map); 1284 sc->age_rdata.age_cmb_block_paddr = 0; 1285 sc->age_rdata.age_cmb_block = NULL; 1286 bus_dma_tag_destroy(sc->age_cdata.age_cmb_block_tag); 1287 sc->age_cdata.age_cmb_block_tag = NULL; 1288 } 1289 /* SMB block */ 1290 if (sc->age_cdata.age_smb_block_tag != NULL) { 1291 if (sc->age_rdata.age_smb_block_paddr != 0) 1292 bus_dmamap_unload(sc->age_cdata.age_smb_block_tag, 1293 sc->age_cdata.age_smb_block_map); 1294 if (sc->age_rdata.age_smb_block != NULL) 1295 bus_dmamem_free(sc->age_cdata.age_smb_block_tag, 1296 sc->age_rdata.age_smb_block, 1297 sc->age_cdata.age_smb_block_map); 1298 sc->age_rdata.age_smb_block_paddr = 0; 1299 sc->age_rdata.age_smb_block = NULL; 1300 bus_dma_tag_destroy(sc->age_cdata.age_smb_block_tag); 1301 sc->age_cdata.age_smb_block_tag = NULL; 1302 } 1303 1304 if (sc->age_cdata.age_buffer_tag != NULL) { 1305 bus_dma_tag_destroy(sc->age_cdata.age_buffer_tag); 1306 sc->age_cdata.age_buffer_tag = NULL; 1307 } 1308 if (sc->age_cdata.age_parent_tag != NULL) { 1309 bus_dma_tag_destroy(sc->age_cdata.age_parent_tag); 1310 sc->age_cdata.age_parent_tag = NULL; 1311 } 1312} 1313 1314/* 1315 * Make sure the interface is stopped at reboot time. 1316 */ 1317static int 1318age_shutdown(device_t dev) 1319{ 1320 1321 return (age_suspend(dev)); 1322} 1323 1324static void 1325age_setwol(struct age_softc *sc) 1326{ 1327 struct ifnet *ifp; 1328 struct mii_data *mii; 1329 uint32_t reg, pmcs; 1330 uint16_t pmstat; 1331 int aneg, i, pmc; 1332 1333 AGE_LOCK_ASSERT(sc); 1334 1335 if (pci_find_cap(sc->age_dev, PCIY_PMG, &pmc) != 0) { 1336 CSR_WRITE_4(sc, AGE_WOL_CFG, 0); 1337 /* 1338 * No PME capability, PHY power down. 1339 * XXX 1340 * Due to an unknown reason powering down PHY resulted 1341 * in unexpected results such as inaccessbility of 1342 * hardware of freshly rebooted system. Disable 1343 * powering down PHY until I got more information for 1344 * Attansic/Atheros PHY hardwares. 1345 */ 1346#ifdef notyet 1347 age_miibus_writereg(sc->age_dev, sc->age_phyaddr, 1348 MII_BMCR, BMCR_PDOWN); 1349#endif 1350 return; 1351 } 1352 1353 ifp = sc->age_ifp; 1354 if ((ifp->if_capenable & IFCAP_WOL) != 0) { 1355 /* 1356 * Note, this driver resets the link speed to 10/100Mbps with 1357 * auto-negotiation but we don't know whether that operation 1358 * would succeed or not as it have no control after powering 1359 * off. If the renegotiation fail WOL may not work. Running 1360 * at 1Gbps will draw more power than 375mA at 3.3V which is 1361 * specified in PCI specification and that would result in 1362 * complete shutdowning power to ethernet controller. 1363 * 1364 * TODO 1365 * Save current negotiated media speed/duplex/flow-control 1366 * to softc and restore the same link again after resuming. 1367 * PHY handling such as power down/resetting to 100Mbps 1368 * may be better handled in suspend method in phy driver. 1369 */ 1370 mii = device_get_softc(sc->age_miibus); 1371 mii_pollstat(mii); 1372 aneg = 0; 1373 if ((mii->mii_media_status & IFM_AVALID) != 0) { 1374 switch IFM_SUBTYPE(mii->mii_media_active) { 1375 case IFM_10_T: 1376 case IFM_100_TX: 1377 goto got_link; 1378 case IFM_1000_T: 1379 aneg++; 1380 default: 1381 break; 1382 } 1383 } 1384 age_miibus_writereg(sc->age_dev, sc->age_phyaddr, 1385 MII_100T2CR, 0); 1386 age_miibus_writereg(sc->age_dev, sc->age_phyaddr, 1387 MII_ANAR, ANAR_TX_FD | ANAR_TX | ANAR_10_FD | 1388 ANAR_10 | ANAR_CSMA); 1389 age_miibus_writereg(sc->age_dev, sc->age_phyaddr, 1390 MII_BMCR, BMCR_RESET | BMCR_AUTOEN | BMCR_STARTNEG); 1391 DELAY(1000); 1392 if (aneg != 0) { 1393 /* Poll link state until age(4) get a 10/100 link. */ 1394 for (i = 0; i < MII_ANEGTICKS_GIGE; i++) { 1395 mii_pollstat(mii); 1396 if ((mii->mii_media_status & IFM_AVALID) != 0) { 1397 switch (IFM_SUBTYPE( 1398 mii->mii_media_active)) { 1399 case IFM_10_T: 1400 case IFM_100_TX: 1401 age_mac_config(sc); 1402 goto got_link; 1403 default: 1404 break; 1405 } 1406 } 1407 AGE_UNLOCK(sc); 1408 pause("agelnk", hz); 1409 AGE_LOCK(sc); 1410 } 1411 if (i == MII_ANEGTICKS_GIGE) 1412 device_printf(sc->age_dev, 1413 "establishing link failed, " 1414 "WOL may not work!"); 1415 } 1416 /* 1417 * No link, force MAC to have 100Mbps, full-duplex link. 1418 * This is the last resort and may/may not work. 1419 */ 1420 mii->mii_media_status = IFM_AVALID | IFM_ACTIVE; 1421 mii->mii_media_active = IFM_ETHER | IFM_100_TX | IFM_FDX; 1422 age_mac_config(sc); 1423 } 1424 1425got_link: 1426 pmcs = 0; 1427 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) 1428 pmcs |= WOL_CFG_MAGIC | WOL_CFG_MAGIC_ENB; 1429 CSR_WRITE_4(sc, AGE_WOL_CFG, pmcs); 1430 reg = CSR_READ_4(sc, AGE_MAC_CFG); 1431 reg &= ~(MAC_CFG_DBG | MAC_CFG_PROMISC); 1432 reg &= ~(MAC_CFG_ALLMULTI | MAC_CFG_BCAST); 1433 if ((ifp->if_capenable & IFCAP_WOL_MCAST) != 0) 1434 reg |= MAC_CFG_ALLMULTI | MAC_CFG_BCAST; 1435 if ((ifp->if_capenable & IFCAP_WOL) != 0) { 1436 reg |= MAC_CFG_RX_ENB; 1437 CSR_WRITE_4(sc, AGE_MAC_CFG, reg); 1438 } 1439 1440 /* Request PME. */ 1441 pmstat = pci_read_config(sc->age_dev, pmc + PCIR_POWER_STATUS, 2); 1442 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); 1443 if ((ifp->if_capenable & IFCAP_WOL) != 0) 1444 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 1445 pci_write_config(sc->age_dev, pmc + PCIR_POWER_STATUS, pmstat, 2); 1446#ifdef notyet 1447 /* See above for powering down PHY issues. */ 1448 if ((ifp->if_capenable & IFCAP_WOL) == 0) { 1449 /* No WOL, PHY power down. */ 1450 age_miibus_writereg(sc->age_dev, sc->age_phyaddr, 1451 MII_BMCR, BMCR_PDOWN); 1452 } 1453#endif 1454} 1455 1456static int 1457age_suspend(device_t dev) 1458{ 1459 struct age_softc *sc; 1460 1461 sc = device_get_softc(dev); 1462 1463 AGE_LOCK(sc); 1464 age_stop(sc); 1465 age_setwol(sc); 1466 AGE_UNLOCK(sc); 1467 1468 return (0); 1469} 1470 1471static int 1472age_resume(device_t dev) 1473{ 1474 struct age_softc *sc; 1475 struct ifnet *ifp; 1476 1477 sc = device_get_softc(dev); 1478 1479 AGE_LOCK(sc); 1480 age_phy_reset(sc); 1481 ifp = sc->age_ifp; 1482 if ((ifp->if_flags & IFF_UP) != 0) 1483 age_init_locked(sc); 1484 1485 AGE_UNLOCK(sc); 1486 1487 return (0); 1488} 1489 1490static int 1491age_encap(struct age_softc *sc, struct mbuf **m_head) 1492{ 1493 struct age_txdesc *txd, *txd_last; 1494 struct tx_desc *desc; 1495 struct mbuf *m; 1496 struct ip *ip; 1497 struct tcphdr *tcp; 1498 bus_dma_segment_t txsegs[AGE_MAXTXSEGS]; 1499 bus_dmamap_t map; 1500 uint32_t cflags, hdrlen, ip_off, poff, vtag; 1501 int error, i, nsegs, prod, si; 1502 1503 AGE_LOCK_ASSERT(sc); 1504 1505 M_ASSERTPKTHDR((*m_head)); 1506 1507 m = *m_head; 1508 ip = NULL; 1509 tcp = NULL; 1510 cflags = vtag = 0; 1511 ip_off = poff = 0; 1512 if ((m->m_pkthdr.csum_flags & (AGE_CSUM_FEATURES | CSUM_TSO)) != 0) { 1513 /* 1514 * L1 requires offset of TCP/UDP payload in its Tx 1515 * descriptor to perform hardware Tx checksum offload. 1516 * Additionally, TSO requires IP/TCP header size and 1517 * modification of IP/TCP header in order to make TSO 1518 * engine work. This kind of operation takes many CPU 1519 * cycles on FreeBSD so fast host CPU is needed to get 1520 * smooth TSO performance. 1521 */ 1522 struct ether_header *eh; 1523 1524 if (M_WRITABLE(m) == 0) { 1525 /* Get a writable copy. */ 1526 m = m_dup(*m_head, M_NOWAIT); 1527 /* Release original mbufs. */ 1528 m_freem(*m_head); 1529 if (m == NULL) { 1530 *m_head = NULL; 1531 return (ENOBUFS); 1532 } 1533 *m_head = m; 1534 } 1535 ip_off = sizeof(struct ether_header); 1536 m = m_pullup(m, ip_off); 1537 if (m == NULL) { 1538 *m_head = NULL; 1539 return (ENOBUFS); 1540 } 1541 eh = mtod(m, struct ether_header *); 1542 /* 1543 * Check if hardware VLAN insertion is off. 1544 * Additional check for LLC/SNAP frame? 1545 */ 1546 if (eh->ether_type == htons(ETHERTYPE_VLAN)) { 1547 ip_off = sizeof(struct ether_vlan_header); 1548 m = m_pullup(m, ip_off); 1549 if (m == NULL) { 1550 *m_head = NULL; 1551 return (ENOBUFS); 1552 } 1553 } 1554 m = m_pullup(m, ip_off + sizeof(struct ip)); 1555 if (m == NULL) { 1556 *m_head = NULL; 1557 return (ENOBUFS); 1558 } 1559 ip = (struct ip *)(mtod(m, char *) + ip_off); 1560 poff = ip_off + (ip->ip_hl << 2); 1561 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 1562 m = m_pullup(m, poff + sizeof(struct tcphdr)); 1563 if (m == NULL) { 1564 *m_head = NULL; 1565 return (ENOBUFS); 1566 } 1567 tcp = (struct tcphdr *)(mtod(m, char *) + poff); 1568 m = m_pullup(m, poff + (tcp->th_off << 2)); 1569 if (m == NULL) { 1570 *m_head = NULL; 1571 return (ENOBUFS); 1572 } 1573 /* 1574 * L1 requires IP/TCP header size and offset as 1575 * well as TCP pseudo checksum which complicates 1576 * TSO configuration. I guess this comes from the 1577 * adherence to Microsoft NDIS Large Send 1578 * specification which requires insertion of 1579 * pseudo checksum by upper stack. The pseudo 1580 * checksum that NDIS refers to doesn't include 1581 * TCP payload length so age(4) should recompute 1582 * the pseudo checksum here. Hopefully this wouldn't 1583 * be much burden on modern CPUs. 1584 * Reset IP checksum and recompute TCP pseudo 1585 * checksum as NDIS specification said. 1586 */ 1587 ip = (struct ip *)(mtod(m, char *) + ip_off); 1588 tcp = (struct tcphdr *)(mtod(m, char *) + poff); 1589 ip->ip_sum = 0; 1590 tcp->th_sum = in_pseudo(ip->ip_src.s_addr, 1591 ip->ip_dst.s_addr, htons(IPPROTO_TCP)); 1592 } 1593 *m_head = m; 1594 } 1595 1596 si = prod = sc->age_cdata.age_tx_prod; 1597 txd = &sc->age_cdata.age_txdesc[prod]; 1598 txd_last = txd; 1599 map = txd->tx_dmamap; 1600 1601 error = bus_dmamap_load_mbuf_sg(sc->age_cdata.age_tx_tag, map, 1602 *m_head, txsegs, &nsegs, 0); 1603 if (error == EFBIG) { 1604 m = m_collapse(*m_head, M_NOWAIT, AGE_MAXTXSEGS); 1605 if (m == NULL) { 1606 m_freem(*m_head); 1607 *m_head = NULL; 1608 return (ENOMEM); 1609 } 1610 *m_head = m; 1611 error = bus_dmamap_load_mbuf_sg(sc->age_cdata.age_tx_tag, map, 1612 *m_head, txsegs, &nsegs, 0); 1613 if (error != 0) { 1614 m_freem(*m_head); 1615 *m_head = NULL; 1616 return (error); 1617 } 1618 } else if (error != 0) 1619 return (error); 1620 if (nsegs == 0) { 1621 m_freem(*m_head); 1622 *m_head = NULL; 1623 return (EIO); 1624 } 1625 1626 /* Check descriptor overrun. */ 1627 if (sc->age_cdata.age_tx_cnt + nsegs >= AGE_TX_RING_CNT - 2) { 1628 bus_dmamap_unload(sc->age_cdata.age_tx_tag, map); 1629 return (ENOBUFS); 1630 } 1631 1632 m = *m_head; 1633 /* Configure VLAN hardware tag insertion. */ 1634 if ((m->m_flags & M_VLANTAG) != 0) { 1635 vtag = AGE_TX_VLAN_TAG(m->m_pkthdr.ether_vtag); 1636 vtag = ((vtag << AGE_TD_VLAN_SHIFT) & AGE_TD_VLAN_MASK); 1637 cflags |= AGE_TD_INSERT_VLAN_TAG; 1638 } 1639 1640 desc = NULL; 1641 i = 0; 1642 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 1643 /* Request TSO and set MSS. */ 1644 cflags |= AGE_TD_TSO_IPV4; 1645 cflags |= AGE_TD_IPCSUM | AGE_TD_TCPCSUM; 1646 cflags |= ((uint32_t)m->m_pkthdr.tso_segsz << 1647 AGE_TD_TSO_MSS_SHIFT); 1648 /* Set IP/TCP header size. */ 1649 cflags |= ip->ip_hl << AGE_TD_IPHDR_LEN_SHIFT; 1650 cflags |= tcp->th_off << AGE_TD_TSO_TCPHDR_LEN_SHIFT; 1651 /* 1652 * L1 requires the first buffer should only hold IP/TCP 1653 * header data. TCP payload should be handled in other 1654 * descriptors. 1655 */ 1656 hdrlen = poff + (tcp->th_off << 2); 1657 desc = &sc->age_rdata.age_tx_ring[prod]; 1658 desc->addr = htole64(txsegs[0].ds_addr); 1659 desc->len = htole32(AGE_TX_BYTES(hdrlen) | vtag); 1660 desc->flags = htole32(cflags); 1661 sc->age_cdata.age_tx_cnt++; 1662 AGE_DESC_INC(prod, AGE_TX_RING_CNT); 1663 if (m->m_len - hdrlen > 0) { 1664 /* Handle remaining payload of the 1st fragment. */ 1665 desc = &sc->age_rdata.age_tx_ring[prod]; 1666 desc->addr = htole64(txsegs[0].ds_addr + hdrlen); 1667 desc->len = htole32(AGE_TX_BYTES(m->m_len - hdrlen) | 1668 vtag); 1669 desc->flags = htole32(cflags); 1670 sc->age_cdata.age_tx_cnt++; 1671 AGE_DESC_INC(prod, AGE_TX_RING_CNT); 1672 } 1673 /* Handle remaining fragments. */ 1674 i = 1; 1675 } else if ((m->m_pkthdr.csum_flags & AGE_CSUM_FEATURES) != 0) { 1676 /* Configure Tx IP/TCP/UDP checksum offload. */ 1677 cflags |= AGE_TD_CSUM; 1678 if ((m->m_pkthdr.csum_flags & CSUM_TCP) != 0) 1679 cflags |= AGE_TD_TCPCSUM; 1680 if ((m->m_pkthdr.csum_flags & CSUM_UDP) != 0) 1681 cflags |= AGE_TD_UDPCSUM; 1682 /* Set checksum start offset. */ 1683 cflags |= (poff << AGE_TD_CSUM_PLOADOFFSET_SHIFT); 1684 /* Set checksum insertion position of TCP/UDP. */ 1685 cflags |= ((poff + m->m_pkthdr.csum_data) << 1686 AGE_TD_CSUM_XSUMOFFSET_SHIFT); 1687 } 1688 for (; i < nsegs; i++) { 1689 desc = &sc->age_rdata.age_tx_ring[prod]; 1690 desc->addr = htole64(txsegs[i].ds_addr); 1691 desc->len = htole32(AGE_TX_BYTES(txsegs[i].ds_len) | vtag); 1692 desc->flags = htole32(cflags); 1693 sc->age_cdata.age_tx_cnt++; 1694 AGE_DESC_INC(prod, AGE_TX_RING_CNT); 1695 } 1696 /* Update producer index. */ 1697 sc->age_cdata.age_tx_prod = prod; 1698 1699 /* Set EOP on the last descriptor. */ 1700 prod = (prod + AGE_TX_RING_CNT - 1) % AGE_TX_RING_CNT; 1701 desc = &sc->age_rdata.age_tx_ring[prod]; 1702 desc->flags |= htole32(AGE_TD_EOP); 1703 1704 /* Lastly set TSO header and modify IP/TCP header for TSO operation. */ 1705 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 1706 desc = &sc->age_rdata.age_tx_ring[si]; 1707 desc->flags |= htole32(AGE_TD_TSO_HDR); 1708 } 1709 1710 /* Swap dmamap of the first and the last. */ 1711 txd = &sc->age_cdata.age_txdesc[prod]; 1712 map = txd_last->tx_dmamap; 1713 txd_last->tx_dmamap = txd->tx_dmamap; 1714 txd->tx_dmamap = map; 1715 txd->tx_m = m; 1716 1717 /* Sync descriptors. */ 1718 bus_dmamap_sync(sc->age_cdata.age_tx_tag, map, BUS_DMASYNC_PREWRITE); 1719 bus_dmamap_sync(sc->age_cdata.age_tx_ring_tag, 1720 sc->age_cdata.age_tx_ring_map, 1721 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1722 1723 return (0); 1724} 1725 1726static void 1727age_start(struct ifnet *ifp) 1728{ 1729 struct age_softc *sc; 1730 1731 sc = ifp->if_softc; 1732 AGE_LOCK(sc); 1733 age_start_locked(ifp); 1734 AGE_UNLOCK(sc); 1735} 1736 1737static void 1738age_start_locked(struct ifnet *ifp) 1739{ 1740 struct age_softc *sc; 1741 struct mbuf *m_head; 1742 int enq; 1743 1744 sc = ifp->if_softc; 1745 1746 AGE_LOCK_ASSERT(sc); 1747 1748 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 1749 IFF_DRV_RUNNING || (sc->age_flags & AGE_FLAG_LINK) == 0) 1750 return; 1751 1752 for (enq = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd); ) { 1753 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 1754 if (m_head == NULL) 1755 break; 1756 /* 1757 * Pack the data into the transmit ring. If we 1758 * don't have room, set the OACTIVE flag and wait 1759 * for the NIC to drain the ring. 1760 */ 1761 if (age_encap(sc, &m_head)) { 1762 if (m_head == NULL) 1763 break; 1764 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 1765 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1766 break; 1767 } 1768 1769 enq++; 1770 /* 1771 * If there's a BPF listener, bounce a copy of this frame 1772 * to him. 1773 */ 1774 ETHER_BPF_MTAP(ifp, m_head); 1775 } 1776 1777 if (enq > 0) { 1778 /* Update mbox. */ 1779 AGE_COMMIT_MBOX(sc); 1780 /* Set a timeout in case the chip goes out to lunch. */ 1781 sc->age_watchdog_timer = AGE_TX_TIMEOUT; 1782 } 1783} 1784 1785static void 1786age_watchdog(struct age_softc *sc) 1787{ 1788 struct ifnet *ifp; 1789 1790 AGE_LOCK_ASSERT(sc); 1791 1792 if (sc->age_watchdog_timer == 0 || --sc->age_watchdog_timer) 1793 return; 1794 1795 ifp = sc->age_ifp; 1796 if ((sc->age_flags & AGE_FLAG_LINK) == 0) { 1797 if_printf(sc->age_ifp, "watchdog timeout (missed link)\n"); 1798 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 1799 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1800 age_init_locked(sc); 1801 return; 1802 } 1803 if (sc->age_cdata.age_tx_cnt == 0) { 1804 if_printf(sc->age_ifp, 1805 "watchdog timeout (missed Tx interrupts) -- recovering\n"); 1806 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1807 age_start_locked(ifp); 1808 return; 1809 } 1810 if_printf(sc->age_ifp, "watchdog timeout\n"); 1811 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 1812 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1813 age_init_locked(sc); 1814 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1815 age_start_locked(ifp); 1816} 1817 1818static int 1819age_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1820{ 1821 struct age_softc *sc; 1822 struct ifreq *ifr; 1823 struct mii_data *mii; 1824 uint32_t reg; 1825 int error, mask; 1826 1827 sc = ifp->if_softc; 1828 ifr = (struct ifreq *)data; 1829 error = 0; 1830 switch (cmd) { 1831 case SIOCSIFMTU: 1832 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > AGE_JUMBO_MTU) 1833 error = EINVAL; 1834 else if (ifp->if_mtu != ifr->ifr_mtu) { 1835 AGE_LOCK(sc); 1836 ifp->if_mtu = ifr->ifr_mtu; 1837 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 1838 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1839 age_init_locked(sc); 1840 } 1841 AGE_UNLOCK(sc); 1842 } 1843 break; 1844 case SIOCSIFFLAGS: 1845 AGE_LOCK(sc); 1846 if ((ifp->if_flags & IFF_UP) != 0) { 1847 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 1848 if (((ifp->if_flags ^ sc->age_if_flags) 1849 & (IFF_PROMISC | IFF_ALLMULTI)) != 0) 1850 age_rxfilter(sc); 1851 } else { 1852 if ((sc->age_flags & AGE_FLAG_DETACH) == 0) 1853 age_init_locked(sc); 1854 } 1855 } else { 1856 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 1857 age_stop(sc); 1858 } 1859 sc->age_if_flags = ifp->if_flags; 1860 AGE_UNLOCK(sc); 1861 break; 1862 case SIOCADDMULTI: 1863 case SIOCDELMULTI: 1864 AGE_LOCK(sc); 1865 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 1866 age_rxfilter(sc); 1867 AGE_UNLOCK(sc); 1868 break; 1869 case SIOCSIFMEDIA: 1870 case SIOCGIFMEDIA: 1871 mii = device_get_softc(sc->age_miibus); 1872 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd); 1873 break; 1874 case SIOCSIFCAP: 1875 AGE_LOCK(sc); 1876 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 1877 if ((mask & IFCAP_TXCSUM) != 0 && 1878 (ifp->if_capabilities & IFCAP_TXCSUM) != 0) { 1879 ifp->if_capenable ^= IFCAP_TXCSUM; 1880 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0) 1881 ifp->if_hwassist |= AGE_CSUM_FEATURES; 1882 else 1883 ifp->if_hwassist &= ~AGE_CSUM_FEATURES; 1884 } 1885 if ((mask & IFCAP_RXCSUM) != 0 && 1886 (ifp->if_capabilities & IFCAP_RXCSUM) != 0) { 1887 ifp->if_capenable ^= IFCAP_RXCSUM; 1888 reg = CSR_READ_4(sc, AGE_MAC_CFG); 1889 reg &= ~MAC_CFG_RXCSUM_ENB; 1890 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) 1891 reg |= MAC_CFG_RXCSUM_ENB; 1892 CSR_WRITE_4(sc, AGE_MAC_CFG, reg); 1893 } 1894 if ((mask & IFCAP_TSO4) != 0 && 1895 (ifp->if_capabilities & IFCAP_TSO4) != 0) { 1896 ifp->if_capenable ^= IFCAP_TSO4; 1897 if ((ifp->if_capenable & IFCAP_TSO4) != 0) 1898 ifp->if_hwassist |= CSUM_TSO; 1899 else 1900 ifp->if_hwassist &= ~CSUM_TSO; 1901 } 1902 1903 if ((mask & IFCAP_WOL_MCAST) != 0 && 1904 (ifp->if_capabilities & IFCAP_WOL_MCAST) != 0) 1905 ifp->if_capenable ^= IFCAP_WOL_MCAST; 1906 if ((mask & IFCAP_WOL_MAGIC) != 0 && 1907 (ifp->if_capabilities & IFCAP_WOL_MAGIC) != 0) 1908 ifp->if_capenable ^= IFCAP_WOL_MAGIC; 1909 if ((mask & IFCAP_VLAN_HWCSUM) != 0 && 1910 (ifp->if_capabilities & IFCAP_VLAN_HWCSUM) != 0) 1911 ifp->if_capenable ^= IFCAP_VLAN_HWCSUM; 1912 if ((mask & IFCAP_VLAN_HWTSO) != 0 && 1913 (ifp->if_capabilities & IFCAP_VLAN_HWTSO) != 0) 1914 ifp->if_capenable ^= IFCAP_VLAN_HWTSO; 1915 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 && 1916 (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) != 0) { 1917 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 1918 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) == 0) 1919 ifp->if_capenable &= ~IFCAP_VLAN_HWTSO; 1920 age_rxvlan(sc); 1921 } 1922 AGE_UNLOCK(sc); 1923 VLAN_CAPABILITIES(ifp); 1924 break; 1925 default: 1926 error = ether_ioctl(ifp, cmd, data); 1927 break; 1928 } 1929 1930 return (error); 1931} 1932 1933static void 1934age_mac_config(struct age_softc *sc) 1935{ 1936 struct mii_data *mii; 1937 uint32_t reg; 1938 1939 AGE_LOCK_ASSERT(sc); 1940 1941 mii = device_get_softc(sc->age_miibus); 1942 reg = CSR_READ_4(sc, AGE_MAC_CFG); 1943 reg &= ~MAC_CFG_FULL_DUPLEX; 1944 reg &= ~(MAC_CFG_TX_FC | MAC_CFG_RX_FC); 1945 reg &= ~MAC_CFG_SPEED_MASK; 1946 /* Reprogram MAC with resolved speed/duplex. */ 1947 switch (IFM_SUBTYPE(mii->mii_media_active)) { 1948 case IFM_10_T: 1949 case IFM_100_TX: 1950 reg |= MAC_CFG_SPEED_10_100; 1951 break; 1952 case IFM_1000_T: 1953 reg |= MAC_CFG_SPEED_1000; 1954 break; 1955 } 1956 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 1957 reg |= MAC_CFG_FULL_DUPLEX; 1958#ifdef notyet 1959 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0) 1960 reg |= MAC_CFG_TX_FC; 1961 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0) 1962 reg |= MAC_CFG_RX_FC; 1963#endif 1964 } 1965 1966 CSR_WRITE_4(sc, AGE_MAC_CFG, reg); 1967} 1968 1969static void 1970age_link_task(void *arg, int pending) 1971{ 1972 struct age_softc *sc; 1973 struct mii_data *mii; 1974 struct ifnet *ifp; 1975 uint32_t reg; 1976 1977 sc = (struct age_softc *)arg; 1978 1979 AGE_LOCK(sc); 1980 mii = device_get_softc(sc->age_miibus); 1981 ifp = sc->age_ifp; 1982 if (mii == NULL || ifp == NULL || 1983 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 1984 AGE_UNLOCK(sc); 1985 return; 1986 } 1987 1988 sc->age_flags &= ~AGE_FLAG_LINK; 1989 if ((mii->mii_media_status & IFM_AVALID) != 0) { 1990 switch (IFM_SUBTYPE(mii->mii_media_active)) { 1991 case IFM_10_T: 1992 case IFM_100_TX: 1993 case IFM_1000_T: 1994 sc->age_flags |= AGE_FLAG_LINK; 1995 break; 1996 default: 1997 break; 1998 } 1999 } 2000 2001 /* Stop Rx/Tx MACs. */ 2002 age_stop_rxmac(sc); 2003 age_stop_txmac(sc); 2004 2005 /* Program MACs with resolved speed/duplex/flow-control. */ 2006 if ((sc->age_flags & AGE_FLAG_LINK) != 0) { 2007 age_mac_config(sc); 2008 reg = CSR_READ_4(sc, AGE_MAC_CFG); 2009 /* Restart DMA engine and Tx/Rx MAC. */ 2010 CSR_WRITE_4(sc, AGE_DMA_CFG, CSR_READ_4(sc, AGE_DMA_CFG) | 2011 DMA_CFG_RD_ENB | DMA_CFG_WR_ENB); 2012 reg |= MAC_CFG_TX_ENB | MAC_CFG_RX_ENB; 2013 CSR_WRITE_4(sc, AGE_MAC_CFG, reg); 2014 } 2015 2016 AGE_UNLOCK(sc); 2017} 2018 2019static void 2020age_stats_update(struct age_softc *sc) 2021{ 2022 struct age_stats *stat; 2023 struct smb *smb; 2024 struct ifnet *ifp; 2025 2026 AGE_LOCK_ASSERT(sc); 2027 2028 stat = &sc->age_stat; 2029 2030 bus_dmamap_sync(sc->age_cdata.age_smb_block_tag, 2031 sc->age_cdata.age_smb_block_map, 2032 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2033 2034 smb = sc->age_rdata.age_smb_block; 2035 if (smb->updated == 0) 2036 return; 2037 2038 ifp = sc->age_ifp; 2039 /* Rx stats. */ 2040 stat->rx_frames += smb->rx_frames; 2041 stat->rx_bcast_frames += smb->rx_bcast_frames; 2042 stat->rx_mcast_frames += smb->rx_mcast_frames; 2043 stat->rx_pause_frames += smb->rx_pause_frames; 2044 stat->rx_control_frames += smb->rx_control_frames; 2045 stat->rx_crcerrs += smb->rx_crcerrs; 2046 stat->rx_lenerrs += smb->rx_lenerrs; 2047 stat->rx_bytes += smb->rx_bytes; 2048 stat->rx_runts += smb->rx_runts; 2049 stat->rx_fragments += smb->rx_fragments; 2050 stat->rx_pkts_64 += smb->rx_pkts_64; 2051 stat->rx_pkts_65_127 += smb->rx_pkts_65_127; 2052 stat->rx_pkts_128_255 += smb->rx_pkts_128_255; 2053 stat->rx_pkts_256_511 += smb->rx_pkts_256_511; 2054 stat->rx_pkts_512_1023 += smb->rx_pkts_512_1023; 2055 stat->rx_pkts_1024_1518 += smb->rx_pkts_1024_1518; 2056 stat->rx_pkts_1519_max += smb->rx_pkts_1519_max; 2057 stat->rx_pkts_truncated += smb->rx_pkts_truncated; 2058 stat->rx_fifo_oflows += smb->rx_fifo_oflows; 2059 stat->rx_desc_oflows += smb->rx_desc_oflows; 2060 stat->rx_alignerrs += smb->rx_alignerrs; 2061 stat->rx_bcast_bytes += smb->rx_bcast_bytes; 2062 stat->rx_mcast_bytes += smb->rx_mcast_bytes; 2063 stat->rx_pkts_filtered += smb->rx_pkts_filtered; 2064 2065 /* Tx stats. */ 2066 stat->tx_frames += smb->tx_frames; 2067 stat->tx_bcast_frames += smb->tx_bcast_frames; 2068 stat->tx_mcast_frames += smb->tx_mcast_frames; 2069 stat->tx_pause_frames += smb->tx_pause_frames; 2070 stat->tx_excess_defer += smb->tx_excess_defer; 2071 stat->tx_control_frames += smb->tx_control_frames; 2072 stat->tx_deferred += smb->tx_deferred; 2073 stat->tx_bytes += smb->tx_bytes; 2074 stat->tx_pkts_64 += smb->tx_pkts_64; 2075 stat->tx_pkts_65_127 += smb->tx_pkts_65_127; 2076 stat->tx_pkts_128_255 += smb->tx_pkts_128_255; 2077 stat->tx_pkts_256_511 += smb->tx_pkts_256_511; 2078 stat->tx_pkts_512_1023 += smb->tx_pkts_512_1023; 2079 stat->tx_pkts_1024_1518 += smb->tx_pkts_1024_1518; 2080 stat->tx_pkts_1519_max += smb->tx_pkts_1519_max; 2081 stat->tx_single_colls += smb->tx_single_colls; 2082 stat->tx_multi_colls += smb->tx_multi_colls; 2083 stat->tx_late_colls += smb->tx_late_colls; 2084 stat->tx_excess_colls += smb->tx_excess_colls; 2085 stat->tx_underrun += smb->tx_underrun; 2086 stat->tx_desc_underrun += smb->tx_desc_underrun; 2087 stat->tx_lenerrs += smb->tx_lenerrs; 2088 stat->tx_pkts_truncated += smb->tx_pkts_truncated; 2089 stat->tx_bcast_bytes += smb->tx_bcast_bytes; 2090 stat->tx_mcast_bytes += smb->tx_mcast_bytes; 2091 2092 /* Update counters in ifnet. */ 2093 if_inc_counter(ifp, IFCOUNTER_OPACKETS, smb->tx_frames); 2094 2095 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, smb->tx_single_colls + 2096 smb->tx_multi_colls + smb->tx_late_colls + 2097 smb->tx_excess_colls * HDPX_CFG_RETRY_DEFAULT); 2098 2099 if_inc_counter(ifp, IFCOUNTER_OERRORS, smb->tx_excess_colls + 2100 smb->tx_late_colls + smb->tx_underrun + 2101 smb->tx_pkts_truncated); 2102 2103 if_inc_counter(ifp, IFCOUNTER_IPACKETS, smb->rx_frames); 2104 2105 if_inc_counter(ifp, IFCOUNTER_IERRORS, smb->rx_crcerrs + 2106 smb->rx_lenerrs + smb->rx_runts + smb->rx_pkts_truncated + 2107 smb->rx_fifo_oflows + smb->rx_desc_oflows + 2108 smb->rx_alignerrs); 2109 2110 /* Update done, clear. */ 2111 smb->updated = 0; 2112 2113 bus_dmamap_sync(sc->age_cdata.age_smb_block_tag, 2114 sc->age_cdata.age_smb_block_map, 2115 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2116} 2117 2118static int 2119age_intr(void *arg) 2120{ 2121 struct age_softc *sc; 2122 uint32_t status; 2123 2124 sc = (struct age_softc *)arg; 2125 2126 status = CSR_READ_4(sc, AGE_INTR_STATUS); 2127 if (status == 0 || (status & AGE_INTRS) == 0) 2128 return (FILTER_STRAY); 2129 /* Disable interrupts. */ 2130 CSR_WRITE_4(sc, AGE_INTR_STATUS, status | INTR_DIS_INT); 2131 taskqueue_enqueue(sc->age_tq, &sc->age_int_task); 2132 2133 return (FILTER_HANDLED); 2134} 2135 2136static void 2137age_int_task(void *arg, int pending) 2138{ 2139 struct age_softc *sc; 2140 struct ifnet *ifp; 2141 struct cmb *cmb; 2142 uint32_t status; 2143 2144 sc = (struct age_softc *)arg; 2145 2146 AGE_LOCK(sc); 2147 2148 bus_dmamap_sync(sc->age_cdata.age_cmb_block_tag, 2149 sc->age_cdata.age_cmb_block_map, 2150 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2151 cmb = sc->age_rdata.age_cmb_block; 2152 status = le32toh(cmb->intr_status); 2153 if (sc->age_morework != 0) 2154 status |= INTR_CMB_RX; 2155 if ((status & AGE_INTRS) == 0) 2156 goto done; 2157 2158 sc->age_tpd_cons = (le32toh(cmb->tpd_cons) & TPD_CONS_MASK) >> 2159 TPD_CONS_SHIFT; 2160 sc->age_rr_prod = (le32toh(cmb->rprod_cons) & RRD_PROD_MASK) >> 2161 RRD_PROD_SHIFT; 2162 /* Let hardware know CMB was served. */ 2163 cmb->intr_status = 0; 2164 bus_dmamap_sync(sc->age_cdata.age_cmb_block_tag, 2165 sc->age_cdata.age_cmb_block_map, 2166 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2167 2168 ifp = sc->age_ifp; 2169 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 2170 if ((status & INTR_CMB_RX) != 0) 2171 sc->age_morework = age_rxintr(sc, sc->age_rr_prod, 2172 sc->age_process_limit); 2173 if ((status & INTR_CMB_TX) != 0) 2174 age_txintr(sc, sc->age_tpd_cons); 2175 if ((status & (INTR_DMA_RD_TO_RST | INTR_DMA_WR_TO_RST)) != 0) { 2176 if ((status & INTR_DMA_RD_TO_RST) != 0) 2177 device_printf(sc->age_dev, 2178 "DMA read error! -- resetting\n"); 2179 if ((status & INTR_DMA_WR_TO_RST) != 0) 2180 device_printf(sc->age_dev, 2181 "DMA write error! -- resetting\n"); 2182 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2183 age_init_locked(sc); 2184 } 2185 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2186 age_start_locked(ifp); 2187 if ((status & INTR_SMB) != 0) 2188 age_stats_update(sc); 2189 } 2190 2191 /* Check whether CMB was updated while serving Tx/Rx/SMB handler. */ 2192 bus_dmamap_sync(sc->age_cdata.age_cmb_block_tag, 2193 sc->age_cdata.age_cmb_block_map, 2194 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2195 status = le32toh(cmb->intr_status); 2196 if (sc->age_morework != 0 || (status & AGE_INTRS) != 0) { 2197 taskqueue_enqueue(sc->age_tq, &sc->age_int_task); 2198 AGE_UNLOCK(sc); 2199 return; 2200 } 2201 2202done: 2203 /* Re-enable interrupts. */ 2204 CSR_WRITE_4(sc, AGE_INTR_STATUS, 0); 2205 AGE_UNLOCK(sc); 2206} 2207 2208static void 2209age_txintr(struct age_softc *sc, int tpd_cons) 2210{ 2211 struct ifnet *ifp; 2212 struct age_txdesc *txd; 2213 int cons, prog; 2214 2215 AGE_LOCK_ASSERT(sc); 2216 2217 ifp = sc->age_ifp; 2218 2219 bus_dmamap_sync(sc->age_cdata.age_tx_ring_tag, 2220 sc->age_cdata.age_tx_ring_map, 2221 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2222 2223 /* 2224 * Go through our Tx list and free mbufs for those 2225 * frames which have been transmitted. 2226 */ 2227 cons = sc->age_cdata.age_tx_cons; 2228 for (prog = 0; cons != tpd_cons; AGE_DESC_INC(cons, AGE_TX_RING_CNT)) { 2229 if (sc->age_cdata.age_tx_cnt <= 0) 2230 break; 2231 prog++; 2232 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2233 sc->age_cdata.age_tx_cnt--; 2234 txd = &sc->age_cdata.age_txdesc[cons]; 2235 /* 2236 * Clear Tx descriptors, it's not required but would 2237 * help debugging in case of Tx issues. 2238 */ 2239 txd->tx_desc->addr = 0; 2240 txd->tx_desc->len = 0; 2241 txd->tx_desc->flags = 0; 2242 2243 if (txd->tx_m == NULL) 2244 continue; 2245 /* Reclaim transmitted mbufs. */ 2246 bus_dmamap_sync(sc->age_cdata.age_tx_tag, txd->tx_dmamap, 2247 BUS_DMASYNC_POSTWRITE); 2248 bus_dmamap_unload(sc->age_cdata.age_tx_tag, txd->tx_dmamap); 2249 m_freem(txd->tx_m); 2250 txd->tx_m = NULL; 2251 } 2252 2253 if (prog > 0) { 2254 sc->age_cdata.age_tx_cons = cons; 2255 2256 /* 2257 * Unarm watchdog timer only when there are no pending 2258 * Tx descriptors in queue. 2259 */ 2260 if (sc->age_cdata.age_tx_cnt == 0) 2261 sc->age_watchdog_timer = 0; 2262 bus_dmamap_sync(sc->age_cdata.age_tx_ring_tag, 2263 sc->age_cdata.age_tx_ring_map, 2264 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2265 } 2266} 2267 2268#ifndef __NO_STRICT_ALIGNMENT 2269static struct mbuf * 2270age_fixup_rx(struct ifnet *ifp, struct mbuf *m) 2271{ 2272 struct mbuf *n; 2273 int i; 2274 uint16_t *src, *dst; 2275 2276 src = mtod(m, uint16_t *); 2277 dst = src - 3; 2278 2279 if (m->m_next == NULL) { 2280 for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++) 2281 *dst++ = *src++; 2282 m->m_data -= 6; 2283 return (m); 2284 } 2285 /* 2286 * Append a new mbuf to received mbuf chain and copy ethernet 2287 * header from the mbuf chain. This can save lots of CPU 2288 * cycles for jumbo frame. 2289 */ 2290 MGETHDR(n, M_NOWAIT, MT_DATA); 2291 if (n == NULL) { 2292 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1); 2293 m_freem(m); 2294 return (NULL); 2295 } 2296 bcopy(m->m_data, n->m_data, ETHER_HDR_LEN); 2297 m->m_data += ETHER_HDR_LEN; 2298 m->m_len -= ETHER_HDR_LEN; 2299 n->m_len = ETHER_HDR_LEN; 2300 M_MOVE_PKTHDR(n, m); 2301 n->m_next = m; 2302 return (n); 2303} 2304#endif 2305 2306/* Receive a frame. */ 2307static void 2308age_rxeof(struct age_softc *sc, struct rx_rdesc *rxrd) 2309{ 2310 struct age_rxdesc *rxd; 2311 struct ifnet *ifp; 2312 struct mbuf *mp, *m; 2313 uint32_t status, index, vtag; 2314 int count, nsegs; 2315 int rx_cons; 2316 2317 AGE_LOCK_ASSERT(sc); 2318 2319 ifp = sc->age_ifp; 2320 status = le32toh(rxrd->flags); 2321 index = le32toh(rxrd->index); 2322 rx_cons = AGE_RX_CONS(index); 2323 nsegs = AGE_RX_NSEGS(index); 2324 2325 sc->age_cdata.age_rxlen = AGE_RX_BYTES(le32toh(rxrd->len)); 2326 if ((status & (AGE_RRD_ERROR | AGE_RRD_LENGTH_NOK)) != 0) { 2327 /* 2328 * We want to pass the following frames to upper 2329 * layer regardless of error status of Rx return 2330 * ring. 2331 * 2332 * o IP/TCP/UDP checksum is bad. 2333 * o frame length and protocol specific length 2334 * does not match. 2335 */ 2336 status |= AGE_RRD_IPCSUM_NOK | AGE_RRD_TCP_UDPCSUM_NOK; 2337 if ((status & (AGE_RRD_CRC | AGE_RRD_CODE | AGE_RRD_DRIBBLE | 2338 AGE_RRD_RUNT | AGE_RRD_OFLOW | AGE_RRD_TRUNC)) != 0) 2339 return; 2340 } 2341 2342 for (count = 0; count < nsegs; count++, 2343 AGE_DESC_INC(rx_cons, AGE_RX_RING_CNT)) { 2344 rxd = &sc->age_cdata.age_rxdesc[rx_cons]; 2345 mp = rxd->rx_m; 2346 /* Add a new receive buffer to the ring. */ 2347 if (age_newbuf(sc, rxd) != 0) { 2348 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1); 2349 /* Reuse Rx buffers. */ 2350 if (sc->age_cdata.age_rxhead != NULL) 2351 m_freem(sc->age_cdata.age_rxhead); 2352 break; 2353 } 2354 2355 /* 2356 * Assume we've received a full sized frame. 2357 * Actual size is fixed when we encounter the end of 2358 * multi-segmented frame. 2359 */ 2360 mp->m_len = AGE_RX_BUF_SIZE; 2361 2362 /* Chain received mbufs. */ 2363 if (sc->age_cdata.age_rxhead == NULL) { 2364 sc->age_cdata.age_rxhead = mp; 2365 sc->age_cdata.age_rxtail = mp; 2366 } else { 2367 mp->m_flags &= ~M_PKTHDR; 2368 sc->age_cdata.age_rxprev_tail = 2369 sc->age_cdata.age_rxtail; 2370 sc->age_cdata.age_rxtail->m_next = mp; 2371 sc->age_cdata.age_rxtail = mp; 2372 } 2373 2374 if (count == nsegs - 1) { 2375 /* Last desc. for this frame. */ 2376 m = sc->age_cdata.age_rxhead; 2377 m->m_flags |= M_PKTHDR; 2378 /* 2379 * It seems that L1 controller has no way 2380 * to tell hardware to strip CRC bytes. 2381 */ 2382 m->m_pkthdr.len = sc->age_cdata.age_rxlen - 2383 ETHER_CRC_LEN; 2384 if (nsegs > 1) { 2385 /* Set last mbuf size. */ 2386 mp->m_len = sc->age_cdata.age_rxlen - 2387 ((nsegs - 1) * AGE_RX_BUF_SIZE); 2388 /* Remove the CRC bytes in chained mbufs. */ 2389 if (mp->m_len <= ETHER_CRC_LEN) { 2390 sc->age_cdata.age_rxtail = 2391 sc->age_cdata.age_rxprev_tail; 2392 sc->age_cdata.age_rxtail->m_len -= 2393 (ETHER_CRC_LEN - mp->m_len); 2394 sc->age_cdata.age_rxtail->m_next = NULL; 2395 m_freem(mp); 2396 } else { 2397 mp->m_len -= ETHER_CRC_LEN; 2398 } 2399 } else 2400 m->m_len = m->m_pkthdr.len; 2401 m->m_pkthdr.rcvif = ifp; 2402 /* 2403 * Set checksum information. 2404 * It seems that L1 controller can compute partial 2405 * checksum. The partial checksum value can be used 2406 * to accelerate checksum computation for fragmented 2407 * TCP/UDP packets. Upper network stack already 2408 * takes advantage of the partial checksum value in 2409 * IP reassembly stage. But I'm not sure the 2410 * correctness of the partial hardware checksum 2411 * assistance due to lack of data sheet. If it is 2412 * proven to work on L1 I'll enable it. 2413 */ 2414 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0 && 2415 (status & AGE_RRD_IPV4) != 0) { 2416 if ((status & AGE_RRD_IPCSUM_NOK) == 0) 2417 m->m_pkthdr.csum_flags |= 2418 CSUM_IP_CHECKED | CSUM_IP_VALID; 2419 if ((status & (AGE_RRD_TCP | AGE_RRD_UDP)) && 2420 (status & AGE_RRD_TCP_UDPCSUM_NOK) == 0) { 2421 m->m_pkthdr.csum_flags |= 2422 CSUM_DATA_VALID | CSUM_PSEUDO_HDR; 2423 m->m_pkthdr.csum_data = 0xffff; 2424 } 2425 /* 2426 * Don't mark bad checksum for TCP/UDP frames 2427 * as fragmented frames may always have set 2428 * bad checksummed bit of descriptor status. 2429 */ 2430 } 2431 2432 /* Check for VLAN tagged frames. */ 2433 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0 && 2434 (status & AGE_RRD_VLAN) != 0) { 2435 vtag = AGE_RX_VLAN(le32toh(rxrd->vtags)); 2436 m->m_pkthdr.ether_vtag = AGE_RX_VLAN_TAG(vtag); 2437 m->m_flags |= M_VLANTAG; 2438 } 2439#ifndef __NO_STRICT_ALIGNMENT 2440 m = age_fixup_rx(ifp, m); 2441 if (m != NULL) 2442#endif 2443 { 2444 /* Pass it on. */ 2445 AGE_UNLOCK(sc); 2446 (*ifp->if_input)(ifp, m); 2447 AGE_LOCK(sc); 2448 } 2449 } 2450 } 2451 2452 /* Reset mbuf chains. */ 2453 AGE_RXCHAIN_RESET(sc); 2454} 2455 2456static int 2457age_rxintr(struct age_softc *sc, int rr_prod, int count) 2458{ 2459 struct rx_rdesc *rxrd; 2460 int rr_cons, nsegs, pktlen, prog; 2461 2462 AGE_LOCK_ASSERT(sc); 2463 2464 rr_cons = sc->age_cdata.age_rr_cons; 2465 if (rr_cons == rr_prod) 2466 return (0); 2467 2468 bus_dmamap_sync(sc->age_cdata.age_rr_ring_tag, 2469 sc->age_cdata.age_rr_ring_map, 2470 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2471 bus_dmamap_sync(sc->age_cdata.age_rx_ring_tag, 2472 sc->age_cdata.age_rx_ring_map, BUS_DMASYNC_POSTWRITE); 2473 2474 for (prog = 0; rr_cons != rr_prod; prog++) { 2475 if (count-- <= 0) 2476 break; 2477 rxrd = &sc->age_rdata.age_rr_ring[rr_cons]; 2478 nsegs = AGE_RX_NSEGS(le32toh(rxrd->index)); 2479 if (nsegs == 0) 2480 break; 2481 /* 2482 * Check number of segments against received bytes. 2483 * Non-matching value would indicate that hardware 2484 * is still trying to update Rx return descriptors. 2485 * I'm not sure whether this check is really needed. 2486 */ 2487 pktlen = AGE_RX_BYTES(le32toh(rxrd->len)); 2488 if (nsegs != howmany(pktlen, AGE_RX_BUF_SIZE)) 2489 break; 2490 2491 /* Received a frame. */ 2492 age_rxeof(sc, rxrd); 2493 /* Clear return ring. */ 2494 rxrd->index = 0; 2495 AGE_DESC_INC(rr_cons, AGE_RR_RING_CNT); 2496 sc->age_cdata.age_rx_cons += nsegs; 2497 sc->age_cdata.age_rx_cons %= AGE_RX_RING_CNT; 2498 } 2499 2500 if (prog > 0) { 2501 /* Update the consumer index. */ 2502 sc->age_cdata.age_rr_cons = rr_cons; 2503 2504 bus_dmamap_sync(sc->age_cdata.age_rx_ring_tag, 2505 sc->age_cdata.age_rx_ring_map, BUS_DMASYNC_PREWRITE); 2506 /* Sync descriptors. */ 2507 bus_dmamap_sync(sc->age_cdata.age_rr_ring_tag, 2508 sc->age_cdata.age_rr_ring_map, 2509 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2510 2511 /* Notify hardware availability of new Rx buffers. */ 2512 AGE_COMMIT_MBOX(sc); 2513 } 2514 2515 return (count > 0 ? 0 : EAGAIN); 2516} 2517 2518static void 2519age_tick(void *arg) 2520{ 2521 struct age_softc *sc; 2522 struct mii_data *mii; 2523 2524 sc = (struct age_softc *)arg; 2525 2526 AGE_LOCK_ASSERT(sc); 2527 2528 mii = device_get_softc(sc->age_miibus); 2529 mii_tick(mii); 2530 age_watchdog(sc); 2531 callout_reset(&sc->age_tick_ch, hz, age_tick, sc); 2532} 2533 2534static void 2535age_reset(struct age_softc *sc) 2536{ 2537 uint32_t reg; 2538 int i; 2539 2540 CSR_WRITE_4(sc, AGE_MASTER_CFG, MASTER_RESET); 2541 CSR_READ_4(sc, AGE_MASTER_CFG); 2542 DELAY(1000); 2543 for (i = AGE_RESET_TIMEOUT; i > 0; i--) { 2544 if ((reg = CSR_READ_4(sc, AGE_IDLE_STATUS)) == 0) 2545 break; 2546 DELAY(10); 2547 } 2548 2549 if (i == 0) 2550 device_printf(sc->age_dev, "reset timeout(0x%08x)!\n", reg); 2551 /* Initialize PCIe module. From Linux. */ 2552 CSR_WRITE_4(sc, 0x12FC, 0x6500); 2553 CSR_WRITE_4(sc, 0x1008, CSR_READ_4(sc, 0x1008) | 0x8000); 2554} 2555 2556static void 2557age_init(void *xsc) 2558{ 2559 struct age_softc *sc; 2560 2561 sc = (struct age_softc *)xsc; 2562 AGE_LOCK(sc); 2563 age_init_locked(sc); 2564 AGE_UNLOCK(sc); 2565} 2566 2567static void 2568age_init_locked(struct age_softc *sc) 2569{ 2570 struct ifnet *ifp; 2571 struct mii_data *mii; 2572 uint8_t eaddr[ETHER_ADDR_LEN]; 2573 bus_addr_t paddr; 2574 uint32_t reg, fsize; 2575 uint32_t rxf_hi, rxf_lo, rrd_hi, rrd_lo; 2576 int error; 2577 2578 AGE_LOCK_ASSERT(sc); 2579 2580 ifp = sc->age_ifp; 2581 mii = device_get_softc(sc->age_miibus); 2582 2583 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 2584 return; 2585 2586 /* 2587 * Cancel any pending I/O. 2588 */ 2589 age_stop(sc); 2590 2591 /* 2592 * Reset the chip to a known state. 2593 */ 2594 age_reset(sc); 2595 2596 /* Initialize descriptors. */ 2597 error = age_init_rx_ring(sc); 2598 if (error != 0) { 2599 device_printf(sc->age_dev, "no memory for Rx buffers.\n"); 2600 age_stop(sc); 2601 return; 2602 } 2603 age_init_rr_ring(sc); 2604 age_init_tx_ring(sc); 2605 age_init_cmb_block(sc); 2606 age_init_smb_block(sc); 2607 2608 /* Reprogram the station address. */ 2609 bcopy(IF_LLADDR(ifp), eaddr, ETHER_ADDR_LEN); 2610 CSR_WRITE_4(sc, AGE_PAR0, 2611 eaddr[2] << 24 | eaddr[3] << 16 | eaddr[4] << 8 | eaddr[5]); 2612 CSR_WRITE_4(sc, AGE_PAR1, eaddr[0] << 8 | eaddr[1]); 2613 2614 /* Set descriptor base addresses. */ 2615 paddr = sc->age_rdata.age_tx_ring_paddr; 2616 CSR_WRITE_4(sc, AGE_DESC_ADDR_HI, AGE_ADDR_HI(paddr)); 2617 paddr = sc->age_rdata.age_rx_ring_paddr; 2618 CSR_WRITE_4(sc, AGE_DESC_RD_ADDR_LO, AGE_ADDR_LO(paddr)); 2619 paddr = sc->age_rdata.age_rr_ring_paddr; 2620 CSR_WRITE_4(sc, AGE_DESC_RRD_ADDR_LO, AGE_ADDR_LO(paddr)); 2621 paddr = sc->age_rdata.age_tx_ring_paddr; 2622 CSR_WRITE_4(sc, AGE_DESC_TPD_ADDR_LO, AGE_ADDR_LO(paddr)); 2623 paddr = sc->age_rdata.age_cmb_block_paddr; 2624 CSR_WRITE_4(sc, AGE_DESC_CMB_ADDR_LO, AGE_ADDR_LO(paddr)); 2625 paddr = sc->age_rdata.age_smb_block_paddr; 2626 CSR_WRITE_4(sc, AGE_DESC_SMB_ADDR_LO, AGE_ADDR_LO(paddr)); 2627 /* Set Rx/Rx return descriptor counter. */ 2628 CSR_WRITE_4(sc, AGE_DESC_RRD_RD_CNT, 2629 ((AGE_RR_RING_CNT << DESC_RRD_CNT_SHIFT) & 2630 DESC_RRD_CNT_MASK) | 2631 ((AGE_RX_RING_CNT << DESC_RD_CNT_SHIFT) & DESC_RD_CNT_MASK)); 2632 /* Set Tx descriptor counter. */ 2633 CSR_WRITE_4(sc, AGE_DESC_TPD_CNT, 2634 (AGE_TX_RING_CNT << DESC_TPD_CNT_SHIFT) & DESC_TPD_CNT_MASK); 2635 2636 /* Tell hardware that we're ready to load descriptors. */ 2637 CSR_WRITE_4(sc, AGE_DMA_BLOCK, DMA_BLOCK_LOAD); 2638 2639 /* 2640 * Initialize mailbox register. 2641 * Updated producer/consumer index information is exchanged 2642 * through this mailbox register. However Tx producer and 2643 * Rx return consumer/Rx producer are all shared such that 2644 * it's hard to separate code path between Tx and Rx without 2645 * locking. If L1 hardware have a separate mail box register 2646 * for Tx and Rx consumer/producer management we could have 2647 * indepent Tx/Rx handler which in turn Rx handler could have 2648 * been run without any locking. 2649 */ 2650 AGE_COMMIT_MBOX(sc); 2651 2652 /* Configure IPG/IFG parameters. */ 2653 CSR_WRITE_4(sc, AGE_IPG_IFG_CFG, 2654 ((IPG_IFG_IPG2_DEFAULT << IPG_IFG_IPG2_SHIFT) & IPG_IFG_IPG2_MASK) | 2655 ((IPG_IFG_IPG1_DEFAULT << IPG_IFG_IPG1_SHIFT) & IPG_IFG_IPG1_MASK) | 2656 ((IPG_IFG_MIFG_DEFAULT << IPG_IFG_MIFG_SHIFT) & IPG_IFG_MIFG_MASK) | 2657 ((IPG_IFG_IPGT_DEFAULT << IPG_IFG_IPGT_SHIFT) & IPG_IFG_IPGT_MASK)); 2658 2659 /* Set parameters for half-duplex media. */ 2660 CSR_WRITE_4(sc, AGE_HDPX_CFG, 2661 ((HDPX_CFG_LCOL_DEFAULT << HDPX_CFG_LCOL_SHIFT) & 2662 HDPX_CFG_LCOL_MASK) | 2663 ((HDPX_CFG_RETRY_DEFAULT << HDPX_CFG_RETRY_SHIFT) & 2664 HDPX_CFG_RETRY_MASK) | HDPX_CFG_EXC_DEF_EN | 2665 ((HDPX_CFG_ABEBT_DEFAULT << HDPX_CFG_ABEBT_SHIFT) & 2666 HDPX_CFG_ABEBT_MASK) | 2667 ((HDPX_CFG_JAMIPG_DEFAULT << HDPX_CFG_JAMIPG_SHIFT) & 2668 HDPX_CFG_JAMIPG_MASK)); 2669 2670 /* Configure interrupt moderation timer. */ 2671 CSR_WRITE_2(sc, AGE_IM_TIMER, AGE_USECS(sc->age_int_mod)); 2672 reg = CSR_READ_4(sc, AGE_MASTER_CFG); 2673 reg &= ~MASTER_MTIMER_ENB; 2674 if (AGE_USECS(sc->age_int_mod) == 0) 2675 reg &= ~MASTER_ITIMER_ENB; 2676 else 2677 reg |= MASTER_ITIMER_ENB; 2678 CSR_WRITE_4(sc, AGE_MASTER_CFG, reg); 2679 if (bootverbose) 2680 device_printf(sc->age_dev, "interrupt moderation is %d us.\n", 2681 sc->age_int_mod); 2682 CSR_WRITE_2(sc, AGE_INTR_CLR_TIMER, AGE_USECS(1000)); 2683 2684 /* Set Maximum frame size but don't let MTU be lass than ETHER_MTU. */ 2685 if (ifp->if_mtu < ETHERMTU) 2686 sc->age_max_frame_size = ETHERMTU; 2687 else 2688 sc->age_max_frame_size = ifp->if_mtu; 2689 sc->age_max_frame_size += ETHER_HDR_LEN + 2690 sizeof(struct ether_vlan_header) + ETHER_CRC_LEN; 2691 CSR_WRITE_4(sc, AGE_FRAME_SIZE, sc->age_max_frame_size); 2692 /* Configure jumbo frame. */ 2693 fsize = roundup(sc->age_max_frame_size, sizeof(uint64_t)); 2694 CSR_WRITE_4(sc, AGE_RXQ_JUMBO_CFG, 2695 (((fsize / sizeof(uint64_t)) << 2696 RXQ_JUMBO_CFG_SZ_THRESH_SHIFT) & RXQ_JUMBO_CFG_SZ_THRESH_MASK) | 2697 ((RXQ_JUMBO_CFG_LKAH_DEFAULT << 2698 RXQ_JUMBO_CFG_LKAH_SHIFT) & RXQ_JUMBO_CFG_LKAH_MASK) | 2699 ((AGE_USECS(8) << RXQ_JUMBO_CFG_RRD_TIMER_SHIFT) & 2700 RXQ_JUMBO_CFG_RRD_TIMER_MASK)); 2701 2702 /* Configure flow-control parameters. From Linux. */ 2703 if ((sc->age_flags & AGE_FLAG_PCIE) != 0) { 2704 /* 2705 * Magic workaround for old-L1. 2706 * Don't know which hw revision requires this magic. 2707 */ 2708 CSR_WRITE_4(sc, 0x12FC, 0x6500); 2709 /* 2710 * Another magic workaround for flow-control mode 2711 * change. From Linux. 2712 */ 2713 CSR_WRITE_4(sc, 0x1008, CSR_READ_4(sc, 0x1008) | 0x8000); 2714 } 2715 /* 2716 * TODO 2717 * Should understand pause parameter relationships between FIFO 2718 * size and number of Rx descriptors and Rx return descriptors. 2719 * 2720 * Magic parameters came from Linux. 2721 */ 2722 switch (sc->age_chip_rev) { 2723 case 0x8001: 2724 case 0x9001: 2725 case 0x9002: 2726 case 0x9003: 2727 rxf_hi = AGE_RX_RING_CNT / 16; 2728 rxf_lo = (AGE_RX_RING_CNT * 7) / 8; 2729 rrd_hi = (AGE_RR_RING_CNT * 7) / 8; 2730 rrd_lo = AGE_RR_RING_CNT / 16; 2731 break; 2732 default: 2733 reg = CSR_READ_4(sc, AGE_SRAM_RX_FIFO_LEN); 2734 rxf_lo = reg / 16; 2735 if (rxf_lo < 192) 2736 rxf_lo = 192; 2737 rxf_hi = (reg * 7) / 8; 2738 if (rxf_hi < rxf_lo) 2739 rxf_hi = rxf_lo + 16; 2740 reg = CSR_READ_4(sc, AGE_SRAM_RRD_LEN); 2741 rrd_lo = reg / 8; 2742 rrd_hi = (reg * 7) / 8; 2743 if (rrd_lo < 2) 2744 rrd_lo = 2; 2745 if (rrd_hi < rrd_lo) 2746 rrd_hi = rrd_lo + 3; 2747 break; 2748 } 2749 CSR_WRITE_4(sc, AGE_RXQ_FIFO_PAUSE_THRESH, 2750 ((rxf_lo << RXQ_FIFO_PAUSE_THRESH_LO_SHIFT) & 2751 RXQ_FIFO_PAUSE_THRESH_LO_MASK) | 2752 ((rxf_hi << RXQ_FIFO_PAUSE_THRESH_HI_SHIFT) & 2753 RXQ_FIFO_PAUSE_THRESH_HI_MASK)); 2754 CSR_WRITE_4(sc, AGE_RXQ_RRD_PAUSE_THRESH, 2755 ((rrd_lo << RXQ_RRD_PAUSE_THRESH_LO_SHIFT) & 2756 RXQ_RRD_PAUSE_THRESH_LO_MASK) | 2757 ((rrd_hi << RXQ_RRD_PAUSE_THRESH_HI_SHIFT) & 2758 RXQ_RRD_PAUSE_THRESH_HI_MASK)); 2759 2760 /* Configure RxQ. */ 2761 CSR_WRITE_4(sc, AGE_RXQ_CFG, 2762 ((RXQ_CFG_RD_BURST_DEFAULT << RXQ_CFG_RD_BURST_SHIFT) & 2763 RXQ_CFG_RD_BURST_MASK) | 2764 ((RXQ_CFG_RRD_BURST_THRESH_DEFAULT << 2765 RXQ_CFG_RRD_BURST_THRESH_SHIFT) & RXQ_CFG_RRD_BURST_THRESH_MASK) | 2766 ((RXQ_CFG_RD_PREF_MIN_IPG_DEFAULT << 2767 RXQ_CFG_RD_PREF_MIN_IPG_SHIFT) & RXQ_CFG_RD_PREF_MIN_IPG_MASK) | 2768 RXQ_CFG_CUT_THROUGH_ENB | RXQ_CFG_ENB); 2769 2770 /* Configure TxQ. */ 2771 CSR_WRITE_4(sc, AGE_TXQ_CFG, 2772 ((TXQ_CFG_TPD_BURST_DEFAULT << TXQ_CFG_TPD_BURST_SHIFT) & 2773 TXQ_CFG_TPD_BURST_MASK) | 2774 ((TXQ_CFG_TX_FIFO_BURST_DEFAULT << TXQ_CFG_TX_FIFO_BURST_SHIFT) & 2775 TXQ_CFG_TX_FIFO_BURST_MASK) | 2776 ((TXQ_CFG_TPD_FETCH_DEFAULT << 2777 TXQ_CFG_TPD_FETCH_THRESH_SHIFT) & TXQ_CFG_TPD_FETCH_THRESH_MASK) | 2778 TXQ_CFG_ENB); 2779 2780 CSR_WRITE_4(sc, AGE_TX_JUMBO_TPD_TH_IPG, 2781 (((fsize / sizeof(uint64_t) << TX_JUMBO_TPD_TH_SHIFT)) & 2782 TX_JUMBO_TPD_TH_MASK) | 2783 ((TX_JUMBO_TPD_IPG_DEFAULT << TX_JUMBO_TPD_IPG_SHIFT) & 2784 TX_JUMBO_TPD_IPG_MASK)); 2785 /* Configure DMA parameters. */ 2786 CSR_WRITE_4(sc, AGE_DMA_CFG, 2787 DMA_CFG_ENH_ORDER | DMA_CFG_RCB_64 | 2788 sc->age_dma_rd_burst | DMA_CFG_RD_ENB | 2789 sc->age_dma_wr_burst | DMA_CFG_WR_ENB); 2790 2791 /* Configure CMB DMA write threshold. */ 2792 CSR_WRITE_4(sc, AGE_CMB_WR_THRESH, 2793 ((CMB_WR_THRESH_RRD_DEFAULT << CMB_WR_THRESH_RRD_SHIFT) & 2794 CMB_WR_THRESH_RRD_MASK) | 2795 ((CMB_WR_THRESH_TPD_DEFAULT << CMB_WR_THRESH_TPD_SHIFT) & 2796 CMB_WR_THRESH_TPD_MASK)); 2797 2798 /* Set CMB/SMB timer and enable them. */ 2799 CSR_WRITE_4(sc, AGE_CMB_WR_TIMER, 2800 ((AGE_USECS(2) << CMB_WR_TIMER_TX_SHIFT) & CMB_WR_TIMER_TX_MASK) | 2801 ((AGE_USECS(2) << CMB_WR_TIMER_RX_SHIFT) & CMB_WR_TIMER_RX_MASK)); 2802 /* Request SMB updates for every seconds. */ 2803 CSR_WRITE_4(sc, AGE_SMB_TIMER, AGE_USECS(1000 * 1000)); 2804 CSR_WRITE_4(sc, AGE_CSMB_CTRL, CSMB_CTRL_SMB_ENB | CSMB_CTRL_CMB_ENB); 2805 2806 /* 2807 * Disable all WOL bits as WOL can interfere normal Rx 2808 * operation. 2809 */ 2810 CSR_WRITE_4(sc, AGE_WOL_CFG, 0); 2811 2812 /* 2813 * Configure Tx/Rx MACs. 2814 * - Auto-padding for short frames. 2815 * - Enable CRC generation. 2816 * Start with full-duplex/1000Mbps media. Actual reconfiguration 2817 * of MAC is followed after link establishment. 2818 */ 2819 CSR_WRITE_4(sc, AGE_MAC_CFG, 2820 MAC_CFG_TX_CRC_ENB | MAC_CFG_TX_AUTO_PAD | 2821 MAC_CFG_FULL_DUPLEX | MAC_CFG_SPEED_1000 | 2822 ((MAC_CFG_PREAMBLE_DEFAULT << MAC_CFG_PREAMBLE_SHIFT) & 2823 MAC_CFG_PREAMBLE_MASK)); 2824 /* Set up the receive filter. */ 2825 age_rxfilter(sc); 2826 age_rxvlan(sc); 2827 2828 reg = CSR_READ_4(sc, AGE_MAC_CFG); 2829 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) 2830 reg |= MAC_CFG_RXCSUM_ENB; 2831 2832 /* Ack all pending interrupts and clear it. */ 2833 CSR_WRITE_4(sc, AGE_INTR_STATUS, 0); 2834 CSR_WRITE_4(sc, AGE_INTR_MASK, AGE_INTRS); 2835 2836 /* Finally enable Tx/Rx MAC. */ 2837 CSR_WRITE_4(sc, AGE_MAC_CFG, reg | MAC_CFG_TX_ENB | MAC_CFG_RX_ENB); 2838 2839 sc->age_flags &= ~AGE_FLAG_LINK; 2840 /* Switch to the current media. */ 2841 mii_mediachg(mii); 2842 2843 callout_reset(&sc->age_tick_ch, hz, age_tick, sc); 2844 2845 ifp->if_drv_flags |= IFF_DRV_RUNNING; 2846 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2847} 2848 2849static void 2850age_stop(struct age_softc *sc) 2851{ 2852 struct ifnet *ifp; 2853 struct age_txdesc *txd; 2854 struct age_rxdesc *rxd; 2855 uint32_t reg; 2856 int i; 2857 2858 AGE_LOCK_ASSERT(sc); 2859 /* 2860 * Mark the interface down and cancel the watchdog timer. 2861 */ 2862 ifp = sc->age_ifp; 2863 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 2864 sc->age_flags &= ~AGE_FLAG_LINK; 2865 callout_stop(&sc->age_tick_ch); 2866 sc->age_watchdog_timer = 0; 2867 2868 /* 2869 * Disable interrupts. 2870 */ 2871 CSR_WRITE_4(sc, AGE_INTR_MASK, 0); 2872 CSR_WRITE_4(sc, AGE_INTR_STATUS, 0xFFFFFFFF); 2873 /* Stop CMB/SMB updates. */ 2874 CSR_WRITE_4(sc, AGE_CSMB_CTRL, 0); 2875 /* Stop Rx/Tx MAC. */ 2876 age_stop_rxmac(sc); 2877 age_stop_txmac(sc); 2878 /* Stop DMA. */ 2879 CSR_WRITE_4(sc, AGE_DMA_CFG, 2880 CSR_READ_4(sc, AGE_DMA_CFG) & ~(DMA_CFG_RD_ENB | DMA_CFG_WR_ENB)); 2881 /* Stop TxQ/RxQ. */ 2882 CSR_WRITE_4(sc, AGE_TXQ_CFG, 2883 CSR_READ_4(sc, AGE_TXQ_CFG) & ~TXQ_CFG_ENB); 2884 CSR_WRITE_4(sc, AGE_RXQ_CFG, 2885 CSR_READ_4(sc, AGE_RXQ_CFG) & ~RXQ_CFG_ENB); 2886 for (i = AGE_RESET_TIMEOUT; i > 0; i--) { 2887 if ((reg = CSR_READ_4(sc, AGE_IDLE_STATUS)) == 0) 2888 break; 2889 DELAY(10); 2890 } 2891 if (i == 0) 2892 device_printf(sc->age_dev, 2893 "stopping Rx/Tx MACs timed out(0x%08x)!\n", reg); 2894 2895 /* Reclaim Rx buffers that have been processed. */ 2896 if (sc->age_cdata.age_rxhead != NULL) 2897 m_freem(sc->age_cdata.age_rxhead); 2898 AGE_RXCHAIN_RESET(sc); 2899 /* 2900 * Free RX and TX mbufs still in the queues. 2901 */ 2902 for (i = 0; i < AGE_RX_RING_CNT; i++) { 2903 rxd = &sc->age_cdata.age_rxdesc[i]; 2904 if (rxd->rx_m != NULL) { 2905 bus_dmamap_sync(sc->age_cdata.age_rx_tag, 2906 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 2907 bus_dmamap_unload(sc->age_cdata.age_rx_tag, 2908 rxd->rx_dmamap); 2909 m_freem(rxd->rx_m); 2910 rxd->rx_m = NULL; 2911 } 2912 } 2913 for (i = 0; i < AGE_TX_RING_CNT; i++) { 2914 txd = &sc->age_cdata.age_txdesc[i]; 2915 if (txd->tx_m != NULL) { 2916 bus_dmamap_sync(sc->age_cdata.age_tx_tag, 2917 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 2918 bus_dmamap_unload(sc->age_cdata.age_tx_tag, 2919 txd->tx_dmamap); 2920 m_freem(txd->tx_m); 2921 txd->tx_m = NULL; 2922 } 2923 } 2924} 2925 2926static void 2927age_stop_txmac(struct age_softc *sc) 2928{ 2929 uint32_t reg; 2930 int i; 2931 2932 AGE_LOCK_ASSERT(sc); 2933 2934 reg = CSR_READ_4(sc, AGE_MAC_CFG); 2935 if ((reg & MAC_CFG_TX_ENB) != 0) { 2936 reg &= ~MAC_CFG_TX_ENB; 2937 CSR_WRITE_4(sc, AGE_MAC_CFG, reg); 2938 } 2939 /* Stop Tx DMA engine. */ 2940 reg = CSR_READ_4(sc, AGE_DMA_CFG); 2941 if ((reg & DMA_CFG_RD_ENB) != 0) { 2942 reg &= ~DMA_CFG_RD_ENB; 2943 CSR_WRITE_4(sc, AGE_DMA_CFG, reg); 2944 } 2945 for (i = AGE_RESET_TIMEOUT; i > 0; i--) { 2946 if ((CSR_READ_4(sc, AGE_IDLE_STATUS) & 2947 (IDLE_STATUS_TXMAC | IDLE_STATUS_DMARD)) == 0) 2948 break; 2949 DELAY(10); 2950 } 2951 if (i == 0) 2952 device_printf(sc->age_dev, "stopping TxMAC timeout!\n"); 2953} 2954 2955static void 2956age_stop_rxmac(struct age_softc *sc) 2957{ 2958 uint32_t reg; 2959 int i; 2960 2961 AGE_LOCK_ASSERT(sc); 2962 2963 reg = CSR_READ_4(sc, AGE_MAC_CFG); 2964 if ((reg & MAC_CFG_RX_ENB) != 0) { 2965 reg &= ~MAC_CFG_RX_ENB; 2966 CSR_WRITE_4(sc, AGE_MAC_CFG, reg); 2967 } 2968 /* Stop Rx DMA engine. */ 2969 reg = CSR_READ_4(sc, AGE_DMA_CFG); 2970 if ((reg & DMA_CFG_WR_ENB) != 0) { 2971 reg &= ~DMA_CFG_WR_ENB; 2972 CSR_WRITE_4(sc, AGE_DMA_CFG, reg); 2973 } 2974 for (i = AGE_RESET_TIMEOUT; i > 0; i--) { 2975 if ((CSR_READ_4(sc, AGE_IDLE_STATUS) & 2976 (IDLE_STATUS_RXMAC | IDLE_STATUS_DMAWR)) == 0) 2977 break; 2978 DELAY(10); 2979 } 2980 if (i == 0) 2981 device_printf(sc->age_dev, "stopping RxMAC timeout!\n"); 2982} 2983 2984static void 2985age_init_tx_ring(struct age_softc *sc) 2986{ 2987 struct age_ring_data *rd; 2988 struct age_txdesc *txd; 2989 int i; 2990 2991 AGE_LOCK_ASSERT(sc); 2992 2993 sc->age_cdata.age_tx_prod = 0; 2994 sc->age_cdata.age_tx_cons = 0; 2995 sc->age_cdata.age_tx_cnt = 0; 2996 2997 rd = &sc->age_rdata; 2998 bzero(rd->age_tx_ring, AGE_TX_RING_SZ); 2999 for (i = 0; i < AGE_TX_RING_CNT; i++) { 3000 txd = &sc->age_cdata.age_txdesc[i]; 3001 txd->tx_desc = &rd->age_tx_ring[i]; 3002 txd->tx_m = NULL; 3003 } 3004 3005 bus_dmamap_sync(sc->age_cdata.age_tx_ring_tag, 3006 sc->age_cdata.age_tx_ring_map, 3007 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3008} 3009 3010static int 3011age_init_rx_ring(struct age_softc *sc) 3012{ 3013 struct age_ring_data *rd; 3014 struct age_rxdesc *rxd; 3015 int i; 3016 3017 AGE_LOCK_ASSERT(sc); 3018 3019 sc->age_cdata.age_rx_cons = AGE_RX_RING_CNT - 1; 3020 sc->age_morework = 0; 3021 rd = &sc->age_rdata; 3022 bzero(rd->age_rx_ring, AGE_RX_RING_SZ); 3023 for (i = 0; i < AGE_RX_RING_CNT; i++) { 3024 rxd = &sc->age_cdata.age_rxdesc[i]; 3025 rxd->rx_m = NULL; 3026 rxd->rx_desc = &rd->age_rx_ring[i]; 3027 if (age_newbuf(sc, rxd) != 0) 3028 return (ENOBUFS); 3029 } 3030 3031 bus_dmamap_sync(sc->age_cdata.age_rx_ring_tag, 3032 sc->age_cdata.age_rx_ring_map, BUS_DMASYNC_PREWRITE); 3033 3034 return (0); 3035} 3036 3037static void 3038age_init_rr_ring(struct age_softc *sc) 3039{ 3040 struct age_ring_data *rd; 3041 3042 AGE_LOCK_ASSERT(sc); 3043 3044 sc->age_cdata.age_rr_cons = 0; 3045 AGE_RXCHAIN_RESET(sc); 3046 3047 rd = &sc->age_rdata; 3048 bzero(rd->age_rr_ring, AGE_RR_RING_SZ); 3049 bus_dmamap_sync(sc->age_cdata.age_rr_ring_tag, 3050 sc->age_cdata.age_rr_ring_map, 3051 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3052} 3053 3054static void 3055age_init_cmb_block(struct age_softc *sc) 3056{ 3057 struct age_ring_data *rd; 3058 3059 AGE_LOCK_ASSERT(sc); 3060 3061 rd = &sc->age_rdata; 3062 bzero(rd->age_cmb_block, AGE_CMB_BLOCK_SZ); 3063 bus_dmamap_sync(sc->age_cdata.age_cmb_block_tag, 3064 sc->age_cdata.age_cmb_block_map, 3065 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3066} 3067 3068static void 3069age_init_smb_block(struct age_softc *sc) 3070{ 3071 struct age_ring_data *rd; 3072 3073 AGE_LOCK_ASSERT(sc); 3074 3075 rd = &sc->age_rdata; 3076 bzero(rd->age_smb_block, AGE_SMB_BLOCK_SZ); 3077 bus_dmamap_sync(sc->age_cdata.age_smb_block_tag, 3078 sc->age_cdata.age_smb_block_map, 3079 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3080} 3081 3082static int 3083age_newbuf(struct age_softc *sc, struct age_rxdesc *rxd) 3084{ 3085 struct rx_desc *desc; 3086 struct mbuf *m; 3087 bus_dma_segment_t segs[1]; 3088 bus_dmamap_t map; 3089 int nsegs; 3090 3091 AGE_LOCK_ASSERT(sc); 3092 3093 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 3094 if (m == NULL) 3095 return (ENOBUFS); 3096 m->m_len = m->m_pkthdr.len = MCLBYTES; 3097#ifndef __NO_STRICT_ALIGNMENT 3098 m_adj(m, AGE_RX_BUF_ALIGN); 3099#endif 3100 3101 if (bus_dmamap_load_mbuf_sg(sc->age_cdata.age_rx_tag, 3102 sc->age_cdata.age_rx_sparemap, m, segs, &nsegs, 0) != 0) { 3103 m_freem(m); 3104 return (ENOBUFS); 3105 } 3106 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 3107 3108 if (rxd->rx_m != NULL) { 3109 bus_dmamap_sync(sc->age_cdata.age_rx_tag, rxd->rx_dmamap, 3110 BUS_DMASYNC_POSTREAD); 3111 bus_dmamap_unload(sc->age_cdata.age_rx_tag, rxd->rx_dmamap); 3112 } 3113 map = rxd->rx_dmamap; 3114 rxd->rx_dmamap = sc->age_cdata.age_rx_sparemap; 3115 sc->age_cdata.age_rx_sparemap = map; 3116 bus_dmamap_sync(sc->age_cdata.age_rx_tag, rxd->rx_dmamap, 3117 BUS_DMASYNC_PREREAD); 3118 rxd->rx_m = m; 3119 3120 desc = rxd->rx_desc; 3121 desc->addr = htole64(segs[0].ds_addr); 3122 desc->len = htole32((segs[0].ds_len & AGE_RD_LEN_MASK) << 3123 AGE_RD_LEN_SHIFT); 3124 return (0); 3125} 3126 3127static void 3128age_rxvlan(struct age_softc *sc) 3129{ 3130 struct ifnet *ifp; 3131 uint32_t reg; 3132 3133 AGE_LOCK_ASSERT(sc); 3134 3135 ifp = sc->age_ifp; 3136 reg = CSR_READ_4(sc, AGE_MAC_CFG); 3137 reg &= ~MAC_CFG_VLAN_TAG_STRIP; 3138 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) 3139 reg |= MAC_CFG_VLAN_TAG_STRIP; 3140 CSR_WRITE_4(sc, AGE_MAC_CFG, reg); 3141} 3142 3143static void 3144age_rxfilter(struct age_softc *sc) 3145{ 3146 struct ifnet *ifp; 3147 struct ifmultiaddr *ifma; 3148 uint32_t crc; 3149 uint32_t mchash[2]; 3150 uint32_t rxcfg; 3151 3152 AGE_LOCK_ASSERT(sc); 3153 3154 ifp = sc->age_ifp; 3155 3156 rxcfg = CSR_READ_4(sc, AGE_MAC_CFG); 3157 rxcfg &= ~(MAC_CFG_ALLMULTI | MAC_CFG_BCAST | MAC_CFG_PROMISC); 3158 if ((ifp->if_flags & IFF_BROADCAST) != 0) 3159 rxcfg |= MAC_CFG_BCAST; 3160 if ((ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) != 0) { 3161 if ((ifp->if_flags & IFF_PROMISC) != 0) 3162 rxcfg |= MAC_CFG_PROMISC; 3163 if ((ifp->if_flags & IFF_ALLMULTI) != 0) 3164 rxcfg |= MAC_CFG_ALLMULTI; 3165 CSR_WRITE_4(sc, AGE_MAR0, 0xFFFFFFFF); 3166 CSR_WRITE_4(sc, AGE_MAR1, 0xFFFFFFFF); 3167 CSR_WRITE_4(sc, AGE_MAC_CFG, rxcfg); 3168 return; 3169 } 3170 3171 /* Program new filter. */ 3172 bzero(mchash, sizeof(mchash)); 3173 3174 if_maddr_rlock(ifp); 3175 TAILQ_FOREACH(ifma, &sc->age_ifp->if_multiaddrs, ifma_link) { 3176 if (ifma->ifma_addr->sa_family != AF_LINK) 3177 continue; 3178 crc = ether_crc32_be(LLADDR((struct sockaddr_dl *) 3179 ifma->ifma_addr), ETHER_ADDR_LEN); 3180 mchash[crc >> 31] |= 1 << ((crc >> 26) & 0x1f); 3181 } 3182 if_maddr_runlock(ifp); 3183 3184 CSR_WRITE_4(sc, AGE_MAR0, mchash[0]); 3185 CSR_WRITE_4(sc, AGE_MAR1, mchash[1]); 3186 CSR_WRITE_4(sc, AGE_MAC_CFG, rxcfg); 3187} 3188 3189static int 3190sysctl_age_stats(SYSCTL_HANDLER_ARGS) 3191{ 3192 struct age_softc *sc; 3193 struct age_stats *stats; 3194 int error, result; 3195 3196 result = -1; 3197 error = sysctl_handle_int(oidp, &result, 0, req); 3198 3199 if (error != 0 || req->newptr == NULL) 3200 return (error); 3201 3202 if (result != 1) 3203 return (error); 3204 3205 sc = (struct age_softc *)arg1; 3206 stats = &sc->age_stat; 3207 printf("%s statistics:\n", device_get_nameunit(sc->age_dev)); 3208 printf("Transmit good frames : %ju\n", 3209 (uintmax_t)stats->tx_frames); 3210 printf("Transmit good broadcast frames : %ju\n", 3211 (uintmax_t)stats->tx_bcast_frames); 3212 printf("Transmit good multicast frames : %ju\n", 3213 (uintmax_t)stats->tx_mcast_frames); 3214 printf("Transmit pause control frames : %u\n", 3215 stats->tx_pause_frames); 3216 printf("Transmit control frames : %u\n", 3217 stats->tx_control_frames); 3218 printf("Transmit frames with excessive deferrals : %u\n", 3219 stats->tx_excess_defer); 3220 printf("Transmit deferrals : %u\n", 3221 stats->tx_deferred); 3222 printf("Transmit good octets : %ju\n", 3223 (uintmax_t)stats->tx_bytes); 3224 printf("Transmit good broadcast octets : %ju\n", 3225 (uintmax_t)stats->tx_bcast_bytes); 3226 printf("Transmit good multicast octets : %ju\n", 3227 (uintmax_t)stats->tx_mcast_bytes); 3228 printf("Transmit frames 64 bytes : %ju\n", 3229 (uintmax_t)stats->tx_pkts_64); 3230 printf("Transmit frames 65 to 127 bytes : %ju\n", 3231 (uintmax_t)stats->tx_pkts_65_127); 3232 printf("Transmit frames 128 to 255 bytes : %ju\n", 3233 (uintmax_t)stats->tx_pkts_128_255); 3234 printf("Transmit frames 256 to 511 bytes : %ju\n", 3235 (uintmax_t)stats->tx_pkts_256_511); 3236 printf("Transmit frames 512 to 1024 bytes : %ju\n", 3237 (uintmax_t)stats->tx_pkts_512_1023); 3238 printf("Transmit frames 1024 to 1518 bytes : %ju\n", 3239 (uintmax_t)stats->tx_pkts_1024_1518); 3240 printf("Transmit frames 1519 to MTU bytes : %ju\n", 3241 (uintmax_t)stats->tx_pkts_1519_max); 3242 printf("Transmit single collisions : %u\n", 3243 stats->tx_single_colls); 3244 printf("Transmit multiple collisions : %u\n", 3245 stats->tx_multi_colls); 3246 printf("Transmit late collisions : %u\n", 3247 stats->tx_late_colls); 3248 printf("Transmit abort due to excessive collisions : %u\n", 3249 stats->tx_excess_colls); 3250 printf("Transmit underruns due to FIFO underruns : %u\n", 3251 stats->tx_underrun); 3252 printf("Transmit descriptor write-back errors : %u\n", 3253 stats->tx_desc_underrun); 3254 printf("Transmit frames with length mismatched frame size : %u\n", 3255 stats->tx_lenerrs); 3256 printf("Transmit frames with truncated due to MTU size : %u\n", 3257 stats->tx_lenerrs); 3258 3259 printf("Receive good frames : %ju\n", 3260 (uintmax_t)stats->rx_frames); 3261 printf("Receive good broadcast frames : %ju\n", 3262 (uintmax_t)stats->rx_bcast_frames); 3263 printf("Receive good multicast frames : %ju\n", 3264 (uintmax_t)stats->rx_mcast_frames); 3265 printf("Receive pause control frames : %u\n", 3266 stats->rx_pause_frames); 3267 printf("Receive control frames : %u\n", 3268 stats->rx_control_frames); 3269 printf("Receive CRC errors : %u\n", 3270 stats->rx_crcerrs); 3271 printf("Receive frames with length errors : %u\n", 3272 stats->rx_lenerrs); 3273 printf("Receive good octets : %ju\n", 3274 (uintmax_t)stats->rx_bytes); 3275 printf("Receive good broadcast octets : %ju\n", 3276 (uintmax_t)stats->rx_bcast_bytes); 3277 printf("Receive good multicast octets : %ju\n", 3278 (uintmax_t)stats->rx_mcast_bytes); 3279 printf("Receive frames too short : %u\n", 3280 stats->rx_runts); 3281 printf("Receive fragmented frames : %ju\n", 3282 (uintmax_t)stats->rx_fragments); 3283 printf("Receive frames 64 bytes : %ju\n", 3284 (uintmax_t)stats->rx_pkts_64); 3285 printf("Receive frames 65 to 127 bytes : %ju\n", 3286 (uintmax_t)stats->rx_pkts_65_127); 3287 printf("Receive frames 128 to 255 bytes : %ju\n", 3288 (uintmax_t)stats->rx_pkts_128_255); 3289 printf("Receive frames 256 to 511 bytes : %ju\n", 3290 (uintmax_t)stats->rx_pkts_256_511); 3291 printf("Receive frames 512 to 1024 bytes : %ju\n", 3292 (uintmax_t)stats->rx_pkts_512_1023); 3293 printf("Receive frames 1024 to 1518 bytes : %ju\n", 3294 (uintmax_t)stats->rx_pkts_1024_1518); 3295 printf("Receive frames 1519 to MTU bytes : %ju\n", 3296 (uintmax_t)stats->rx_pkts_1519_max); 3297 printf("Receive frames too long : %ju\n", 3298 (uint64_t)stats->rx_pkts_truncated); 3299 printf("Receive frames with FIFO overflow : %u\n", 3300 stats->rx_fifo_oflows); 3301 printf("Receive frames with return descriptor overflow : %u\n", 3302 stats->rx_desc_oflows); 3303 printf("Receive frames with alignment errors : %u\n", 3304 stats->rx_alignerrs); 3305 printf("Receive frames dropped due to address filtering : %ju\n", 3306 (uint64_t)stats->rx_pkts_filtered); 3307 3308 return (error); 3309} 3310 3311static int 3312sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high) 3313{ 3314 int error, value; 3315 3316 if (arg1 == NULL) 3317 return (EINVAL); 3318 value = *(int *)arg1; 3319 error = sysctl_handle_int(oidp, &value, 0, req); 3320 if (error || req->newptr == NULL) 3321 return (error); 3322 if (value < low || value > high) 3323 return (EINVAL); 3324 *(int *)arg1 = value; 3325 3326 return (0); 3327} 3328 3329static int 3330sysctl_hw_age_proc_limit(SYSCTL_HANDLER_ARGS) 3331{ 3332 return (sysctl_int_range(oidp, arg1, arg2, req, 3333 AGE_PROC_MIN, AGE_PROC_MAX)); 3334} 3335 3336static int 3337sysctl_hw_age_int_mod(SYSCTL_HANDLER_ARGS) 3338{ 3339 3340 return (sysctl_int_range(oidp, arg1, arg2, req, AGE_IM_TIMER_MIN, 3341 AGE_IM_TIMER_MAX)); 3342} 3343