1/*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2009, Pyun YongHyeon <yongari@FreeBSD.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice unmodified, this list of conditions, and the following 12 * disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30/* Driver for Atheros AR813x/AR815x PCIe Ethernet. */ 31 32#include <sys/cdefs.h> 33__FBSDID("$FreeBSD$"); 34 35#include <sys/param.h> 36#include <sys/systm.h> 37#include <sys/bus.h> 38#include <sys/endian.h> 39#include <sys/kernel.h> 40#include <sys/lock.h> 41#include <sys/malloc.h> 42#include <sys/mbuf.h> 43#include <sys/module.h> 44#include <sys/mutex.h> 45#include <sys/rman.h> 46#include <sys/queue.h> 47#include <sys/socket.h> 48#include <sys/sockio.h> 49#include <sys/sysctl.h> 50#include <sys/taskqueue.h> 51 52#include <net/bpf.h> 53#include <net/debugnet.h> 54#include <net/if.h> 55#include <net/if_var.h> 56#include <net/if_arp.h> 57#include <net/ethernet.h> 58#include <net/if_dl.h> 59#include <net/if_llc.h> 60#include <net/if_media.h> 61#include <net/if_types.h> 62#include <net/if_vlan_var.h> 63 64#include <netinet/in.h> 65#include <netinet/in_systm.h> 66#include <netinet/ip.h> 67#include <netinet/tcp.h> 68 69#include <dev/mii/mii.h> 70#include <dev/mii/miivar.h> 71 72#include <dev/pci/pcireg.h> 73#include <dev/pci/pcivar.h> 74 75#include <machine/bus.h> 76#include <machine/in_cksum.h> 77 78#include <dev/alc/if_alcreg.h> 79#include <dev/alc/if_alcvar.h> 80 81/* "device miibus" required. See GENERIC if you get errors here. */ 82#include "miibus_if.h" 83#undef ALC_USE_CUSTOM_CSUM 84 85#ifdef ALC_USE_CUSTOM_CSUM 86#define ALC_CSUM_FEATURES (CSUM_TCP | CSUM_UDP) 87#else 88#define ALC_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 89#endif 90 91MODULE_DEPEND(alc, pci, 1, 1, 1); 92MODULE_DEPEND(alc, ether, 1, 1, 1); 93MODULE_DEPEND(alc, miibus, 1, 1, 1); 94 95/* Tunables. */ 96static int msi_disable = 0; 97static int msix_disable = 0; 98TUNABLE_INT("hw.alc.msi_disable", &msi_disable); 99TUNABLE_INT("hw.alc.msix_disable", &msix_disable); 100 101/* 102 * Devices supported by this driver. 103 */ 104static struct alc_ident alc_ident_table[] = { 105 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8131, 9 * 1024, 106 "Atheros AR8131 PCIe Gigabit Ethernet" }, 107 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8132, 9 * 1024, 108 "Atheros AR8132 PCIe Fast Ethernet" }, 109 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8151, 6 * 1024, 110 "Atheros AR8151 v1.0 PCIe Gigabit Ethernet" }, 111 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8151_V2, 6 * 1024, 112 "Atheros AR8151 v2.0 PCIe Gigabit Ethernet" }, 113 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8152_B, 6 * 1024, 114 "Atheros AR8152 v1.1 PCIe Fast Ethernet" }, 115 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8152_B2, 6 * 1024, 116 "Atheros AR8152 v2.0 PCIe Fast Ethernet" }, 117 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8161, 9 * 1024, 118 "Atheros AR8161 PCIe Gigabit Ethernet" }, 119 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8162, 9 * 1024, 120 "Atheros AR8162 PCIe Fast Ethernet" }, 121 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8171, 9 * 1024, 122 "Atheros AR8171 PCIe Gigabit Ethernet" }, 123 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8172, 9 * 1024, 124 "Atheros AR8172 PCIe Fast Ethernet" }, 125 { VENDORID_ATHEROS, DEVICEID_ATHEROS_E2200, 9 * 1024, 126 "Killer E2200 Gigabit Ethernet" }, 127 { VENDORID_ATHEROS, DEVICEID_ATHEROS_E2400, 9 * 1024, 128 "Killer E2400 Gigabit Ethernet" }, 129 { VENDORID_ATHEROS, DEVICEID_ATHEROS_E2500, 9 * 1024, 130 "Killer E2500 Gigabit Ethernet" }, 131 { 0, 0, 0, NULL} 132}; 133 134static void alc_aspm(struct alc_softc *, int, int); 135static void alc_aspm_813x(struct alc_softc *, int); 136static void alc_aspm_816x(struct alc_softc *, int); 137static int alc_attach(device_t); 138static int alc_check_boundary(struct alc_softc *); 139static void alc_config_msi(struct alc_softc *); 140static int alc_detach(device_t); 141static void alc_disable_l0s_l1(struct alc_softc *); 142static int alc_dma_alloc(struct alc_softc *); 143static void alc_dma_free(struct alc_softc *); 144static void alc_dmamap_cb(void *, bus_dma_segment_t *, int, int); 145static void alc_dsp_fixup(struct alc_softc *, int); 146static int alc_encap(struct alc_softc *, struct mbuf **); 147static struct alc_ident * 148 alc_find_ident(device_t); 149#ifndef __NO_STRICT_ALIGNMENT 150static struct mbuf * 151 alc_fixup_rx(struct ifnet *, struct mbuf *); 152#endif 153static void alc_get_macaddr(struct alc_softc *); 154static void alc_get_macaddr_813x(struct alc_softc *); 155static void alc_get_macaddr_816x(struct alc_softc *); 156static void alc_get_macaddr_par(struct alc_softc *); 157static void alc_init(void *); 158static void alc_init_cmb(struct alc_softc *); 159static void alc_init_locked(struct alc_softc *); 160static void alc_init_rr_ring(struct alc_softc *); 161static int alc_init_rx_ring(struct alc_softc *); 162static void alc_init_smb(struct alc_softc *); 163static void alc_init_tx_ring(struct alc_softc *); 164static void alc_int_task(void *, int); 165static int alc_intr(void *); 166static int alc_ioctl(struct ifnet *, u_long, caddr_t); 167static void alc_mac_config(struct alc_softc *); 168static uint32_t alc_mii_readreg_813x(struct alc_softc *, int, int); 169static uint32_t alc_mii_readreg_816x(struct alc_softc *, int, int); 170static uint32_t alc_mii_writereg_813x(struct alc_softc *, int, int, int); 171static uint32_t alc_mii_writereg_816x(struct alc_softc *, int, int, int); 172static int alc_miibus_readreg(device_t, int, int); 173static void alc_miibus_statchg(device_t); 174static int alc_miibus_writereg(device_t, int, int, int); 175static uint32_t alc_miidbg_readreg(struct alc_softc *, int); 176static uint32_t alc_miidbg_writereg(struct alc_softc *, int, int); 177static uint32_t alc_miiext_readreg(struct alc_softc *, int, int); 178static uint32_t alc_miiext_writereg(struct alc_softc *, int, int, int); 179static int alc_mediachange(struct ifnet *); 180static int alc_mediachange_locked(struct alc_softc *); 181static void alc_mediastatus(struct ifnet *, struct ifmediareq *); 182static int alc_newbuf(struct alc_softc *, struct alc_rxdesc *); 183static void alc_osc_reset(struct alc_softc *); 184static void alc_phy_down(struct alc_softc *); 185static void alc_phy_reset(struct alc_softc *); 186static void alc_phy_reset_813x(struct alc_softc *); 187static void alc_phy_reset_816x(struct alc_softc *); 188static int alc_probe(device_t); 189static void alc_reset(struct alc_softc *); 190static int alc_resume(device_t); 191static void alc_rxeof(struct alc_softc *, struct rx_rdesc *); 192static int alc_rxintr(struct alc_softc *, int); 193static void alc_rxfilter(struct alc_softc *); 194static void alc_rxvlan(struct alc_softc *); 195static void alc_setlinkspeed(struct alc_softc *); 196static void alc_setwol(struct alc_softc *); 197static void alc_setwol_813x(struct alc_softc *); 198static void alc_setwol_816x(struct alc_softc *); 199static int alc_shutdown(device_t); 200static void alc_start(struct ifnet *); 201static void alc_start_locked(struct ifnet *); 202static void alc_start_queue(struct alc_softc *); 203static void alc_start_tx(struct alc_softc *); 204static void alc_stats_clear(struct alc_softc *); 205static void alc_stats_update(struct alc_softc *); 206static void alc_stop(struct alc_softc *); 207static void alc_stop_mac(struct alc_softc *); 208static void alc_stop_queue(struct alc_softc *); 209static int alc_suspend(device_t); 210static void alc_sysctl_node(struct alc_softc *); 211static void alc_tick(void *); 212static void alc_txeof(struct alc_softc *); 213static void alc_watchdog(struct alc_softc *); 214static int sysctl_int_range(SYSCTL_HANDLER_ARGS, int, int); 215static int sysctl_hw_alc_proc_limit(SYSCTL_HANDLER_ARGS); 216static int sysctl_hw_alc_int_mod(SYSCTL_HANDLER_ARGS); 217 218DEBUGNET_DEFINE(alc); 219 220static device_method_t alc_methods[] = { 221 /* Device interface. */ 222 DEVMETHOD(device_probe, alc_probe), 223 DEVMETHOD(device_attach, alc_attach), 224 DEVMETHOD(device_detach, alc_detach), 225 DEVMETHOD(device_shutdown, alc_shutdown), 226 DEVMETHOD(device_suspend, alc_suspend), 227 DEVMETHOD(device_resume, alc_resume), 228 229 /* MII interface. */ 230 DEVMETHOD(miibus_readreg, alc_miibus_readreg), 231 DEVMETHOD(miibus_writereg, alc_miibus_writereg), 232 DEVMETHOD(miibus_statchg, alc_miibus_statchg), 233 234 DEVMETHOD_END 235}; 236 237static driver_t alc_driver = { 238 "alc", 239 alc_methods, 240 sizeof(struct alc_softc) 241}; 242 243static devclass_t alc_devclass; 244 245DRIVER_MODULE(alc, pci, alc_driver, alc_devclass, 0, 0); 246MODULE_PNP_INFO("U16:vendor;U16:device", pci, alc, alc_ident_table, 247 nitems(alc_ident_table) - 1); 248DRIVER_MODULE(miibus, alc, miibus_driver, miibus_devclass, 0, 0); 249 250static struct resource_spec alc_res_spec_mem[] = { 251 { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE }, 252 { -1, 0, 0 } 253}; 254 255static struct resource_spec alc_irq_spec_legacy[] = { 256 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE }, 257 { -1, 0, 0 } 258}; 259 260static struct resource_spec alc_irq_spec_msi[] = { 261 { SYS_RES_IRQ, 1, RF_ACTIVE }, 262 { -1, 0, 0 } 263}; 264 265static struct resource_spec alc_irq_spec_msix[] = { 266 { SYS_RES_IRQ, 1, RF_ACTIVE }, 267 { -1, 0, 0 } 268}; 269 270static uint32_t alc_dma_burst[] = { 128, 256, 512, 1024, 2048, 4096, 0, 0 }; 271 272static int 273alc_miibus_readreg(device_t dev, int phy, int reg) 274{ 275 struct alc_softc *sc; 276 int v; 277 278 sc = device_get_softc(dev); 279 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 280 v = alc_mii_readreg_816x(sc, phy, reg); 281 else 282 v = alc_mii_readreg_813x(sc, phy, reg); 283 return (v); 284} 285 286static uint32_t 287alc_mii_readreg_813x(struct alc_softc *sc, int phy, int reg) 288{ 289 uint32_t v; 290 int i; 291 292 /* 293 * For AR8132 fast ethernet controller, do not report 1000baseT 294 * capability to mii(4). Even though AR8132 uses the same 295 * model/revision number of F1 gigabit PHY, the PHY has no 296 * ability to establish 1000baseT link. 297 */ 298 if ((sc->alc_flags & ALC_FLAG_FASTETHER) != 0 && 299 reg == MII_EXTSR) 300 return (0); 301 302 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ | 303 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); 304 for (i = ALC_PHY_TIMEOUT; i > 0; i--) { 305 DELAY(5); 306 v = CSR_READ_4(sc, ALC_MDIO); 307 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) 308 break; 309 } 310 311 if (i == 0) { 312 device_printf(sc->alc_dev, "phy read timeout : %d\n", reg); 313 return (0); 314 } 315 316 return ((v & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT); 317} 318 319static uint32_t 320alc_mii_readreg_816x(struct alc_softc *sc, int phy, int reg) 321{ 322 uint32_t clk, v; 323 int i; 324 325 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) 326 clk = MDIO_CLK_25_128; 327 else 328 clk = MDIO_CLK_25_4; 329 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ | 330 MDIO_SUP_PREAMBLE | clk | MDIO_REG_ADDR(reg)); 331 for (i = ALC_PHY_TIMEOUT; i > 0; i--) { 332 DELAY(5); 333 v = CSR_READ_4(sc, ALC_MDIO); 334 if ((v & MDIO_OP_BUSY) == 0) 335 break; 336 } 337 338 if (i == 0) { 339 device_printf(sc->alc_dev, "phy read timeout : %d\n", reg); 340 return (0); 341 } 342 343 return ((v & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT); 344} 345 346static int 347alc_miibus_writereg(device_t dev, int phy, int reg, int val) 348{ 349 struct alc_softc *sc; 350 int v; 351 352 sc = device_get_softc(dev); 353 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 354 v = alc_mii_writereg_816x(sc, phy, reg, val); 355 else 356 v = alc_mii_writereg_813x(sc, phy, reg, val); 357 return (v); 358} 359 360static uint32_t 361alc_mii_writereg_813x(struct alc_softc *sc, int phy, int reg, int val) 362{ 363 uint32_t v; 364 int i; 365 366 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE | 367 (val & MDIO_DATA_MASK) << MDIO_DATA_SHIFT | 368 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); 369 for (i = ALC_PHY_TIMEOUT; i > 0; i--) { 370 DELAY(5); 371 v = CSR_READ_4(sc, ALC_MDIO); 372 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) 373 break; 374 } 375 376 if (i == 0) 377 device_printf(sc->alc_dev, "phy write timeout : %d\n", reg); 378 379 return (0); 380} 381 382static uint32_t 383alc_mii_writereg_816x(struct alc_softc *sc, int phy, int reg, int val) 384{ 385 uint32_t clk, v; 386 int i; 387 388 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) 389 clk = MDIO_CLK_25_128; 390 else 391 clk = MDIO_CLK_25_4; 392 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE | 393 ((val & MDIO_DATA_MASK) << MDIO_DATA_SHIFT) | MDIO_REG_ADDR(reg) | 394 MDIO_SUP_PREAMBLE | clk); 395 for (i = ALC_PHY_TIMEOUT; i > 0; i--) { 396 DELAY(5); 397 v = CSR_READ_4(sc, ALC_MDIO); 398 if ((v & MDIO_OP_BUSY) == 0) 399 break; 400 } 401 402 if (i == 0) 403 device_printf(sc->alc_dev, "phy write timeout : %d\n", reg); 404 405 return (0); 406} 407 408static void 409alc_miibus_statchg(device_t dev) 410{ 411 struct alc_softc *sc; 412 struct mii_data *mii; 413 struct ifnet *ifp; 414 uint32_t reg; 415 416 sc = device_get_softc(dev); 417 418 mii = device_get_softc(sc->alc_miibus); 419 ifp = sc->alc_ifp; 420 if (mii == NULL || ifp == NULL || 421 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 422 return; 423 424 sc->alc_flags &= ~ALC_FLAG_LINK; 425 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 426 (IFM_ACTIVE | IFM_AVALID)) { 427 switch (IFM_SUBTYPE(mii->mii_media_active)) { 428 case IFM_10_T: 429 case IFM_100_TX: 430 sc->alc_flags |= ALC_FLAG_LINK; 431 break; 432 case IFM_1000_T: 433 if ((sc->alc_flags & ALC_FLAG_FASTETHER) == 0) 434 sc->alc_flags |= ALC_FLAG_LINK; 435 break; 436 default: 437 break; 438 } 439 } 440 /* Stop Rx/Tx MACs. */ 441 alc_stop_mac(sc); 442 443 /* Program MACs with resolved speed/duplex/flow-control. */ 444 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) { 445 alc_start_queue(sc); 446 alc_mac_config(sc); 447 /* Re-enable Tx/Rx MACs. */ 448 reg = CSR_READ_4(sc, ALC_MAC_CFG); 449 reg |= MAC_CFG_TX_ENB | MAC_CFG_RX_ENB; 450 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 451 } 452 alc_aspm(sc, 0, IFM_SUBTYPE(mii->mii_media_active)); 453 alc_dsp_fixup(sc, IFM_SUBTYPE(mii->mii_media_active)); 454} 455 456static uint32_t 457alc_miidbg_readreg(struct alc_softc *sc, int reg) 458{ 459 460 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, ALC_MII_DBG_ADDR, 461 reg); 462 return (alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr, 463 ALC_MII_DBG_DATA)); 464} 465 466static uint32_t 467alc_miidbg_writereg(struct alc_softc *sc, int reg, int val) 468{ 469 470 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, ALC_MII_DBG_ADDR, 471 reg); 472 return (alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 473 ALC_MII_DBG_DATA, val)); 474} 475 476static uint32_t 477alc_miiext_readreg(struct alc_softc *sc, int devaddr, int reg) 478{ 479 uint32_t clk, v; 480 int i; 481 482 CSR_WRITE_4(sc, ALC_EXT_MDIO, EXT_MDIO_REG(reg) | 483 EXT_MDIO_DEVADDR(devaddr)); 484 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) 485 clk = MDIO_CLK_25_128; 486 else 487 clk = MDIO_CLK_25_4; 488 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ | 489 MDIO_SUP_PREAMBLE | clk | MDIO_MODE_EXT); 490 for (i = ALC_PHY_TIMEOUT; i > 0; i--) { 491 DELAY(5); 492 v = CSR_READ_4(sc, ALC_MDIO); 493 if ((v & MDIO_OP_BUSY) == 0) 494 break; 495 } 496 497 if (i == 0) { 498 device_printf(sc->alc_dev, "phy ext read timeout : %d, %d\n", 499 devaddr, reg); 500 return (0); 501 } 502 503 return ((v & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT); 504} 505 506static uint32_t 507alc_miiext_writereg(struct alc_softc *sc, int devaddr, int reg, int val) 508{ 509 uint32_t clk, v; 510 int i; 511 512 CSR_WRITE_4(sc, ALC_EXT_MDIO, EXT_MDIO_REG(reg) | 513 EXT_MDIO_DEVADDR(devaddr)); 514 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) 515 clk = MDIO_CLK_25_128; 516 else 517 clk = MDIO_CLK_25_4; 518 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE | 519 ((val & MDIO_DATA_MASK) << MDIO_DATA_SHIFT) | 520 MDIO_SUP_PREAMBLE | clk | MDIO_MODE_EXT); 521 for (i = ALC_PHY_TIMEOUT; i > 0; i--) { 522 DELAY(5); 523 v = CSR_READ_4(sc, ALC_MDIO); 524 if ((v & MDIO_OP_BUSY) == 0) 525 break; 526 } 527 528 if (i == 0) 529 device_printf(sc->alc_dev, "phy ext write timeout : %d, %d\n", 530 devaddr, reg); 531 532 return (0); 533} 534 535static void 536alc_dsp_fixup(struct alc_softc *sc, int media) 537{ 538 uint16_t agc, len, val; 539 540 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 541 return; 542 if (AR816X_REV(sc->alc_rev) >= AR816X_REV_C0) 543 return; 544 545 /* 546 * Vendor PHY magic. 547 * 1000BT/AZ, wrong cable length 548 */ 549 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) { 550 len = alc_miiext_readreg(sc, MII_EXT_PCS, MII_EXT_CLDCTL6); 551 len = (len >> EXT_CLDCTL6_CAB_LEN_SHIFT) & 552 EXT_CLDCTL6_CAB_LEN_MASK; 553 agc = alc_miidbg_readreg(sc, MII_DBG_AGC); 554 agc = (agc >> DBG_AGC_2_VGA_SHIFT) & DBG_AGC_2_VGA_MASK; 555 if ((media == IFM_1000_T && len > EXT_CLDCTL6_CAB_LEN_SHORT1G && 556 agc > DBG_AGC_LONG1G_LIMT) || 557 (media == IFM_100_TX && len > DBG_AGC_LONG100M_LIMT && 558 agc > DBG_AGC_LONG1G_LIMT)) { 559 alc_miidbg_writereg(sc, MII_DBG_AZ_ANADECT, 560 DBG_AZ_ANADECT_LONG); 561 val = alc_miiext_readreg(sc, MII_EXT_ANEG, 562 MII_EXT_ANEG_AFE); 563 val |= ANEG_AFEE_10BT_100M_TH; 564 alc_miiext_writereg(sc, MII_EXT_ANEG, MII_EXT_ANEG_AFE, 565 val); 566 } else { 567 alc_miidbg_writereg(sc, MII_DBG_AZ_ANADECT, 568 DBG_AZ_ANADECT_DEFAULT); 569 val = alc_miiext_readreg(sc, MII_EXT_ANEG, 570 MII_EXT_ANEG_AFE); 571 val &= ~ANEG_AFEE_10BT_100M_TH; 572 alc_miiext_writereg(sc, MII_EXT_ANEG, MII_EXT_ANEG_AFE, 573 val); 574 } 575 if ((sc->alc_flags & ALC_FLAG_LINK_WAR) != 0 && 576 AR816X_REV(sc->alc_rev) == AR816X_REV_B0) { 577 if (media == IFM_1000_T) { 578 /* 579 * Giga link threshold, raise the tolerance of 580 * noise 50%. 581 */ 582 val = alc_miidbg_readreg(sc, MII_DBG_MSE20DB); 583 val &= ~DBG_MSE20DB_TH_MASK; 584 val |= (DBG_MSE20DB_TH_HI << 585 DBG_MSE20DB_TH_SHIFT); 586 alc_miidbg_writereg(sc, MII_DBG_MSE20DB, val); 587 } else if (media == IFM_100_TX) 588 alc_miidbg_writereg(sc, MII_DBG_MSE16DB, 589 DBG_MSE16DB_UP); 590 } 591 } else { 592 val = alc_miiext_readreg(sc, MII_EXT_ANEG, MII_EXT_ANEG_AFE); 593 val &= ~ANEG_AFEE_10BT_100M_TH; 594 alc_miiext_writereg(sc, MII_EXT_ANEG, MII_EXT_ANEG_AFE, val); 595 if ((sc->alc_flags & ALC_FLAG_LINK_WAR) != 0 && 596 AR816X_REV(sc->alc_rev) == AR816X_REV_B0) { 597 alc_miidbg_writereg(sc, MII_DBG_MSE16DB, 598 DBG_MSE16DB_DOWN); 599 val = alc_miidbg_readreg(sc, MII_DBG_MSE20DB); 600 val &= ~DBG_MSE20DB_TH_MASK; 601 val |= (DBG_MSE20DB_TH_DEFAULT << DBG_MSE20DB_TH_SHIFT); 602 alc_miidbg_writereg(sc, MII_DBG_MSE20DB, val); 603 } 604 } 605} 606 607static void 608alc_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 609{ 610 struct alc_softc *sc; 611 struct mii_data *mii; 612 613 sc = ifp->if_softc; 614 ALC_LOCK(sc); 615 if ((ifp->if_flags & IFF_UP) == 0) { 616 ALC_UNLOCK(sc); 617 return; 618 } 619 mii = device_get_softc(sc->alc_miibus); 620 621 mii_pollstat(mii); 622 ifmr->ifm_status = mii->mii_media_status; 623 ifmr->ifm_active = mii->mii_media_active; 624 ALC_UNLOCK(sc); 625} 626 627static int 628alc_mediachange(struct ifnet *ifp) 629{ 630 struct alc_softc *sc; 631 int error; 632 633 sc = ifp->if_softc; 634 ALC_LOCK(sc); 635 error = alc_mediachange_locked(sc); 636 ALC_UNLOCK(sc); 637 638 return (error); 639} 640 641static int 642alc_mediachange_locked(struct alc_softc *sc) 643{ 644 struct mii_data *mii; 645 struct mii_softc *miisc; 646 int error; 647 648 ALC_LOCK_ASSERT(sc); 649 650 mii = device_get_softc(sc->alc_miibus); 651 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 652 PHY_RESET(miisc); 653 error = mii_mediachg(mii); 654 655 return (error); 656} 657 658static struct alc_ident * 659alc_find_ident(device_t dev) 660{ 661 struct alc_ident *ident; 662 uint16_t vendor, devid; 663 664 vendor = pci_get_vendor(dev); 665 devid = pci_get_device(dev); 666 for (ident = alc_ident_table; ident->name != NULL; ident++) { 667 if (vendor == ident->vendorid && devid == ident->deviceid) 668 return (ident); 669 } 670 671 return (NULL); 672} 673 674static int 675alc_probe(device_t dev) 676{ 677 struct alc_ident *ident; 678 679 ident = alc_find_ident(dev); 680 if (ident != NULL) { 681 device_set_desc(dev, ident->name); 682 return (BUS_PROBE_DEFAULT); 683 } 684 685 return (ENXIO); 686} 687 688static void 689alc_get_macaddr(struct alc_softc *sc) 690{ 691 692 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 693 alc_get_macaddr_816x(sc); 694 else 695 alc_get_macaddr_813x(sc); 696} 697 698static void 699alc_get_macaddr_813x(struct alc_softc *sc) 700{ 701 uint32_t opt; 702 uint16_t val; 703 int eeprom, i; 704 705 eeprom = 0; 706 opt = CSR_READ_4(sc, ALC_OPT_CFG); 707 if ((CSR_READ_4(sc, ALC_MASTER_CFG) & MASTER_OTP_SEL) != 0 && 708 (CSR_READ_4(sc, ALC_TWSI_DEBUG) & TWSI_DEBUG_DEV_EXIST) != 0) { 709 /* 710 * EEPROM found, let TWSI reload EEPROM configuration. 711 * This will set ethernet address of controller. 712 */ 713 eeprom++; 714 switch (sc->alc_ident->deviceid) { 715 case DEVICEID_ATHEROS_AR8131: 716 case DEVICEID_ATHEROS_AR8132: 717 if ((opt & OPT_CFG_CLK_ENB) == 0) { 718 opt |= OPT_CFG_CLK_ENB; 719 CSR_WRITE_4(sc, ALC_OPT_CFG, opt); 720 CSR_READ_4(sc, ALC_OPT_CFG); 721 DELAY(1000); 722 } 723 break; 724 case DEVICEID_ATHEROS_AR8151: 725 case DEVICEID_ATHEROS_AR8151_V2: 726 case DEVICEID_ATHEROS_AR8152_B: 727 case DEVICEID_ATHEROS_AR8152_B2: 728 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 729 ALC_MII_DBG_ADDR, 0x00); 730 val = alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr, 731 ALC_MII_DBG_DATA); 732 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 733 ALC_MII_DBG_DATA, val & 0xFF7F); 734 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 735 ALC_MII_DBG_ADDR, 0x3B); 736 val = alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr, 737 ALC_MII_DBG_DATA); 738 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 739 ALC_MII_DBG_DATA, val | 0x0008); 740 DELAY(20); 741 break; 742 } 743 744 CSR_WRITE_4(sc, ALC_LTSSM_ID_CFG, 745 CSR_READ_4(sc, ALC_LTSSM_ID_CFG) & ~LTSSM_ID_WRO_ENB); 746 CSR_WRITE_4(sc, ALC_WOL_CFG, 0); 747 CSR_READ_4(sc, ALC_WOL_CFG); 748 749 CSR_WRITE_4(sc, ALC_TWSI_CFG, CSR_READ_4(sc, ALC_TWSI_CFG) | 750 TWSI_CFG_SW_LD_START); 751 for (i = 100; i > 0; i--) { 752 DELAY(1000); 753 if ((CSR_READ_4(sc, ALC_TWSI_CFG) & 754 TWSI_CFG_SW_LD_START) == 0) 755 break; 756 } 757 if (i == 0) 758 device_printf(sc->alc_dev, 759 "reloading EEPROM timeout!\n"); 760 } else { 761 if (bootverbose) 762 device_printf(sc->alc_dev, "EEPROM not found!\n"); 763 } 764 if (eeprom != 0) { 765 switch (sc->alc_ident->deviceid) { 766 case DEVICEID_ATHEROS_AR8131: 767 case DEVICEID_ATHEROS_AR8132: 768 if ((opt & OPT_CFG_CLK_ENB) != 0) { 769 opt &= ~OPT_CFG_CLK_ENB; 770 CSR_WRITE_4(sc, ALC_OPT_CFG, opt); 771 CSR_READ_4(sc, ALC_OPT_CFG); 772 DELAY(1000); 773 } 774 break; 775 case DEVICEID_ATHEROS_AR8151: 776 case DEVICEID_ATHEROS_AR8151_V2: 777 case DEVICEID_ATHEROS_AR8152_B: 778 case DEVICEID_ATHEROS_AR8152_B2: 779 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 780 ALC_MII_DBG_ADDR, 0x00); 781 val = alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr, 782 ALC_MII_DBG_DATA); 783 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 784 ALC_MII_DBG_DATA, val | 0x0080); 785 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 786 ALC_MII_DBG_ADDR, 0x3B); 787 val = alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr, 788 ALC_MII_DBG_DATA); 789 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 790 ALC_MII_DBG_DATA, val & 0xFFF7); 791 DELAY(20); 792 break; 793 } 794 } 795 796 alc_get_macaddr_par(sc); 797} 798 799static void 800alc_get_macaddr_816x(struct alc_softc *sc) 801{ 802 uint32_t reg; 803 int i, reloaded; 804 805 reloaded = 0; 806 /* Try to reload station address via TWSI. */ 807 for (i = 100; i > 0; i--) { 808 reg = CSR_READ_4(sc, ALC_SLD); 809 if ((reg & (SLD_PROGRESS | SLD_START)) == 0) 810 break; 811 DELAY(1000); 812 } 813 if (i != 0) { 814 CSR_WRITE_4(sc, ALC_SLD, reg | SLD_START); 815 for (i = 100; i > 0; i--) { 816 DELAY(1000); 817 reg = CSR_READ_4(sc, ALC_SLD); 818 if ((reg & SLD_START) == 0) 819 break; 820 } 821 if (i != 0) 822 reloaded++; 823 else if (bootverbose) 824 device_printf(sc->alc_dev, 825 "reloading station address via TWSI timed out!\n"); 826 } 827 828 /* Try to reload station address from EEPROM or FLASH. */ 829 if (reloaded == 0) { 830 reg = CSR_READ_4(sc, ALC_EEPROM_LD); 831 if ((reg & (EEPROM_LD_EEPROM_EXIST | 832 EEPROM_LD_FLASH_EXIST)) != 0) { 833 for (i = 100; i > 0; i--) { 834 reg = CSR_READ_4(sc, ALC_EEPROM_LD); 835 if ((reg & (EEPROM_LD_PROGRESS | 836 EEPROM_LD_START)) == 0) 837 break; 838 DELAY(1000); 839 } 840 if (i != 0) { 841 CSR_WRITE_4(sc, ALC_EEPROM_LD, reg | 842 EEPROM_LD_START); 843 for (i = 100; i > 0; i--) { 844 DELAY(1000); 845 reg = CSR_READ_4(sc, ALC_EEPROM_LD); 846 if ((reg & EEPROM_LD_START) == 0) 847 break; 848 } 849 } else if (bootverbose) 850 device_printf(sc->alc_dev, 851 "reloading EEPROM/FLASH timed out!\n"); 852 } 853 } 854 855 alc_get_macaddr_par(sc); 856} 857 858static void 859alc_get_macaddr_par(struct alc_softc *sc) 860{ 861 uint32_t ea[2]; 862 863 ea[0] = CSR_READ_4(sc, ALC_PAR0); 864 ea[1] = CSR_READ_4(sc, ALC_PAR1); 865 sc->alc_eaddr[0] = (ea[1] >> 8) & 0xFF; 866 sc->alc_eaddr[1] = (ea[1] >> 0) & 0xFF; 867 sc->alc_eaddr[2] = (ea[0] >> 24) & 0xFF; 868 sc->alc_eaddr[3] = (ea[0] >> 16) & 0xFF; 869 sc->alc_eaddr[4] = (ea[0] >> 8) & 0xFF; 870 sc->alc_eaddr[5] = (ea[0] >> 0) & 0xFF; 871} 872 873static void 874alc_disable_l0s_l1(struct alc_softc *sc) 875{ 876 uint32_t pmcfg; 877 878 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 879 /* Another magic from vendor. */ 880 pmcfg = CSR_READ_4(sc, ALC_PM_CFG); 881 pmcfg &= ~(PM_CFG_L1_ENTRY_TIMER_MASK | PM_CFG_CLK_SWH_L1 | 882 PM_CFG_ASPM_L0S_ENB | PM_CFG_ASPM_L1_ENB | 883 PM_CFG_MAC_ASPM_CHK | PM_CFG_SERDES_PD_EX_L1); 884 pmcfg |= PM_CFG_SERDES_BUDS_RX_L1_ENB | 885 PM_CFG_SERDES_PLL_L1_ENB | PM_CFG_SERDES_L1_ENB; 886 CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg); 887 } 888} 889 890static void 891alc_phy_reset(struct alc_softc *sc) 892{ 893 894 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 895 alc_phy_reset_816x(sc); 896 else 897 alc_phy_reset_813x(sc); 898} 899 900static void 901alc_phy_reset_813x(struct alc_softc *sc) 902{ 903 uint16_t data; 904 905 /* Reset magic from Linux. */ 906 CSR_WRITE_2(sc, ALC_GPHY_CFG, GPHY_CFG_SEL_ANA_RESET); 907 CSR_READ_2(sc, ALC_GPHY_CFG); 908 DELAY(10 * 1000); 909 910 CSR_WRITE_2(sc, ALC_GPHY_CFG, GPHY_CFG_EXT_RESET | 911 GPHY_CFG_SEL_ANA_RESET); 912 CSR_READ_2(sc, ALC_GPHY_CFG); 913 DELAY(10 * 1000); 914 915 /* DSP fixup, Vendor magic. */ 916 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B) { 917 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 918 ALC_MII_DBG_ADDR, 0x000A); 919 data = alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr, 920 ALC_MII_DBG_DATA); 921 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 922 ALC_MII_DBG_DATA, data & 0xDFFF); 923 } 924 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151 || 925 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151_V2 || 926 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B || 927 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B2) { 928 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 929 ALC_MII_DBG_ADDR, 0x003B); 930 data = alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr, 931 ALC_MII_DBG_DATA); 932 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 933 ALC_MII_DBG_DATA, data & 0xFFF7); 934 DELAY(20 * 1000); 935 } 936 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151) { 937 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 938 ALC_MII_DBG_ADDR, 0x0029); 939 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 940 ALC_MII_DBG_DATA, 0x929D); 941 } 942 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8131 || 943 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8132 || 944 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151_V2 || 945 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B2) { 946 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 947 ALC_MII_DBG_ADDR, 0x0029); 948 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 949 ALC_MII_DBG_DATA, 0xB6DD); 950 } 951 952 /* Load DSP codes, vendor magic. */ 953 data = ANA_LOOP_SEL_10BT | ANA_EN_MASK_TB | ANA_EN_10BT_IDLE | 954 ((1 << ANA_INTERVAL_SEL_TIMER_SHIFT) & ANA_INTERVAL_SEL_TIMER_MASK); 955 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 956 ALC_MII_DBG_ADDR, MII_ANA_CFG18); 957 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 958 ALC_MII_DBG_DATA, data); 959 960 data = ((2 << ANA_SERDES_CDR_BW_SHIFT) & ANA_SERDES_CDR_BW_MASK) | 961 ANA_SERDES_EN_DEEM | ANA_SERDES_SEL_HSP | ANA_SERDES_EN_PLL | 962 ANA_SERDES_EN_LCKDT; 963 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 964 ALC_MII_DBG_ADDR, MII_ANA_CFG5); 965 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 966 ALC_MII_DBG_DATA, data); 967 968 data = ((44 << ANA_LONG_CABLE_TH_100_SHIFT) & 969 ANA_LONG_CABLE_TH_100_MASK) | 970 ((33 << ANA_SHORT_CABLE_TH_100_SHIFT) & 971 ANA_SHORT_CABLE_TH_100_SHIFT) | 972 ANA_BP_BAD_LINK_ACCUM | ANA_BP_SMALL_BW; 973 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 974 ALC_MII_DBG_ADDR, MII_ANA_CFG54); 975 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 976 ALC_MII_DBG_DATA, data); 977 978 data = ((11 << ANA_IECHO_ADJ_3_SHIFT) & ANA_IECHO_ADJ_3_MASK) | 979 ((11 << ANA_IECHO_ADJ_2_SHIFT) & ANA_IECHO_ADJ_2_MASK) | 980 ((8 << ANA_IECHO_ADJ_1_SHIFT) & ANA_IECHO_ADJ_1_MASK) | 981 ((8 << ANA_IECHO_ADJ_0_SHIFT) & ANA_IECHO_ADJ_0_MASK); 982 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 983 ALC_MII_DBG_ADDR, MII_ANA_CFG4); 984 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 985 ALC_MII_DBG_DATA, data); 986 987 data = ((7 & ANA_MANUL_SWICH_ON_SHIFT) & ANA_MANUL_SWICH_ON_MASK) | 988 ANA_RESTART_CAL | ANA_MAN_ENABLE | ANA_SEL_HSP | ANA_EN_HB | 989 ANA_OEN_125M; 990 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 991 ALC_MII_DBG_ADDR, MII_ANA_CFG0); 992 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 993 ALC_MII_DBG_DATA, data); 994 DELAY(1000); 995 996 /* Disable hibernation. */ 997 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, ALC_MII_DBG_ADDR, 998 0x0029); 999 data = alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr, 1000 ALC_MII_DBG_DATA); 1001 data &= ~0x8000; 1002 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, ALC_MII_DBG_DATA, 1003 data); 1004 1005 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, ALC_MII_DBG_ADDR, 1006 0x000B); 1007 data = alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr, 1008 ALC_MII_DBG_DATA); 1009 data &= ~0x8000; 1010 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, ALC_MII_DBG_DATA, 1011 data); 1012} 1013 1014static void 1015alc_phy_reset_816x(struct alc_softc *sc) 1016{ 1017 uint32_t val; 1018 1019 val = CSR_READ_4(sc, ALC_GPHY_CFG); 1020 val &= ~(GPHY_CFG_EXT_RESET | GPHY_CFG_LED_MODE | 1021 GPHY_CFG_GATE_25M_ENB | GPHY_CFG_PHY_IDDQ | GPHY_CFG_PHY_PLL_ON | 1022 GPHY_CFG_PWDOWN_HW | GPHY_CFG_100AB_ENB); 1023 val |= GPHY_CFG_SEL_ANA_RESET; 1024#ifdef notyet 1025 val |= GPHY_CFG_HIB_PULSE | GPHY_CFG_HIB_EN | GPHY_CFG_SEL_ANA_RESET; 1026#else 1027 /* Disable PHY hibernation. */ 1028 val &= ~(GPHY_CFG_HIB_PULSE | GPHY_CFG_HIB_EN); 1029#endif 1030 CSR_WRITE_4(sc, ALC_GPHY_CFG, val); 1031 DELAY(10); 1032 CSR_WRITE_4(sc, ALC_GPHY_CFG, val | GPHY_CFG_EXT_RESET); 1033 DELAY(800); 1034 1035 /* Vendor PHY magic. */ 1036#ifdef notyet 1037 alc_miidbg_writereg(sc, MII_DBG_LEGCYPS, DBG_LEGCYPS_DEFAULT); 1038 alc_miidbg_writereg(sc, MII_DBG_SYSMODCTL, DBG_SYSMODCTL_DEFAULT); 1039 alc_miiext_writereg(sc, MII_EXT_PCS, MII_EXT_VDRVBIAS, 1040 EXT_VDRVBIAS_DEFAULT); 1041#else 1042 /* Disable PHY hibernation. */ 1043 alc_miidbg_writereg(sc, MII_DBG_LEGCYPS, 1044 DBG_LEGCYPS_DEFAULT & ~DBG_LEGCYPS_ENB); 1045 alc_miidbg_writereg(sc, MII_DBG_HIBNEG, 1046 DBG_HIBNEG_DEFAULT & ~(DBG_HIBNEG_PSHIB_EN | DBG_HIBNEG_HIB_PULSE)); 1047 alc_miidbg_writereg(sc, MII_DBG_GREENCFG, DBG_GREENCFG_DEFAULT); 1048#endif 1049 1050 /* XXX Disable EEE. */ 1051 val = CSR_READ_4(sc, ALC_LPI_CTL); 1052 val &= ~LPI_CTL_ENB; 1053 CSR_WRITE_4(sc, ALC_LPI_CTL, val); 1054 alc_miiext_writereg(sc, MII_EXT_ANEG, MII_EXT_ANEG_LOCAL_EEEADV, 0); 1055 1056 /* PHY power saving. */ 1057 alc_miidbg_writereg(sc, MII_DBG_TST10BTCFG, DBG_TST10BTCFG_DEFAULT); 1058 alc_miidbg_writereg(sc, MII_DBG_SRDSYSMOD, DBG_SRDSYSMOD_DEFAULT); 1059 alc_miidbg_writereg(sc, MII_DBG_TST100BTCFG, DBG_TST100BTCFG_DEFAULT); 1060 alc_miidbg_writereg(sc, MII_DBG_ANACTL, DBG_ANACTL_DEFAULT); 1061 val = alc_miidbg_readreg(sc, MII_DBG_GREENCFG2); 1062 val &= ~DBG_GREENCFG2_GATE_DFSE_EN; 1063 alc_miidbg_writereg(sc, MII_DBG_GREENCFG2, val); 1064 1065 /* RTL8139C, 120m issue. */ 1066 alc_miiext_writereg(sc, MII_EXT_ANEG, MII_EXT_ANEG_NLP78, 1067 ANEG_NLP78_120M_DEFAULT); 1068 alc_miiext_writereg(sc, MII_EXT_ANEG, MII_EXT_ANEG_S3DIG10, 1069 ANEG_S3DIG10_DEFAULT); 1070 1071 if ((sc->alc_flags & ALC_FLAG_LINK_WAR) != 0) { 1072 /* Turn off half amplitude. */ 1073 val = alc_miiext_readreg(sc, MII_EXT_PCS, MII_EXT_CLDCTL3); 1074 val |= EXT_CLDCTL3_BP_CABLE1TH_DET_GT; 1075 alc_miiext_writereg(sc, MII_EXT_PCS, MII_EXT_CLDCTL3, val); 1076 /* Turn off Green feature. */ 1077 val = alc_miidbg_readreg(sc, MII_DBG_GREENCFG2); 1078 val |= DBG_GREENCFG2_BP_GREEN; 1079 alc_miidbg_writereg(sc, MII_DBG_GREENCFG2, val); 1080 /* Turn off half bias. */ 1081 val = alc_miiext_readreg(sc, MII_EXT_PCS, MII_EXT_CLDCTL5); 1082 val |= EXT_CLDCTL5_BP_VD_HLFBIAS; 1083 alc_miiext_writereg(sc, MII_EXT_PCS, MII_EXT_CLDCTL5, val); 1084 } 1085} 1086 1087static void 1088alc_phy_down(struct alc_softc *sc) 1089{ 1090 uint32_t gphy; 1091 1092 switch (sc->alc_ident->deviceid) { 1093 case DEVICEID_ATHEROS_AR8161: 1094 case DEVICEID_ATHEROS_E2200: 1095 case DEVICEID_ATHEROS_E2400: 1096 case DEVICEID_ATHEROS_E2500: 1097 case DEVICEID_ATHEROS_AR8162: 1098 case DEVICEID_ATHEROS_AR8171: 1099 case DEVICEID_ATHEROS_AR8172: 1100 gphy = CSR_READ_4(sc, ALC_GPHY_CFG); 1101 gphy &= ~(GPHY_CFG_EXT_RESET | GPHY_CFG_LED_MODE | 1102 GPHY_CFG_100AB_ENB | GPHY_CFG_PHY_PLL_ON); 1103 gphy |= GPHY_CFG_HIB_EN | GPHY_CFG_HIB_PULSE | 1104 GPHY_CFG_SEL_ANA_RESET; 1105 gphy |= GPHY_CFG_PHY_IDDQ | GPHY_CFG_PWDOWN_HW; 1106 CSR_WRITE_4(sc, ALC_GPHY_CFG, gphy); 1107 break; 1108 case DEVICEID_ATHEROS_AR8151: 1109 case DEVICEID_ATHEROS_AR8151_V2: 1110 case DEVICEID_ATHEROS_AR8152_B: 1111 case DEVICEID_ATHEROS_AR8152_B2: 1112 /* 1113 * GPHY power down caused more problems on AR8151 v2.0. 1114 * When driver is reloaded after GPHY power down, 1115 * accesses to PHY/MAC registers hung the system. Only 1116 * cold boot recovered from it. I'm not sure whether 1117 * AR8151 v1.0 also requires this one though. I don't 1118 * have AR8151 v1.0 controller in hand. 1119 * The only option left is to isolate the PHY and 1120 * initiates power down the PHY which in turn saves 1121 * more power when driver is unloaded. 1122 */ 1123 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 1124 MII_BMCR, BMCR_ISO | BMCR_PDOWN); 1125 break; 1126 default: 1127 /* Force PHY down. */ 1128 CSR_WRITE_2(sc, ALC_GPHY_CFG, GPHY_CFG_EXT_RESET | 1129 GPHY_CFG_SEL_ANA_RESET | GPHY_CFG_PHY_IDDQ | 1130 GPHY_CFG_PWDOWN_HW); 1131 DELAY(1000); 1132 break; 1133 } 1134} 1135 1136static void 1137alc_aspm(struct alc_softc *sc, int init, int media) 1138{ 1139 1140 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 1141 alc_aspm_816x(sc, init); 1142 else 1143 alc_aspm_813x(sc, media); 1144} 1145 1146static void 1147alc_aspm_813x(struct alc_softc *sc, int media) 1148{ 1149 uint32_t pmcfg; 1150 uint16_t linkcfg; 1151 1152 if ((sc->alc_flags & ALC_FLAG_LINK) == 0) 1153 return; 1154 1155 pmcfg = CSR_READ_4(sc, ALC_PM_CFG); 1156 if ((sc->alc_flags & (ALC_FLAG_APS | ALC_FLAG_PCIE)) == 1157 (ALC_FLAG_APS | ALC_FLAG_PCIE)) 1158 linkcfg = CSR_READ_2(sc, sc->alc_expcap + 1159 PCIER_LINK_CTL); 1160 else 1161 linkcfg = 0; 1162 pmcfg &= ~PM_CFG_SERDES_PD_EX_L1; 1163 pmcfg &= ~(PM_CFG_L1_ENTRY_TIMER_MASK | PM_CFG_LCKDET_TIMER_MASK); 1164 pmcfg |= PM_CFG_MAC_ASPM_CHK; 1165 pmcfg |= (PM_CFG_LCKDET_TIMER_DEFAULT << PM_CFG_LCKDET_TIMER_SHIFT); 1166 pmcfg &= ~(PM_CFG_ASPM_L1_ENB | PM_CFG_ASPM_L0S_ENB); 1167 1168 if ((sc->alc_flags & ALC_FLAG_APS) != 0) { 1169 /* Disable extended sync except AR8152 B v1.0 */ 1170 linkcfg &= ~PCIEM_LINK_CTL_EXTENDED_SYNC; 1171 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B && 1172 sc->alc_rev == ATHEROS_AR8152_B_V10) 1173 linkcfg |= PCIEM_LINK_CTL_EXTENDED_SYNC; 1174 CSR_WRITE_2(sc, sc->alc_expcap + PCIER_LINK_CTL, 1175 linkcfg); 1176 pmcfg &= ~(PM_CFG_EN_BUFS_RX_L0S | PM_CFG_SA_DLY_ENB | 1177 PM_CFG_HOTRST); 1178 pmcfg |= (PM_CFG_L1_ENTRY_TIMER_DEFAULT << 1179 PM_CFG_L1_ENTRY_TIMER_SHIFT); 1180 pmcfg &= ~PM_CFG_PM_REQ_TIMER_MASK; 1181 pmcfg |= (PM_CFG_PM_REQ_TIMER_DEFAULT << 1182 PM_CFG_PM_REQ_TIMER_SHIFT); 1183 pmcfg |= PM_CFG_SERDES_PD_EX_L1 | PM_CFG_PCIE_RECV; 1184 } 1185 1186 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) { 1187 if ((sc->alc_flags & ALC_FLAG_L0S) != 0) 1188 pmcfg |= PM_CFG_ASPM_L0S_ENB; 1189 if ((sc->alc_flags & ALC_FLAG_L1S) != 0) 1190 pmcfg |= PM_CFG_ASPM_L1_ENB; 1191 if ((sc->alc_flags & ALC_FLAG_APS) != 0) { 1192 if (sc->alc_ident->deviceid == 1193 DEVICEID_ATHEROS_AR8152_B) 1194 pmcfg &= ~PM_CFG_ASPM_L0S_ENB; 1195 pmcfg &= ~(PM_CFG_SERDES_L1_ENB | 1196 PM_CFG_SERDES_PLL_L1_ENB | 1197 PM_CFG_SERDES_BUDS_RX_L1_ENB); 1198 pmcfg |= PM_CFG_CLK_SWH_L1; 1199 if (media == IFM_100_TX || media == IFM_1000_T) { 1200 pmcfg &= ~PM_CFG_L1_ENTRY_TIMER_MASK; 1201 switch (sc->alc_ident->deviceid) { 1202 case DEVICEID_ATHEROS_AR8152_B: 1203 pmcfg |= (7 << 1204 PM_CFG_L1_ENTRY_TIMER_SHIFT); 1205 break; 1206 case DEVICEID_ATHEROS_AR8152_B2: 1207 case DEVICEID_ATHEROS_AR8151_V2: 1208 pmcfg |= (4 << 1209 PM_CFG_L1_ENTRY_TIMER_SHIFT); 1210 break; 1211 default: 1212 pmcfg |= (15 << 1213 PM_CFG_L1_ENTRY_TIMER_SHIFT); 1214 break; 1215 } 1216 } 1217 } else { 1218 pmcfg |= PM_CFG_SERDES_L1_ENB | 1219 PM_CFG_SERDES_PLL_L1_ENB | 1220 PM_CFG_SERDES_BUDS_RX_L1_ENB; 1221 pmcfg &= ~(PM_CFG_CLK_SWH_L1 | 1222 PM_CFG_ASPM_L1_ENB | PM_CFG_ASPM_L0S_ENB); 1223 } 1224 } else { 1225 pmcfg &= ~(PM_CFG_SERDES_BUDS_RX_L1_ENB | PM_CFG_SERDES_L1_ENB | 1226 PM_CFG_SERDES_PLL_L1_ENB); 1227 pmcfg |= PM_CFG_CLK_SWH_L1; 1228 if ((sc->alc_flags & ALC_FLAG_L1S) != 0) 1229 pmcfg |= PM_CFG_ASPM_L1_ENB; 1230 } 1231 CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg); 1232} 1233 1234static void 1235alc_aspm_816x(struct alc_softc *sc, int init) 1236{ 1237 uint32_t pmcfg; 1238 1239 pmcfg = CSR_READ_4(sc, ALC_PM_CFG); 1240 pmcfg &= ~PM_CFG_L1_ENTRY_TIMER_816X_MASK; 1241 pmcfg |= PM_CFG_L1_ENTRY_TIMER_816X_DEFAULT; 1242 pmcfg &= ~PM_CFG_PM_REQ_TIMER_MASK; 1243 pmcfg |= PM_CFG_PM_REQ_TIMER_816X_DEFAULT; 1244 pmcfg &= ~PM_CFG_LCKDET_TIMER_MASK; 1245 pmcfg |= PM_CFG_LCKDET_TIMER_DEFAULT; 1246 pmcfg |= PM_CFG_SERDES_PD_EX_L1 | PM_CFG_CLK_SWH_L1 | PM_CFG_PCIE_RECV; 1247 pmcfg &= ~(PM_CFG_RX_L1_AFTER_L0S | PM_CFG_TX_L1_AFTER_L0S | 1248 PM_CFG_ASPM_L1_ENB | PM_CFG_ASPM_L0S_ENB | 1249 PM_CFG_SERDES_L1_ENB | PM_CFG_SERDES_PLL_L1_ENB | 1250 PM_CFG_SERDES_BUDS_RX_L1_ENB | PM_CFG_SA_DLY_ENB | 1251 PM_CFG_MAC_ASPM_CHK | PM_CFG_HOTRST); 1252 if (AR816X_REV(sc->alc_rev) <= AR816X_REV_A1 && 1253 (sc->alc_rev & 0x01) != 0) 1254 pmcfg |= PM_CFG_SERDES_L1_ENB | PM_CFG_SERDES_PLL_L1_ENB; 1255 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) { 1256 /* Link up, enable both L0s, L1s. */ 1257 pmcfg |= PM_CFG_ASPM_L0S_ENB | PM_CFG_ASPM_L1_ENB | 1258 PM_CFG_MAC_ASPM_CHK; 1259 } else { 1260 if (init != 0) 1261 pmcfg |= PM_CFG_ASPM_L0S_ENB | PM_CFG_ASPM_L1_ENB | 1262 PM_CFG_MAC_ASPM_CHK; 1263 else if ((sc->alc_ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 1264 pmcfg |= PM_CFG_ASPM_L1_ENB | PM_CFG_MAC_ASPM_CHK; 1265 } 1266 CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg); 1267} 1268 1269static void 1270alc_init_pcie(struct alc_softc *sc) 1271{ 1272 const char *aspm_state[] = { "L0s/L1", "L0s", "L1", "L0s/L1" }; 1273 uint32_t cap, ctl, val; 1274 int state; 1275 1276 /* Clear data link and flow-control protocol error. */ 1277 val = CSR_READ_4(sc, ALC_PEX_UNC_ERR_SEV); 1278 val &= ~(PEX_UNC_ERR_SEV_DLP | PEX_UNC_ERR_SEV_FCP); 1279 CSR_WRITE_4(sc, ALC_PEX_UNC_ERR_SEV, val); 1280 1281 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 1282 CSR_WRITE_4(sc, ALC_LTSSM_ID_CFG, 1283 CSR_READ_4(sc, ALC_LTSSM_ID_CFG) & ~LTSSM_ID_WRO_ENB); 1284 CSR_WRITE_4(sc, ALC_PCIE_PHYMISC, 1285 CSR_READ_4(sc, ALC_PCIE_PHYMISC) | 1286 PCIE_PHYMISC_FORCE_RCV_DET); 1287 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B && 1288 sc->alc_rev == ATHEROS_AR8152_B_V10) { 1289 val = CSR_READ_4(sc, ALC_PCIE_PHYMISC2); 1290 val &= ~(PCIE_PHYMISC2_SERDES_CDR_MASK | 1291 PCIE_PHYMISC2_SERDES_TH_MASK); 1292 val |= 3 << PCIE_PHYMISC2_SERDES_CDR_SHIFT; 1293 val |= 3 << PCIE_PHYMISC2_SERDES_TH_SHIFT; 1294 CSR_WRITE_4(sc, ALC_PCIE_PHYMISC2, val); 1295 } 1296 /* Disable ASPM L0S and L1. */ 1297 cap = CSR_READ_2(sc, sc->alc_expcap + PCIER_LINK_CAP); 1298 if ((cap & PCIEM_LINK_CAP_ASPM) != 0) { 1299 ctl = CSR_READ_2(sc, sc->alc_expcap + PCIER_LINK_CTL); 1300 if ((ctl & PCIEM_LINK_CTL_RCB) != 0) 1301 sc->alc_rcb = DMA_CFG_RCB_128; 1302 if (bootverbose) 1303 device_printf(sc->alc_dev, "RCB %u bytes\n", 1304 sc->alc_rcb == DMA_CFG_RCB_64 ? 64 : 128); 1305 state = ctl & PCIEM_LINK_CTL_ASPMC; 1306 if (state & PCIEM_LINK_CTL_ASPMC_L0S) 1307 sc->alc_flags |= ALC_FLAG_L0S; 1308 if (state & PCIEM_LINK_CTL_ASPMC_L1) 1309 sc->alc_flags |= ALC_FLAG_L1S; 1310 if (bootverbose) 1311 device_printf(sc->alc_dev, "ASPM %s %s\n", 1312 aspm_state[state], 1313 state == 0 ? "disabled" : "enabled"); 1314 alc_disable_l0s_l1(sc); 1315 } else { 1316 if (bootverbose) 1317 device_printf(sc->alc_dev, 1318 "no ASPM support\n"); 1319 } 1320 } else { 1321 val = CSR_READ_4(sc, ALC_PDLL_TRNS1); 1322 val &= ~PDLL_TRNS1_D3PLLOFF_ENB; 1323 CSR_WRITE_4(sc, ALC_PDLL_TRNS1, val); 1324 val = CSR_READ_4(sc, ALC_MASTER_CFG); 1325 if (AR816X_REV(sc->alc_rev) <= AR816X_REV_A1 && 1326 (sc->alc_rev & 0x01) != 0) { 1327 if ((val & MASTER_WAKEN_25M) == 0 || 1328 (val & MASTER_CLK_SEL_DIS) == 0) { 1329 val |= MASTER_WAKEN_25M | MASTER_CLK_SEL_DIS; 1330 CSR_WRITE_4(sc, ALC_MASTER_CFG, val); 1331 } 1332 } else { 1333 if ((val & MASTER_WAKEN_25M) == 0 || 1334 (val & MASTER_CLK_SEL_DIS) != 0) { 1335 val |= MASTER_WAKEN_25M; 1336 val &= ~MASTER_CLK_SEL_DIS; 1337 CSR_WRITE_4(sc, ALC_MASTER_CFG, val); 1338 } 1339 } 1340 } 1341 alc_aspm(sc, 1, IFM_UNKNOWN); 1342} 1343 1344static void 1345alc_config_msi(struct alc_softc *sc) 1346{ 1347 uint32_t ctl, mod; 1348 1349 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 1350 /* 1351 * It seems interrupt moderation is controlled by 1352 * ALC_MSI_RETRANS_TIMER register if MSI/MSIX is active. 1353 * Driver uses RX interrupt moderation parameter to 1354 * program ALC_MSI_RETRANS_TIMER register. 1355 */ 1356 ctl = CSR_READ_4(sc, ALC_MSI_RETRANS_TIMER); 1357 ctl &= ~MSI_RETRANS_TIMER_MASK; 1358 ctl &= ~MSI_RETRANS_MASK_SEL_LINE; 1359 mod = ALC_USECS(sc->alc_int_rx_mod); 1360 if (mod == 0) 1361 mod = 1; 1362 ctl |= mod; 1363 if ((sc->alc_flags & ALC_FLAG_MSIX) != 0) 1364 CSR_WRITE_4(sc, ALC_MSI_RETRANS_TIMER, ctl | 1365 MSI_RETRANS_MASK_SEL_STD); 1366 else if ((sc->alc_flags & ALC_FLAG_MSI) != 0) 1367 CSR_WRITE_4(sc, ALC_MSI_RETRANS_TIMER, ctl | 1368 MSI_RETRANS_MASK_SEL_LINE); 1369 else 1370 CSR_WRITE_4(sc, ALC_MSI_RETRANS_TIMER, 0); 1371 } 1372} 1373 1374static int 1375alc_attach(device_t dev) 1376{ 1377 struct alc_softc *sc; 1378 struct ifnet *ifp; 1379 int base, error, i, msic, msixc; 1380 uint16_t burst; 1381 1382 error = 0; 1383 sc = device_get_softc(dev); 1384 sc->alc_dev = dev; 1385 sc->alc_rev = pci_get_revid(dev); 1386 1387 mtx_init(&sc->alc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 1388 MTX_DEF); 1389 callout_init_mtx(&sc->alc_tick_ch, &sc->alc_mtx, 0); 1390 NET_TASK_INIT(&sc->alc_int_task, 0, alc_int_task, sc); 1391 sc->alc_ident = alc_find_ident(dev); 1392 1393 /* Map the device. */ 1394 pci_enable_busmaster(dev); 1395 sc->alc_res_spec = alc_res_spec_mem; 1396 sc->alc_irq_spec = alc_irq_spec_legacy; 1397 error = bus_alloc_resources(dev, sc->alc_res_spec, sc->alc_res); 1398 if (error != 0) { 1399 device_printf(dev, "cannot allocate memory resources.\n"); 1400 goto fail; 1401 } 1402 1403 /* Set PHY address. */ 1404 sc->alc_phyaddr = ALC_PHY_ADDR; 1405 1406 /* 1407 * One odd thing is AR8132 uses the same PHY hardware(F1 1408 * gigabit PHY) of AR8131. So atphy(4) of AR8132 reports 1409 * the PHY supports 1000Mbps but that's not true. The PHY 1410 * used in AR8132 can't establish gigabit link even if it 1411 * shows the same PHY model/revision number of AR8131. 1412 */ 1413 switch (sc->alc_ident->deviceid) { 1414 case DEVICEID_ATHEROS_E2200: 1415 case DEVICEID_ATHEROS_E2400: 1416 case DEVICEID_ATHEROS_E2500: 1417 sc->alc_flags |= ALC_FLAG_E2X00; 1418 /* FALLTHROUGH */ 1419 case DEVICEID_ATHEROS_AR8161: 1420 if (pci_get_subvendor(dev) == VENDORID_ATHEROS && 1421 pci_get_subdevice(dev) == 0x0091 && sc->alc_rev == 0) 1422 sc->alc_flags |= ALC_FLAG_LINK_WAR; 1423 /* FALLTHROUGH */ 1424 case DEVICEID_ATHEROS_AR8171: 1425 sc->alc_flags |= ALC_FLAG_AR816X_FAMILY; 1426 break; 1427 case DEVICEID_ATHEROS_AR8162: 1428 case DEVICEID_ATHEROS_AR8172: 1429 sc->alc_flags |= ALC_FLAG_FASTETHER | ALC_FLAG_AR816X_FAMILY; 1430 break; 1431 case DEVICEID_ATHEROS_AR8152_B: 1432 case DEVICEID_ATHEROS_AR8152_B2: 1433 sc->alc_flags |= ALC_FLAG_APS; 1434 /* FALLTHROUGH */ 1435 case DEVICEID_ATHEROS_AR8132: 1436 sc->alc_flags |= ALC_FLAG_FASTETHER; 1437 break; 1438 case DEVICEID_ATHEROS_AR8151: 1439 case DEVICEID_ATHEROS_AR8151_V2: 1440 sc->alc_flags |= ALC_FLAG_APS; 1441 if (CSR_READ_4(sc, ALC_MT_MAGIC) == MT_MAGIC) 1442 sc->alc_flags |= ALC_FLAG_MT; 1443 /* FALLTHROUGH */ 1444 default: 1445 break; 1446 } 1447 sc->alc_flags |= ALC_FLAG_JUMBO; 1448 1449 /* 1450 * It seems that AR813x/AR815x has silicon bug for SMB. In 1451 * addition, Atheros said that enabling SMB wouldn't improve 1452 * performance. However I think it's bad to access lots of 1453 * registers to extract MAC statistics. 1454 */ 1455 sc->alc_flags |= ALC_FLAG_SMB_BUG; 1456 /* 1457 * Don't use Tx CMB. It is known to have silicon bug. 1458 */ 1459 sc->alc_flags |= ALC_FLAG_CMB_BUG; 1460 sc->alc_chip_rev = CSR_READ_4(sc, ALC_MASTER_CFG) >> 1461 MASTER_CHIP_REV_SHIFT; 1462 if (bootverbose) { 1463 device_printf(dev, "PCI device revision : 0x%04x\n", 1464 sc->alc_rev); 1465 device_printf(dev, "Chip id/revision : 0x%04x\n", 1466 sc->alc_chip_rev); 1467 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 1468 device_printf(dev, "AR816x revision : 0x%x\n", 1469 AR816X_REV(sc->alc_rev)); 1470 } 1471 device_printf(dev, "%u Tx FIFO, %u Rx FIFO\n", 1472 CSR_READ_4(sc, ALC_SRAM_TX_FIFO_LEN) * 8, 1473 CSR_READ_4(sc, ALC_SRAM_RX_FIFO_LEN) * 8); 1474 1475 /* Initialize DMA parameters. */ 1476 sc->alc_dma_rd_burst = 0; 1477 sc->alc_dma_wr_burst = 0; 1478 sc->alc_rcb = DMA_CFG_RCB_64; 1479 if (pci_find_cap(dev, PCIY_EXPRESS, &base) == 0) { 1480 sc->alc_flags |= ALC_FLAG_PCIE; 1481 sc->alc_expcap = base; 1482 burst = CSR_READ_2(sc, base + PCIER_DEVICE_CTL); 1483 sc->alc_dma_rd_burst = 1484 (burst & PCIEM_CTL_MAX_READ_REQUEST) >> 12; 1485 sc->alc_dma_wr_burst = (burst & PCIEM_CTL_MAX_PAYLOAD) >> 5; 1486 if (bootverbose) { 1487 device_printf(dev, "Read request size : %u bytes.\n", 1488 alc_dma_burst[sc->alc_dma_rd_burst]); 1489 device_printf(dev, "TLP payload size : %u bytes.\n", 1490 alc_dma_burst[sc->alc_dma_wr_burst]); 1491 } 1492 if (alc_dma_burst[sc->alc_dma_rd_burst] > 1024) 1493 sc->alc_dma_rd_burst = 3; 1494 if (alc_dma_burst[sc->alc_dma_wr_burst] > 1024) 1495 sc->alc_dma_wr_burst = 3; 1496 /* 1497 * Force maximum payload size to 128 bytes for 1498 * E2200/E2400/E2500/AR8162/AR8171/AR8172. 1499 * Otherwise it triggers DMA write error. 1500 */ 1501 if ((sc->alc_flags & 1502 (ALC_FLAG_E2X00 | ALC_FLAG_AR816X_FAMILY)) != 0) 1503 sc->alc_dma_wr_burst = 0; 1504 alc_init_pcie(sc); 1505 } 1506 1507 /* Reset PHY. */ 1508 alc_phy_reset(sc); 1509 1510 /* Reset the ethernet controller. */ 1511 alc_stop_mac(sc); 1512 alc_reset(sc); 1513 1514 /* Allocate IRQ resources. */ 1515 msixc = pci_msix_count(dev); 1516 msic = pci_msi_count(dev); 1517 if (bootverbose) { 1518 device_printf(dev, "MSIX count : %d\n", msixc); 1519 device_printf(dev, "MSI count : %d\n", msic); 1520 } 1521 if (msixc > 1) 1522 msixc = 1; 1523 if (msic > 1) 1524 msic = 1; 1525 /* 1526 * Prefer MSIX over MSI. 1527 * AR816x controller has a silicon bug that MSI interrupt 1528 * does not assert if PCIM_CMD_INTxDIS bit of command 1529 * register is set. pci(4) was taught to handle that case. 1530 */ 1531 if (msix_disable == 0 || msi_disable == 0) { 1532 if (msix_disable == 0 && msixc > 0 && 1533 pci_alloc_msix(dev, &msixc) == 0) { 1534 if (msic == 1) { 1535 device_printf(dev, 1536 "Using %d MSIX message(s).\n", msixc); 1537 sc->alc_flags |= ALC_FLAG_MSIX; 1538 sc->alc_irq_spec = alc_irq_spec_msix; 1539 } else 1540 pci_release_msi(dev); 1541 } 1542 if (msi_disable == 0 && (sc->alc_flags & ALC_FLAG_MSIX) == 0 && 1543 msic > 0 && pci_alloc_msi(dev, &msic) == 0) { 1544 if (msic == 1) { 1545 device_printf(dev, 1546 "Using %d MSI message(s).\n", msic); 1547 sc->alc_flags |= ALC_FLAG_MSI; 1548 sc->alc_irq_spec = alc_irq_spec_msi; 1549 } else 1550 pci_release_msi(dev); 1551 } 1552 } 1553 1554 error = bus_alloc_resources(dev, sc->alc_irq_spec, sc->alc_irq); 1555 if (error != 0) { 1556 device_printf(dev, "cannot allocate IRQ resources.\n"); 1557 goto fail; 1558 } 1559 1560 /* Create device sysctl node. */ 1561 alc_sysctl_node(sc); 1562 1563 if ((error = alc_dma_alloc(sc)) != 0) 1564 goto fail; 1565 1566 /* Load station address. */ 1567 alc_get_macaddr(sc); 1568 1569 ifp = sc->alc_ifp = if_alloc(IFT_ETHER); 1570 if (ifp == NULL) { 1571 device_printf(dev, "cannot allocate ifnet structure.\n"); 1572 error = ENXIO; 1573 goto fail; 1574 } 1575 1576 ifp->if_softc = sc; 1577 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1578 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1579 ifp->if_ioctl = alc_ioctl; 1580 ifp->if_start = alc_start; 1581 ifp->if_init = alc_init; 1582 ifp->if_snd.ifq_drv_maxlen = ALC_TX_RING_CNT - 1; 1583 IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen); 1584 IFQ_SET_READY(&ifp->if_snd); 1585 ifp->if_capabilities = IFCAP_TXCSUM | IFCAP_TSO4; 1586 ifp->if_hwassist = ALC_CSUM_FEATURES | CSUM_TSO; 1587 if (pci_find_cap(dev, PCIY_PMG, &base) == 0) { 1588 ifp->if_capabilities |= IFCAP_WOL_MAGIC | IFCAP_WOL_MCAST; 1589 sc->alc_flags |= ALC_FLAG_PM; 1590 sc->alc_pmcap = base; 1591 } 1592 ifp->if_capenable = ifp->if_capabilities; 1593 1594 /* Set up MII bus. */ 1595 error = mii_attach(dev, &sc->alc_miibus, ifp, alc_mediachange, 1596 alc_mediastatus, BMSR_DEFCAPMASK, sc->alc_phyaddr, MII_OFFSET_ANY, 1597 MIIF_DOPAUSE); 1598 if (error != 0) { 1599 device_printf(dev, "attaching PHYs failed\n"); 1600 goto fail; 1601 } 1602 1603 ether_ifattach(ifp, sc->alc_eaddr); 1604 1605 /* VLAN capability setup. */ 1606 ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING | 1607 IFCAP_VLAN_HWCSUM | IFCAP_VLAN_HWTSO; 1608 ifp->if_capenable = ifp->if_capabilities; 1609 /* 1610 * XXX 1611 * It seems enabling Tx checksum offloading makes more trouble. 1612 * Sometimes the controller does not receive any frames when 1613 * Tx checksum offloading is enabled. I'm not sure whether this 1614 * is a bug in Tx checksum offloading logic or I got broken 1615 * sample boards. To safety, don't enable Tx checksum offloading 1616 * by default but give chance to users to toggle it if they know 1617 * their controllers work without problems. 1618 * Fortunately, Tx checksum offloading for AR816x family 1619 * seems to work. 1620 */ 1621 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 1622 ifp->if_capenable &= ~IFCAP_TXCSUM; 1623 ifp->if_hwassist &= ~ALC_CSUM_FEATURES; 1624 } 1625 1626 /* Tell the upper layer(s) we support long frames. */ 1627 ifp->if_hdrlen = sizeof(struct ether_vlan_header); 1628 1629 /* Create local taskq. */ 1630 sc->alc_tq = taskqueue_create_fast("alc_taskq", M_WAITOK, 1631 taskqueue_thread_enqueue, &sc->alc_tq); 1632 if (sc->alc_tq == NULL) { 1633 device_printf(dev, "could not create taskqueue.\n"); 1634 ether_ifdetach(ifp); 1635 error = ENXIO; 1636 goto fail; 1637 } 1638 taskqueue_start_threads(&sc->alc_tq, 1, PI_NET, "%s taskq", 1639 device_get_nameunit(sc->alc_dev)); 1640 1641 alc_config_msi(sc); 1642 if ((sc->alc_flags & ALC_FLAG_MSIX) != 0) 1643 msic = ALC_MSIX_MESSAGES; 1644 else if ((sc->alc_flags & ALC_FLAG_MSI) != 0) 1645 msic = ALC_MSI_MESSAGES; 1646 else 1647 msic = 1; 1648 for (i = 0; i < msic; i++) { 1649 error = bus_setup_intr(dev, sc->alc_irq[i], 1650 INTR_TYPE_NET | INTR_MPSAFE, alc_intr, NULL, sc, 1651 &sc->alc_intrhand[i]); 1652 if (error != 0) 1653 break; 1654 } 1655 if (error != 0) { 1656 device_printf(dev, "could not set up interrupt handler.\n"); 1657 taskqueue_free(sc->alc_tq); 1658 sc->alc_tq = NULL; 1659 ether_ifdetach(ifp); 1660 goto fail; 1661 } 1662 1663 /* Attach driver debugnet methods. */ 1664 DEBUGNET_SET(ifp, alc); 1665 1666fail: 1667 if (error != 0) 1668 alc_detach(dev); 1669 1670 return (error); 1671} 1672 1673static int 1674alc_detach(device_t dev) 1675{ 1676 struct alc_softc *sc; 1677 struct ifnet *ifp; 1678 int i, msic; 1679 1680 sc = device_get_softc(dev); 1681 1682 ifp = sc->alc_ifp; 1683 if (device_is_attached(dev)) { 1684 ether_ifdetach(ifp); 1685 ALC_LOCK(sc); 1686 alc_stop(sc); 1687 ALC_UNLOCK(sc); 1688 callout_drain(&sc->alc_tick_ch); 1689 taskqueue_drain(sc->alc_tq, &sc->alc_int_task); 1690 } 1691 1692 if (sc->alc_tq != NULL) { 1693 taskqueue_drain(sc->alc_tq, &sc->alc_int_task); 1694 taskqueue_free(sc->alc_tq); 1695 sc->alc_tq = NULL; 1696 } 1697 1698 if (sc->alc_miibus != NULL) { 1699 device_delete_child(dev, sc->alc_miibus); 1700 sc->alc_miibus = NULL; 1701 } 1702 bus_generic_detach(dev); 1703 alc_dma_free(sc); 1704 1705 if (ifp != NULL) { 1706 if_free(ifp); 1707 sc->alc_ifp = NULL; 1708 } 1709 1710 if ((sc->alc_flags & ALC_FLAG_MSIX) != 0) 1711 msic = ALC_MSIX_MESSAGES; 1712 else if ((sc->alc_flags & ALC_FLAG_MSI) != 0) 1713 msic = ALC_MSI_MESSAGES; 1714 else 1715 msic = 1; 1716 for (i = 0; i < msic; i++) { 1717 if (sc->alc_intrhand[i] != NULL) { 1718 bus_teardown_intr(dev, sc->alc_irq[i], 1719 sc->alc_intrhand[i]); 1720 sc->alc_intrhand[i] = NULL; 1721 } 1722 } 1723 if (sc->alc_res[0] != NULL) 1724 alc_phy_down(sc); 1725 bus_release_resources(dev, sc->alc_irq_spec, sc->alc_irq); 1726 if ((sc->alc_flags & (ALC_FLAG_MSI | ALC_FLAG_MSIX)) != 0) 1727 pci_release_msi(dev); 1728 bus_release_resources(dev, sc->alc_res_spec, sc->alc_res); 1729 mtx_destroy(&sc->alc_mtx); 1730 1731 return (0); 1732} 1733 1734#define ALC_SYSCTL_STAT_ADD32(c, h, n, p, d) \ 1735 SYSCTL_ADD_UINT(c, h, OID_AUTO, n, CTLFLAG_RD, p, 0, d) 1736#define ALC_SYSCTL_STAT_ADD64(c, h, n, p, d) \ 1737 SYSCTL_ADD_UQUAD(c, h, OID_AUTO, n, CTLFLAG_RD, p, d) 1738 1739static void 1740alc_sysctl_node(struct alc_softc *sc) 1741{ 1742 struct sysctl_ctx_list *ctx; 1743 struct sysctl_oid_list *child, *parent; 1744 struct sysctl_oid *tree; 1745 struct alc_hw_stats *stats; 1746 int error; 1747 1748 stats = &sc->alc_stats; 1749 ctx = device_get_sysctl_ctx(sc->alc_dev); 1750 child = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->alc_dev)); 1751 1752 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "int_rx_mod", 1753 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, &sc->alc_int_rx_mod, 1754 0, sysctl_hw_alc_int_mod, "I", "alc Rx interrupt moderation"); 1755 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "int_tx_mod", 1756 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, &sc->alc_int_tx_mod, 1757 0, sysctl_hw_alc_int_mod, "I", "alc Tx interrupt moderation"); 1758 /* Pull in device tunables. */ 1759 sc->alc_int_rx_mod = ALC_IM_RX_TIMER_DEFAULT; 1760 error = resource_int_value(device_get_name(sc->alc_dev), 1761 device_get_unit(sc->alc_dev), "int_rx_mod", &sc->alc_int_rx_mod); 1762 if (error == 0) { 1763 if (sc->alc_int_rx_mod < ALC_IM_TIMER_MIN || 1764 sc->alc_int_rx_mod > ALC_IM_TIMER_MAX) { 1765 device_printf(sc->alc_dev, "int_rx_mod value out of " 1766 "range; using default: %d\n", 1767 ALC_IM_RX_TIMER_DEFAULT); 1768 sc->alc_int_rx_mod = ALC_IM_RX_TIMER_DEFAULT; 1769 } 1770 } 1771 sc->alc_int_tx_mod = ALC_IM_TX_TIMER_DEFAULT; 1772 error = resource_int_value(device_get_name(sc->alc_dev), 1773 device_get_unit(sc->alc_dev), "int_tx_mod", &sc->alc_int_tx_mod); 1774 if (error == 0) { 1775 if (sc->alc_int_tx_mod < ALC_IM_TIMER_MIN || 1776 sc->alc_int_tx_mod > ALC_IM_TIMER_MAX) { 1777 device_printf(sc->alc_dev, "int_tx_mod value out of " 1778 "range; using default: %d\n", 1779 ALC_IM_TX_TIMER_DEFAULT); 1780 sc->alc_int_tx_mod = ALC_IM_TX_TIMER_DEFAULT; 1781 } 1782 } 1783 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "process_limit", 1784 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 1785 &sc->alc_process_limit, 0, sysctl_hw_alc_proc_limit, "I", 1786 "max number of Rx events to process"); 1787 /* Pull in device tunables. */ 1788 sc->alc_process_limit = ALC_PROC_DEFAULT; 1789 error = resource_int_value(device_get_name(sc->alc_dev), 1790 device_get_unit(sc->alc_dev), "process_limit", 1791 &sc->alc_process_limit); 1792 if (error == 0) { 1793 if (sc->alc_process_limit < ALC_PROC_MIN || 1794 sc->alc_process_limit > ALC_PROC_MAX) { 1795 device_printf(sc->alc_dev, 1796 "process_limit value out of range; " 1797 "using default: %d\n", ALC_PROC_DEFAULT); 1798 sc->alc_process_limit = ALC_PROC_DEFAULT; 1799 } 1800 } 1801 1802 tree = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "stats", 1803 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "ALC statistics"); 1804 parent = SYSCTL_CHILDREN(tree); 1805 1806 /* Rx statistics. */ 1807 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "rx", 1808 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Rx MAC statistics"); 1809 child = SYSCTL_CHILDREN(tree); 1810 ALC_SYSCTL_STAT_ADD32(ctx, child, "good_frames", 1811 &stats->rx_frames, "Good frames"); 1812 ALC_SYSCTL_STAT_ADD32(ctx, child, "good_bcast_frames", 1813 &stats->rx_bcast_frames, "Good broadcast frames"); 1814 ALC_SYSCTL_STAT_ADD32(ctx, child, "good_mcast_frames", 1815 &stats->rx_mcast_frames, "Good multicast frames"); 1816 ALC_SYSCTL_STAT_ADD32(ctx, child, "pause_frames", 1817 &stats->rx_pause_frames, "Pause control frames"); 1818 ALC_SYSCTL_STAT_ADD32(ctx, child, "control_frames", 1819 &stats->rx_control_frames, "Control frames"); 1820 ALC_SYSCTL_STAT_ADD32(ctx, child, "crc_errs", 1821 &stats->rx_crcerrs, "CRC errors"); 1822 ALC_SYSCTL_STAT_ADD32(ctx, child, "len_errs", 1823 &stats->rx_lenerrs, "Frames with length mismatched"); 1824 ALC_SYSCTL_STAT_ADD64(ctx, child, "good_octets", 1825 &stats->rx_bytes, "Good octets"); 1826 ALC_SYSCTL_STAT_ADD64(ctx, child, "good_bcast_octets", 1827 &stats->rx_bcast_bytes, "Good broadcast octets"); 1828 ALC_SYSCTL_STAT_ADD64(ctx, child, "good_mcast_octets", 1829 &stats->rx_mcast_bytes, "Good multicast octets"); 1830 ALC_SYSCTL_STAT_ADD32(ctx, child, "runts", 1831 &stats->rx_runts, "Too short frames"); 1832 ALC_SYSCTL_STAT_ADD32(ctx, child, "fragments", 1833 &stats->rx_fragments, "Fragmented frames"); 1834 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_64", 1835 &stats->rx_pkts_64, "64 bytes frames"); 1836 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_65_127", 1837 &stats->rx_pkts_65_127, "65 to 127 bytes frames"); 1838 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_128_255", 1839 &stats->rx_pkts_128_255, "128 to 255 bytes frames"); 1840 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_256_511", 1841 &stats->rx_pkts_256_511, "256 to 511 bytes frames"); 1842 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_512_1023", 1843 &stats->rx_pkts_512_1023, "512 to 1023 bytes frames"); 1844 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_1024_1518", 1845 &stats->rx_pkts_1024_1518, "1024 to 1518 bytes frames"); 1846 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_1519_max", 1847 &stats->rx_pkts_1519_max, "1519 to max frames"); 1848 ALC_SYSCTL_STAT_ADD32(ctx, child, "trunc_errs", 1849 &stats->rx_pkts_truncated, "Truncated frames due to MTU size"); 1850 ALC_SYSCTL_STAT_ADD32(ctx, child, "fifo_oflows", 1851 &stats->rx_fifo_oflows, "FIFO overflows"); 1852 ALC_SYSCTL_STAT_ADD32(ctx, child, "rrs_errs", 1853 &stats->rx_rrs_errs, "Return status write-back errors"); 1854 ALC_SYSCTL_STAT_ADD32(ctx, child, "align_errs", 1855 &stats->rx_alignerrs, "Alignment errors"); 1856 ALC_SYSCTL_STAT_ADD32(ctx, child, "filtered", 1857 &stats->rx_pkts_filtered, 1858 "Frames dropped due to address filtering"); 1859 1860 /* Tx statistics. */ 1861 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "tx", 1862 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Tx MAC statistics"); 1863 child = SYSCTL_CHILDREN(tree); 1864 ALC_SYSCTL_STAT_ADD32(ctx, child, "good_frames", 1865 &stats->tx_frames, "Good frames"); 1866 ALC_SYSCTL_STAT_ADD32(ctx, child, "good_bcast_frames", 1867 &stats->tx_bcast_frames, "Good broadcast frames"); 1868 ALC_SYSCTL_STAT_ADD32(ctx, child, "good_mcast_frames", 1869 &stats->tx_mcast_frames, "Good multicast frames"); 1870 ALC_SYSCTL_STAT_ADD32(ctx, child, "pause_frames", 1871 &stats->tx_pause_frames, "Pause control frames"); 1872 ALC_SYSCTL_STAT_ADD32(ctx, child, "control_frames", 1873 &stats->tx_control_frames, "Control frames"); 1874 ALC_SYSCTL_STAT_ADD32(ctx, child, "excess_defers", 1875 &stats->tx_excess_defer, "Frames with excessive derferrals"); 1876 ALC_SYSCTL_STAT_ADD32(ctx, child, "defers", 1877 &stats->tx_excess_defer, "Frames with derferrals"); 1878 ALC_SYSCTL_STAT_ADD64(ctx, child, "good_octets", 1879 &stats->tx_bytes, "Good octets"); 1880 ALC_SYSCTL_STAT_ADD64(ctx, child, "good_bcast_octets", 1881 &stats->tx_bcast_bytes, "Good broadcast octets"); 1882 ALC_SYSCTL_STAT_ADD64(ctx, child, "good_mcast_octets", 1883 &stats->tx_mcast_bytes, "Good multicast octets"); 1884 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_64", 1885 &stats->tx_pkts_64, "64 bytes frames"); 1886 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_65_127", 1887 &stats->tx_pkts_65_127, "65 to 127 bytes frames"); 1888 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_128_255", 1889 &stats->tx_pkts_128_255, "128 to 255 bytes frames"); 1890 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_256_511", 1891 &stats->tx_pkts_256_511, "256 to 511 bytes frames"); 1892 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_512_1023", 1893 &stats->tx_pkts_512_1023, "512 to 1023 bytes frames"); 1894 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_1024_1518", 1895 &stats->tx_pkts_1024_1518, "1024 to 1518 bytes frames"); 1896 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_1519_max", 1897 &stats->tx_pkts_1519_max, "1519 to max frames"); 1898 ALC_SYSCTL_STAT_ADD32(ctx, child, "single_colls", 1899 &stats->tx_single_colls, "Single collisions"); 1900 ALC_SYSCTL_STAT_ADD32(ctx, child, "multi_colls", 1901 &stats->tx_multi_colls, "Multiple collisions"); 1902 ALC_SYSCTL_STAT_ADD32(ctx, child, "late_colls", 1903 &stats->tx_late_colls, "Late collisions"); 1904 ALC_SYSCTL_STAT_ADD32(ctx, child, "excess_colls", 1905 &stats->tx_excess_colls, "Excessive collisions"); 1906 ALC_SYSCTL_STAT_ADD32(ctx, child, "underruns", 1907 &stats->tx_underrun, "FIFO underruns"); 1908 ALC_SYSCTL_STAT_ADD32(ctx, child, "desc_underruns", 1909 &stats->tx_desc_underrun, "Descriptor write-back errors"); 1910 ALC_SYSCTL_STAT_ADD32(ctx, child, "len_errs", 1911 &stats->tx_lenerrs, "Frames with length mismatched"); 1912 ALC_SYSCTL_STAT_ADD32(ctx, child, "trunc_errs", 1913 &stats->tx_pkts_truncated, "Truncated frames due to MTU size"); 1914} 1915 1916#undef ALC_SYSCTL_STAT_ADD32 1917#undef ALC_SYSCTL_STAT_ADD64 1918 1919struct alc_dmamap_arg { 1920 bus_addr_t alc_busaddr; 1921}; 1922 1923static void 1924alc_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 1925{ 1926 struct alc_dmamap_arg *ctx; 1927 1928 if (error != 0) 1929 return; 1930 1931 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 1932 1933 ctx = (struct alc_dmamap_arg *)arg; 1934 ctx->alc_busaddr = segs[0].ds_addr; 1935} 1936 1937/* 1938 * Normal and high Tx descriptors shares single Tx high address. 1939 * Four Rx descriptor/return rings and CMB shares the same Rx 1940 * high address. 1941 */ 1942static int 1943alc_check_boundary(struct alc_softc *sc) 1944{ 1945 bus_addr_t cmb_end, rx_ring_end, rr_ring_end, tx_ring_end; 1946 1947 rx_ring_end = sc->alc_rdata.alc_rx_ring_paddr + ALC_RX_RING_SZ; 1948 rr_ring_end = sc->alc_rdata.alc_rr_ring_paddr + ALC_RR_RING_SZ; 1949 cmb_end = sc->alc_rdata.alc_cmb_paddr + ALC_CMB_SZ; 1950 tx_ring_end = sc->alc_rdata.alc_tx_ring_paddr + ALC_TX_RING_SZ; 1951 1952 /* 4GB boundary crossing is not allowed. */ 1953 if ((ALC_ADDR_HI(rx_ring_end) != 1954 ALC_ADDR_HI(sc->alc_rdata.alc_rx_ring_paddr)) || 1955 (ALC_ADDR_HI(rr_ring_end) != 1956 ALC_ADDR_HI(sc->alc_rdata.alc_rr_ring_paddr)) || 1957 (ALC_ADDR_HI(cmb_end) != 1958 ALC_ADDR_HI(sc->alc_rdata.alc_cmb_paddr)) || 1959 (ALC_ADDR_HI(tx_ring_end) != 1960 ALC_ADDR_HI(sc->alc_rdata.alc_tx_ring_paddr))) 1961 return (EFBIG); 1962 /* 1963 * Make sure Rx return descriptor/Rx descriptor/CMB use 1964 * the same high address. 1965 */ 1966 if ((ALC_ADDR_HI(rx_ring_end) != ALC_ADDR_HI(rr_ring_end)) || 1967 (ALC_ADDR_HI(rx_ring_end) != ALC_ADDR_HI(cmb_end))) 1968 return (EFBIG); 1969 1970 return (0); 1971} 1972 1973static int 1974alc_dma_alloc(struct alc_softc *sc) 1975{ 1976 struct alc_txdesc *txd; 1977 struct alc_rxdesc *rxd; 1978 bus_addr_t lowaddr; 1979 struct alc_dmamap_arg ctx; 1980 int error, i; 1981 1982 lowaddr = BUS_SPACE_MAXADDR; 1983 if (sc->alc_flags & ALC_FLAG_MT) 1984 lowaddr = BUS_SPACE_MAXSIZE_32BIT; 1985again: 1986 /* Create parent DMA tag. */ 1987 error = bus_dma_tag_create( 1988 bus_get_dma_tag(sc->alc_dev), /* parent */ 1989 1, 0, /* alignment, boundary */ 1990 lowaddr, /* lowaddr */ 1991 BUS_SPACE_MAXADDR, /* highaddr */ 1992 NULL, NULL, /* filter, filterarg */ 1993 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 1994 0, /* nsegments */ 1995 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 1996 0, /* flags */ 1997 NULL, NULL, /* lockfunc, lockarg */ 1998 &sc->alc_cdata.alc_parent_tag); 1999 if (error != 0) { 2000 device_printf(sc->alc_dev, 2001 "could not create parent DMA tag.\n"); 2002 goto fail; 2003 } 2004 2005 /* Create DMA tag for Tx descriptor ring. */ 2006 error = bus_dma_tag_create( 2007 sc->alc_cdata.alc_parent_tag, /* parent */ 2008 ALC_TX_RING_ALIGN, 0, /* alignment, boundary */ 2009 BUS_SPACE_MAXADDR, /* lowaddr */ 2010 BUS_SPACE_MAXADDR, /* highaddr */ 2011 NULL, NULL, /* filter, filterarg */ 2012 ALC_TX_RING_SZ, /* maxsize */ 2013 1, /* nsegments */ 2014 ALC_TX_RING_SZ, /* maxsegsize */ 2015 0, /* flags */ 2016 NULL, NULL, /* lockfunc, lockarg */ 2017 &sc->alc_cdata.alc_tx_ring_tag); 2018 if (error != 0) { 2019 device_printf(sc->alc_dev, 2020 "could not create Tx ring DMA tag.\n"); 2021 goto fail; 2022 } 2023 2024 /* Create DMA tag for Rx free descriptor ring. */ 2025 error = bus_dma_tag_create( 2026 sc->alc_cdata.alc_parent_tag, /* parent */ 2027 ALC_RX_RING_ALIGN, 0, /* alignment, boundary */ 2028 BUS_SPACE_MAXADDR, /* lowaddr */ 2029 BUS_SPACE_MAXADDR, /* highaddr */ 2030 NULL, NULL, /* filter, filterarg */ 2031 ALC_RX_RING_SZ, /* maxsize */ 2032 1, /* nsegments */ 2033 ALC_RX_RING_SZ, /* maxsegsize */ 2034 0, /* flags */ 2035 NULL, NULL, /* lockfunc, lockarg */ 2036 &sc->alc_cdata.alc_rx_ring_tag); 2037 if (error != 0) { 2038 device_printf(sc->alc_dev, 2039 "could not create Rx ring DMA tag.\n"); 2040 goto fail; 2041 } 2042 /* Create DMA tag for Rx return descriptor ring. */ 2043 error = bus_dma_tag_create( 2044 sc->alc_cdata.alc_parent_tag, /* parent */ 2045 ALC_RR_RING_ALIGN, 0, /* alignment, boundary */ 2046 BUS_SPACE_MAXADDR, /* lowaddr */ 2047 BUS_SPACE_MAXADDR, /* highaddr */ 2048 NULL, NULL, /* filter, filterarg */ 2049 ALC_RR_RING_SZ, /* maxsize */ 2050 1, /* nsegments */ 2051 ALC_RR_RING_SZ, /* maxsegsize */ 2052 0, /* flags */ 2053 NULL, NULL, /* lockfunc, lockarg */ 2054 &sc->alc_cdata.alc_rr_ring_tag); 2055 if (error != 0) { 2056 device_printf(sc->alc_dev, 2057 "could not create Rx return ring DMA tag.\n"); 2058 goto fail; 2059 } 2060 2061 /* Create DMA tag for coalescing message block. */ 2062 error = bus_dma_tag_create( 2063 sc->alc_cdata.alc_parent_tag, /* parent */ 2064 ALC_CMB_ALIGN, 0, /* alignment, boundary */ 2065 BUS_SPACE_MAXADDR, /* lowaddr */ 2066 BUS_SPACE_MAXADDR, /* highaddr */ 2067 NULL, NULL, /* filter, filterarg */ 2068 ALC_CMB_SZ, /* maxsize */ 2069 1, /* nsegments */ 2070 ALC_CMB_SZ, /* maxsegsize */ 2071 0, /* flags */ 2072 NULL, NULL, /* lockfunc, lockarg */ 2073 &sc->alc_cdata.alc_cmb_tag); 2074 if (error != 0) { 2075 device_printf(sc->alc_dev, 2076 "could not create CMB DMA tag.\n"); 2077 goto fail; 2078 } 2079 /* Create DMA tag for status message block. */ 2080 error = bus_dma_tag_create( 2081 sc->alc_cdata.alc_parent_tag, /* parent */ 2082 ALC_SMB_ALIGN, 0, /* alignment, boundary */ 2083 BUS_SPACE_MAXADDR, /* lowaddr */ 2084 BUS_SPACE_MAXADDR, /* highaddr */ 2085 NULL, NULL, /* filter, filterarg */ 2086 ALC_SMB_SZ, /* maxsize */ 2087 1, /* nsegments */ 2088 ALC_SMB_SZ, /* maxsegsize */ 2089 0, /* flags */ 2090 NULL, NULL, /* lockfunc, lockarg */ 2091 &sc->alc_cdata.alc_smb_tag); 2092 if (error != 0) { 2093 device_printf(sc->alc_dev, 2094 "could not create SMB DMA tag.\n"); 2095 goto fail; 2096 } 2097 2098 /* Allocate DMA'able memory and load the DMA map for Tx ring. */ 2099 error = bus_dmamem_alloc(sc->alc_cdata.alc_tx_ring_tag, 2100 (void **)&sc->alc_rdata.alc_tx_ring, 2101 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 2102 &sc->alc_cdata.alc_tx_ring_map); 2103 if (error != 0) { 2104 device_printf(sc->alc_dev, 2105 "could not allocate DMA'able memory for Tx ring.\n"); 2106 goto fail; 2107 } 2108 ctx.alc_busaddr = 0; 2109 error = bus_dmamap_load(sc->alc_cdata.alc_tx_ring_tag, 2110 sc->alc_cdata.alc_tx_ring_map, sc->alc_rdata.alc_tx_ring, 2111 ALC_TX_RING_SZ, alc_dmamap_cb, &ctx, 0); 2112 if (error != 0 || ctx.alc_busaddr == 0) { 2113 device_printf(sc->alc_dev, 2114 "could not load DMA'able memory for Tx ring.\n"); 2115 goto fail; 2116 } 2117 sc->alc_rdata.alc_tx_ring_paddr = ctx.alc_busaddr; 2118 2119 /* Allocate DMA'able memory and load the DMA map for Rx ring. */ 2120 error = bus_dmamem_alloc(sc->alc_cdata.alc_rx_ring_tag, 2121 (void **)&sc->alc_rdata.alc_rx_ring, 2122 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 2123 &sc->alc_cdata.alc_rx_ring_map); 2124 if (error != 0) { 2125 device_printf(sc->alc_dev, 2126 "could not allocate DMA'able memory for Rx ring.\n"); 2127 goto fail; 2128 } 2129 ctx.alc_busaddr = 0; 2130 error = bus_dmamap_load(sc->alc_cdata.alc_rx_ring_tag, 2131 sc->alc_cdata.alc_rx_ring_map, sc->alc_rdata.alc_rx_ring, 2132 ALC_RX_RING_SZ, alc_dmamap_cb, &ctx, 0); 2133 if (error != 0 || ctx.alc_busaddr == 0) { 2134 device_printf(sc->alc_dev, 2135 "could not load DMA'able memory for Rx ring.\n"); 2136 goto fail; 2137 } 2138 sc->alc_rdata.alc_rx_ring_paddr = ctx.alc_busaddr; 2139 2140 /* Allocate DMA'able memory and load the DMA map for Rx return ring. */ 2141 error = bus_dmamem_alloc(sc->alc_cdata.alc_rr_ring_tag, 2142 (void **)&sc->alc_rdata.alc_rr_ring, 2143 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 2144 &sc->alc_cdata.alc_rr_ring_map); 2145 if (error != 0) { 2146 device_printf(sc->alc_dev, 2147 "could not allocate DMA'able memory for Rx return ring.\n"); 2148 goto fail; 2149 } 2150 ctx.alc_busaddr = 0; 2151 error = bus_dmamap_load(sc->alc_cdata.alc_rr_ring_tag, 2152 sc->alc_cdata.alc_rr_ring_map, sc->alc_rdata.alc_rr_ring, 2153 ALC_RR_RING_SZ, alc_dmamap_cb, &ctx, 0); 2154 if (error != 0 || ctx.alc_busaddr == 0) { 2155 device_printf(sc->alc_dev, 2156 "could not load DMA'able memory for Tx ring.\n"); 2157 goto fail; 2158 } 2159 sc->alc_rdata.alc_rr_ring_paddr = ctx.alc_busaddr; 2160 2161 /* Allocate DMA'able memory and load the DMA map for CMB. */ 2162 error = bus_dmamem_alloc(sc->alc_cdata.alc_cmb_tag, 2163 (void **)&sc->alc_rdata.alc_cmb, 2164 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 2165 &sc->alc_cdata.alc_cmb_map); 2166 if (error != 0) { 2167 device_printf(sc->alc_dev, 2168 "could not allocate DMA'able memory for CMB.\n"); 2169 goto fail; 2170 } 2171 ctx.alc_busaddr = 0; 2172 error = bus_dmamap_load(sc->alc_cdata.alc_cmb_tag, 2173 sc->alc_cdata.alc_cmb_map, sc->alc_rdata.alc_cmb, 2174 ALC_CMB_SZ, alc_dmamap_cb, &ctx, 0); 2175 if (error != 0 || ctx.alc_busaddr == 0) { 2176 device_printf(sc->alc_dev, 2177 "could not load DMA'able memory for CMB.\n"); 2178 goto fail; 2179 } 2180 sc->alc_rdata.alc_cmb_paddr = ctx.alc_busaddr; 2181 2182 /* Allocate DMA'able memory and load the DMA map for SMB. */ 2183 error = bus_dmamem_alloc(sc->alc_cdata.alc_smb_tag, 2184 (void **)&sc->alc_rdata.alc_smb, 2185 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 2186 &sc->alc_cdata.alc_smb_map); 2187 if (error != 0) { 2188 device_printf(sc->alc_dev, 2189 "could not allocate DMA'able memory for SMB.\n"); 2190 goto fail; 2191 } 2192 ctx.alc_busaddr = 0; 2193 error = bus_dmamap_load(sc->alc_cdata.alc_smb_tag, 2194 sc->alc_cdata.alc_smb_map, sc->alc_rdata.alc_smb, 2195 ALC_SMB_SZ, alc_dmamap_cb, &ctx, 0); 2196 if (error != 0 || ctx.alc_busaddr == 0) { 2197 device_printf(sc->alc_dev, 2198 "could not load DMA'able memory for CMB.\n"); 2199 goto fail; 2200 } 2201 sc->alc_rdata.alc_smb_paddr = ctx.alc_busaddr; 2202 2203 /* Make sure we've not crossed 4GB boundary. */ 2204 if (lowaddr != BUS_SPACE_MAXADDR_32BIT && 2205 (error = alc_check_boundary(sc)) != 0) { 2206 device_printf(sc->alc_dev, "4GB boundary crossed, " 2207 "switching to 32bit DMA addressing mode.\n"); 2208 alc_dma_free(sc); 2209 /* 2210 * Limit max allowable DMA address space to 32bit 2211 * and try again. 2212 */ 2213 lowaddr = BUS_SPACE_MAXADDR_32BIT; 2214 goto again; 2215 } 2216 2217 /* 2218 * Create Tx buffer parent tag. 2219 * AR81[3567]x allows 64bit DMA addressing of Tx/Rx buffers 2220 * so it needs separate parent DMA tag as parent DMA address 2221 * space could be restricted to be within 32bit address space 2222 * by 4GB boundary crossing. 2223 */ 2224 error = bus_dma_tag_create( 2225 bus_get_dma_tag(sc->alc_dev), /* parent */ 2226 1, 0, /* alignment, boundary */ 2227 lowaddr, /* lowaddr */ 2228 BUS_SPACE_MAXADDR, /* highaddr */ 2229 NULL, NULL, /* filter, filterarg */ 2230 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 2231 0, /* nsegments */ 2232 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 2233 0, /* flags */ 2234 NULL, NULL, /* lockfunc, lockarg */ 2235 &sc->alc_cdata.alc_buffer_tag); 2236 if (error != 0) { 2237 device_printf(sc->alc_dev, 2238 "could not create parent buffer DMA tag.\n"); 2239 goto fail; 2240 } 2241 2242 /* Create DMA tag for Tx buffers. */ 2243 error = bus_dma_tag_create( 2244 sc->alc_cdata.alc_buffer_tag, /* parent */ 2245 1, 0, /* alignment, boundary */ 2246 BUS_SPACE_MAXADDR, /* lowaddr */ 2247 BUS_SPACE_MAXADDR, /* highaddr */ 2248 NULL, NULL, /* filter, filterarg */ 2249 ALC_TSO_MAXSIZE, /* maxsize */ 2250 ALC_MAXTXSEGS, /* nsegments */ 2251 ALC_TSO_MAXSEGSIZE, /* maxsegsize */ 2252 0, /* flags */ 2253 NULL, NULL, /* lockfunc, lockarg */ 2254 &sc->alc_cdata.alc_tx_tag); 2255 if (error != 0) { 2256 device_printf(sc->alc_dev, "could not create Tx DMA tag.\n"); 2257 goto fail; 2258 } 2259 2260 /* Create DMA tag for Rx buffers. */ 2261 error = bus_dma_tag_create( 2262 sc->alc_cdata.alc_buffer_tag, /* parent */ 2263 ALC_RX_BUF_ALIGN, 0, /* alignment, boundary */ 2264 BUS_SPACE_MAXADDR, /* lowaddr */ 2265 BUS_SPACE_MAXADDR, /* highaddr */ 2266 NULL, NULL, /* filter, filterarg */ 2267 MCLBYTES, /* maxsize */ 2268 1, /* nsegments */ 2269 MCLBYTES, /* maxsegsize */ 2270 0, /* flags */ 2271 NULL, NULL, /* lockfunc, lockarg */ 2272 &sc->alc_cdata.alc_rx_tag); 2273 if (error != 0) { 2274 device_printf(sc->alc_dev, "could not create Rx DMA tag.\n"); 2275 goto fail; 2276 } 2277 /* Create DMA maps for Tx buffers. */ 2278 for (i = 0; i < ALC_TX_RING_CNT; i++) { 2279 txd = &sc->alc_cdata.alc_txdesc[i]; 2280 txd->tx_m = NULL; 2281 txd->tx_dmamap = NULL; 2282 error = bus_dmamap_create(sc->alc_cdata.alc_tx_tag, 0, 2283 &txd->tx_dmamap); 2284 if (error != 0) { 2285 device_printf(sc->alc_dev, 2286 "could not create Tx dmamap.\n"); 2287 goto fail; 2288 } 2289 } 2290 /* Create DMA maps for Rx buffers. */ 2291 if ((error = bus_dmamap_create(sc->alc_cdata.alc_rx_tag, 0, 2292 &sc->alc_cdata.alc_rx_sparemap)) != 0) { 2293 device_printf(sc->alc_dev, 2294 "could not create spare Rx dmamap.\n"); 2295 goto fail; 2296 } 2297 for (i = 0; i < ALC_RX_RING_CNT; i++) { 2298 rxd = &sc->alc_cdata.alc_rxdesc[i]; 2299 rxd->rx_m = NULL; 2300 rxd->rx_dmamap = NULL; 2301 error = bus_dmamap_create(sc->alc_cdata.alc_rx_tag, 0, 2302 &rxd->rx_dmamap); 2303 if (error != 0) { 2304 device_printf(sc->alc_dev, 2305 "could not create Rx dmamap.\n"); 2306 goto fail; 2307 } 2308 } 2309 2310fail: 2311 return (error); 2312} 2313 2314static void 2315alc_dma_free(struct alc_softc *sc) 2316{ 2317 struct alc_txdesc *txd; 2318 struct alc_rxdesc *rxd; 2319 int i; 2320 2321 /* Tx buffers. */ 2322 if (sc->alc_cdata.alc_tx_tag != NULL) { 2323 for (i = 0; i < ALC_TX_RING_CNT; i++) { 2324 txd = &sc->alc_cdata.alc_txdesc[i]; 2325 if (txd->tx_dmamap != NULL) { 2326 bus_dmamap_destroy(sc->alc_cdata.alc_tx_tag, 2327 txd->tx_dmamap); 2328 txd->tx_dmamap = NULL; 2329 } 2330 } 2331 bus_dma_tag_destroy(sc->alc_cdata.alc_tx_tag); 2332 sc->alc_cdata.alc_tx_tag = NULL; 2333 } 2334 /* Rx buffers */ 2335 if (sc->alc_cdata.alc_rx_tag != NULL) { 2336 for (i = 0; i < ALC_RX_RING_CNT; i++) { 2337 rxd = &sc->alc_cdata.alc_rxdesc[i]; 2338 if (rxd->rx_dmamap != NULL) { 2339 bus_dmamap_destroy(sc->alc_cdata.alc_rx_tag, 2340 rxd->rx_dmamap); 2341 rxd->rx_dmamap = NULL; 2342 } 2343 } 2344 if (sc->alc_cdata.alc_rx_sparemap != NULL) { 2345 bus_dmamap_destroy(sc->alc_cdata.alc_rx_tag, 2346 sc->alc_cdata.alc_rx_sparemap); 2347 sc->alc_cdata.alc_rx_sparemap = NULL; 2348 } 2349 bus_dma_tag_destroy(sc->alc_cdata.alc_rx_tag); 2350 sc->alc_cdata.alc_rx_tag = NULL; 2351 } 2352 /* Tx descriptor ring. */ 2353 if (sc->alc_cdata.alc_tx_ring_tag != NULL) { 2354 if (sc->alc_rdata.alc_tx_ring_paddr != 0) 2355 bus_dmamap_unload(sc->alc_cdata.alc_tx_ring_tag, 2356 sc->alc_cdata.alc_tx_ring_map); 2357 if (sc->alc_rdata.alc_tx_ring != NULL) 2358 bus_dmamem_free(sc->alc_cdata.alc_tx_ring_tag, 2359 sc->alc_rdata.alc_tx_ring, 2360 sc->alc_cdata.alc_tx_ring_map); 2361 sc->alc_rdata.alc_tx_ring_paddr = 0; 2362 sc->alc_rdata.alc_tx_ring = NULL; 2363 bus_dma_tag_destroy(sc->alc_cdata.alc_tx_ring_tag); 2364 sc->alc_cdata.alc_tx_ring_tag = NULL; 2365 } 2366 /* Rx ring. */ 2367 if (sc->alc_cdata.alc_rx_ring_tag != NULL) { 2368 if (sc->alc_rdata.alc_rx_ring_paddr != 0) 2369 bus_dmamap_unload(sc->alc_cdata.alc_rx_ring_tag, 2370 sc->alc_cdata.alc_rx_ring_map); 2371 if (sc->alc_rdata.alc_rx_ring != NULL) 2372 bus_dmamem_free(sc->alc_cdata.alc_rx_ring_tag, 2373 sc->alc_rdata.alc_rx_ring, 2374 sc->alc_cdata.alc_rx_ring_map); 2375 sc->alc_rdata.alc_rx_ring_paddr = 0; 2376 sc->alc_rdata.alc_rx_ring = NULL; 2377 bus_dma_tag_destroy(sc->alc_cdata.alc_rx_ring_tag); 2378 sc->alc_cdata.alc_rx_ring_tag = NULL; 2379 } 2380 /* Rx return ring. */ 2381 if (sc->alc_cdata.alc_rr_ring_tag != NULL) { 2382 if (sc->alc_rdata.alc_rr_ring_paddr != 0) 2383 bus_dmamap_unload(sc->alc_cdata.alc_rr_ring_tag, 2384 sc->alc_cdata.alc_rr_ring_map); 2385 if (sc->alc_rdata.alc_rr_ring != NULL) 2386 bus_dmamem_free(sc->alc_cdata.alc_rr_ring_tag, 2387 sc->alc_rdata.alc_rr_ring, 2388 sc->alc_cdata.alc_rr_ring_map); 2389 sc->alc_rdata.alc_rr_ring_paddr = 0; 2390 sc->alc_rdata.alc_rr_ring = NULL; 2391 bus_dma_tag_destroy(sc->alc_cdata.alc_rr_ring_tag); 2392 sc->alc_cdata.alc_rr_ring_tag = NULL; 2393 } 2394 /* CMB block */ 2395 if (sc->alc_cdata.alc_cmb_tag != NULL) { 2396 if (sc->alc_rdata.alc_cmb_paddr != 0) 2397 bus_dmamap_unload(sc->alc_cdata.alc_cmb_tag, 2398 sc->alc_cdata.alc_cmb_map); 2399 if (sc->alc_rdata.alc_cmb != NULL) 2400 bus_dmamem_free(sc->alc_cdata.alc_cmb_tag, 2401 sc->alc_rdata.alc_cmb, 2402 sc->alc_cdata.alc_cmb_map); 2403 sc->alc_rdata.alc_cmb_paddr = 0; 2404 sc->alc_rdata.alc_cmb = NULL; 2405 bus_dma_tag_destroy(sc->alc_cdata.alc_cmb_tag); 2406 sc->alc_cdata.alc_cmb_tag = NULL; 2407 } 2408 /* SMB block */ 2409 if (sc->alc_cdata.alc_smb_tag != NULL) { 2410 if (sc->alc_rdata.alc_smb_paddr != 0) 2411 bus_dmamap_unload(sc->alc_cdata.alc_smb_tag, 2412 sc->alc_cdata.alc_smb_map); 2413 if (sc->alc_rdata.alc_smb != NULL) 2414 bus_dmamem_free(sc->alc_cdata.alc_smb_tag, 2415 sc->alc_rdata.alc_smb, 2416 sc->alc_cdata.alc_smb_map); 2417 sc->alc_rdata.alc_smb_paddr = 0; 2418 sc->alc_rdata.alc_smb = NULL; 2419 bus_dma_tag_destroy(sc->alc_cdata.alc_smb_tag); 2420 sc->alc_cdata.alc_smb_tag = NULL; 2421 } 2422 if (sc->alc_cdata.alc_buffer_tag != NULL) { 2423 bus_dma_tag_destroy(sc->alc_cdata.alc_buffer_tag); 2424 sc->alc_cdata.alc_buffer_tag = NULL; 2425 } 2426 if (sc->alc_cdata.alc_parent_tag != NULL) { 2427 bus_dma_tag_destroy(sc->alc_cdata.alc_parent_tag); 2428 sc->alc_cdata.alc_parent_tag = NULL; 2429 } 2430} 2431 2432static int 2433alc_shutdown(device_t dev) 2434{ 2435 2436 return (alc_suspend(dev)); 2437} 2438 2439/* 2440 * Note, this driver resets the link speed to 10/100Mbps by 2441 * restarting auto-negotiation in suspend/shutdown phase but we 2442 * don't know whether that auto-negotiation would succeed or not 2443 * as driver has no control after powering off/suspend operation. 2444 * If the renegotiation fail WOL may not work. Running at 1Gbps 2445 * will draw more power than 375mA at 3.3V which is specified in 2446 * PCI specification and that would result in complete 2447 * shutdowning power to ethernet controller. 2448 * 2449 * TODO 2450 * Save current negotiated media speed/duplex/flow-control to 2451 * softc and restore the same link again after resuming. PHY 2452 * handling such as power down/resetting to 100Mbps may be better 2453 * handled in suspend method in phy driver. 2454 */ 2455static void 2456alc_setlinkspeed(struct alc_softc *sc) 2457{ 2458 struct mii_data *mii; 2459 int aneg, i; 2460 2461 mii = device_get_softc(sc->alc_miibus); 2462 mii_pollstat(mii); 2463 aneg = 0; 2464 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 2465 (IFM_ACTIVE | IFM_AVALID)) { 2466 switch IFM_SUBTYPE(mii->mii_media_active) { 2467 case IFM_10_T: 2468 case IFM_100_TX: 2469 return; 2470 case IFM_1000_T: 2471 aneg++; 2472 break; 2473 default: 2474 break; 2475 } 2476 } 2477 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, MII_100T2CR, 0); 2478 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 2479 MII_ANAR, ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10 | ANAR_CSMA); 2480 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 2481 MII_BMCR, BMCR_RESET | BMCR_AUTOEN | BMCR_STARTNEG); 2482 DELAY(1000); 2483 if (aneg != 0) { 2484 /* 2485 * Poll link state until alc(4) get a 10/100Mbps link. 2486 */ 2487 for (i = 0; i < MII_ANEGTICKS_GIGE; i++) { 2488 mii_pollstat(mii); 2489 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) 2490 == (IFM_ACTIVE | IFM_AVALID)) { 2491 switch (IFM_SUBTYPE( 2492 mii->mii_media_active)) { 2493 case IFM_10_T: 2494 case IFM_100_TX: 2495 alc_mac_config(sc); 2496 return; 2497 default: 2498 break; 2499 } 2500 } 2501 ALC_UNLOCK(sc); 2502 pause("alclnk", hz); 2503 ALC_LOCK(sc); 2504 } 2505 if (i == MII_ANEGTICKS_GIGE) 2506 device_printf(sc->alc_dev, 2507 "establishing a link failed, WOL may not work!"); 2508 } 2509 /* 2510 * No link, force MAC to have 100Mbps, full-duplex link. 2511 * This is the last resort and may/may not work. 2512 */ 2513 mii->mii_media_status = IFM_AVALID | IFM_ACTIVE; 2514 mii->mii_media_active = IFM_ETHER | IFM_100_TX | IFM_FDX; 2515 alc_mac_config(sc); 2516} 2517 2518static void 2519alc_setwol(struct alc_softc *sc) 2520{ 2521 2522 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 2523 alc_setwol_816x(sc); 2524 else 2525 alc_setwol_813x(sc); 2526} 2527 2528static void 2529alc_setwol_813x(struct alc_softc *sc) 2530{ 2531 struct ifnet *ifp; 2532 uint32_t reg, pmcs; 2533 uint16_t pmstat; 2534 2535 ALC_LOCK_ASSERT(sc); 2536 2537 alc_disable_l0s_l1(sc); 2538 ifp = sc->alc_ifp; 2539 if ((sc->alc_flags & ALC_FLAG_PM) == 0) { 2540 /* Disable WOL. */ 2541 CSR_WRITE_4(sc, ALC_WOL_CFG, 0); 2542 reg = CSR_READ_4(sc, ALC_PCIE_PHYMISC); 2543 reg |= PCIE_PHYMISC_FORCE_RCV_DET; 2544 CSR_WRITE_4(sc, ALC_PCIE_PHYMISC, reg); 2545 /* Force PHY power down. */ 2546 alc_phy_down(sc); 2547 CSR_WRITE_4(sc, ALC_MASTER_CFG, 2548 CSR_READ_4(sc, ALC_MASTER_CFG) | MASTER_CLK_SEL_DIS); 2549 return; 2550 } 2551 2552 if ((ifp->if_capenable & IFCAP_WOL) != 0) { 2553 if ((sc->alc_flags & ALC_FLAG_FASTETHER) == 0) 2554 alc_setlinkspeed(sc); 2555 CSR_WRITE_4(sc, ALC_MASTER_CFG, 2556 CSR_READ_4(sc, ALC_MASTER_CFG) & ~MASTER_CLK_SEL_DIS); 2557 } 2558 2559 pmcs = 0; 2560 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) 2561 pmcs |= WOL_CFG_MAGIC | WOL_CFG_MAGIC_ENB; 2562 CSR_WRITE_4(sc, ALC_WOL_CFG, pmcs); 2563 reg = CSR_READ_4(sc, ALC_MAC_CFG); 2564 reg &= ~(MAC_CFG_DBG | MAC_CFG_PROMISC | MAC_CFG_ALLMULTI | 2565 MAC_CFG_BCAST); 2566 if ((ifp->if_capenable & IFCAP_WOL_MCAST) != 0) 2567 reg |= MAC_CFG_ALLMULTI | MAC_CFG_BCAST; 2568 if ((ifp->if_capenable & IFCAP_WOL) != 0) 2569 reg |= MAC_CFG_RX_ENB; 2570 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 2571 2572 reg = CSR_READ_4(sc, ALC_PCIE_PHYMISC); 2573 reg |= PCIE_PHYMISC_FORCE_RCV_DET; 2574 CSR_WRITE_4(sc, ALC_PCIE_PHYMISC, reg); 2575 if ((ifp->if_capenable & IFCAP_WOL) == 0) { 2576 /* WOL disabled, PHY power down. */ 2577 alc_phy_down(sc); 2578 CSR_WRITE_4(sc, ALC_MASTER_CFG, 2579 CSR_READ_4(sc, ALC_MASTER_CFG) | MASTER_CLK_SEL_DIS); 2580 } 2581 /* Request PME. */ 2582 pmstat = pci_read_config(sc->alc_dev, 2583 sc->alc_pmcap + PCIR_POWER_STATUS, 2); 2584 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); 2585 if ((ifp->if_capenable & IFCAP_WOL) != 0) 2586 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 2587 pci_write_config(sc->alc_dev, 2588 sc->alc_pmcap + PCIR_POWER_STATUS, pmstat, 2); 2589} 2590 2591static void 2592alc_setwol_816x(struct alc_softc *sc) 2593{ 2594 struct ifnet *ifp; 2595 uint32_t gphy, mac, master, pmcs, reg; 2596 uint16_t pmstat; 2597 2598 ALC_LOCK_ASSERT(sc); 2599 2600 ifp = sc->alc_ifp; 2601 master = CSR_READ_4(sc, ALC_MASTER_CFG); 2602 master &= ~MASTER_CLK_SEL_DIS; 2603 gphy = CSR_READ_4(sc, ALC_GPHY_CFG); 2604 gphy &= ~(GPHY_CFG_EXT_RESET | GPHY_CFG_LED_MODE | GPHY_CFG_100AB_ENB | 2605 GPHY_CFG_PHY_PLL_ON); 2606 gphy |= GPHY_CFG_HIB_EN | GPHY_CFG_HIB_PULSE | GPHY_CFG_SEL_ANA_RESET; 2607 if ((sc->alc_flags & ALC_FLAG_PM) == 0) { 2608 CSR_WRITE_4(sc, ALC_WOL_CFG, 0); 2609 gphy |= GPHY_CFG_PHY_IDDQ | GPHY_CFG_PWDOWN_HW; 2610 mac = CSR_READ_4(sc, ALC_MAC_CFG); 2611 } else { 2612 if ((ifp->if_capenable & IFCAP_WOL) != 0) { 2613 gphy |= GPHY_CFG_EXT_RESET; 2614 if ((sc->alc_flags & ALC_FLAG_FASTETHER) == 0) 2615 alc_setlinkspeed(sc); 2616 } 2617 pmcs = 0; 2618 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) 2619 pmcs |= WOL_CFG_MAGIC | WOL_CFG_MAGIC_ENB; 2620 CSR_WRITE_4(sc, ALC_WOL_CFG, pmcs); 2621 mac = CSR_READ_4(sc, ALC_MAC_CFG); 2622 mac &= ~(MAC_CFG_DBG | MAC_CFG_PROMISC | MAC_CFG_ALLMULTI | 2623 MAC_CFG_BCAST); 2624 if ((ifp->if_capenable & IFCAP_WOL_MCAST) != 0) 2625 mac |= MAC_CFG_ALLMULTI | MAC_CFG_BCAST; 2626 if ((ifp->if_capenable & IFCAP_WOL) != 0) 2627 mac |= MAC_CFG_RX_ENB; 2628 alc_miiext_writereg(sc, MII_EXT_ANEG, MII_EXT_ANEG_S3DIG10, 2629 ANEG_S3DIG10_SL); 2630 } 2631 2632 /* Enable OSC. */ 2633 reg = CSR_READ_4(sc, ALC_MISC); 2634 reg &= ~MISC_INTNLOSC_OPEN; 2635 CSR_WRITE_4(sc, ALC_MISC, reg); 2636 reg |= MISC_INTNLOSC_OPEN; 2637 CSR_WRITE_4(sc, ALC_MISC, reg); 2638 CSR_WRITE_4(sc, ALC_MASTER_CFG, master); 2639 CSR_WRITE_4(sc, ALC_MAC_CFG, mac); 2640 CSR_WRITE_4(sc, ALC_GPHY_CFG, gphy); 2641 reg = CSR_READ_4(sc, ALC_PDLL_TRNS1); 2642 reg |= PDLL_TRNS1_D3PLLOFF_ENB; 2643 CSR_WRITE_4(sc, ALC_PDLL_TRNS1, reg); 2644 2645 if ((sc->alc_flags & ALC_FLAG_PM) != 0) { 2646 /* Request PME. */ 2647 pmstat = pci_read_config(sc->alc_dev, 2648 sc->alc_pmcap + PCIR_POWER_STATUS, 2); 2649 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); 2650 if ((ifp->if_capenable & IFCAP_WOL) != 0) 2651 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 2652 pci_write_config(sc->alc_dev, 2653 sc->alc_pmcap + PCIR_POWER_STATUS, pmstat, 2); 2654 } 2655} 2656 2657static int 2658alc_suspend(device_t dev) 2659{ 2660 struct alc_softc *sc; 2661 2662 sc = device_get_softc(dev); 2663 2664 ALC_LOCK(sc); 2665 alc_stop(sc); 2666 alc_setwol(sc); 2667 ALC_UNLOCK(sc); 2668 2669 return (0); 2670} 2671 2672static int 2673alc_resume(device_t dev) 2674{ 2675 struct alc_softc *sc; 2676 struct ifnet *ifp; 2677 uint16_t pmstat; 2678 2679 sc = device_get_softc(dev); 2680 2681 ALC_LOCK(sc); 2682 if ((sc->alc_flags & ALC_FLAG_PM) != 0) { 2683 /* Disable PME and clear PME status. */ 2684 pmstat = pci_read_config(sc->alc_dev, 2685 sc->alc_pmcap + PCIR_POWER_STATUS, 2); 2686 if ((pmstat & PCIM_PSTAT_PMEENABLE) != 0) { 2687 pmstat &= ~PCIM_PSTAT_PMEENABLE; 2688 pci_write_config(sc->alc_dev, 2689 sc->alc_pmcap + PCIR_POWER_STATUS, pmstat, 2); 2690 } 2691 } 2692 /* Reset PHY. */ 2693 alc_phy_reset(sc); 2694 ifp = sc->alc_ifp; 2695 if ((ifp->if_flags & IFF_UP) != 0) { 2696 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2697 alc_init_locked(sc); 2698 } 2699 ALC_UNLOCK(sc); 2700 2701 return (0); 2702} 2703 2704static int 2705alc_encap(struct alc_softc *sc, struct mbuf **m_head) 2706{ 2707 struct alc_txdesc *txd, *txd_last; 2708 struct tx_desc *desc; 2709 struct mbuf *m; 2710 struct ip *ip; 2711 struct tcphdr *tcp; 2712 bus_dma_segment_t txsegs[ALC_MAXTXSEGS]; 2713 bus_dmamap_t map; 2714 uint32_t cflags, hdrlen, ip_off, poff, vtag; 2715 int error, idx, nsegs, prod; 2716 2717 ALC_LOCK_ASSERT(sc); 2718 2719 M_ASSERTPKTHDR((*m_head)); 2720 2721 m = *m_head; 2722 ip = NULL; 2723 tcp = NULL; 2724 ip_off = poff = 0; 2725 if ((m->m_pkthdr.csum_flags & (ALC_CSUM_FEATURES | CSUM_TSO)) != 0) { 2726 /* 2727 * AR81[3567]x requires offset of TCP/UDP header in its 2728 * Tx descriptor to perform Tx checksum offloading. TSO 2729 * also requires TCP header offset and modification of 2730 * IP/TCP header. This kind of operation takes many CPU 2731 * cycles on FreeBSD so fast host CPU is required to get 2732 * smooth TSO performance. 2733 */ 2734 struct ether_header *eh; 2735 2736 if (M_WRITABLE(m) == 0) { 2737 /* Get a writable copy. */ 2738 m = m_dup(*m_head, M_NOWAIT); 2739 /* Release original mbufs. */ 2740 m_freem(*m_head); 2741 if (m == NULL) { 2742 *m_head = NULL; 2743 return (ENOBUFS); 2744 } 2745 *m_head = m; 2746 } 2747 2748 ip_off = sizeof(struct ether_header); 2749 m = m_pullup(m, ip_off); 2750 if (m == NULL) { 2751 *m_head = NULL; 2752 return (ENOBUFS); 2753 } 2754 eh = mtod(m, struct ether_header *); 2755 /* 2756 * Check if hardware VLAN insertion is off. 2757 * Additional check for LLC/SNAP frame? 2758 */ 2759 if (eh->ether_type == htons(ETHERTYPE_VLAN)) { 2760 ip_off = sizeof(struct ether_vlan_header); 2761 m = m_pullup(m, ip_off); 2762 if (m == NULL) { 2763 *m_head = NULL; 2764 return (ENOBUFS); 2765 } 2766 } 2767 m = m_pullup(m, ip_off + sizeof(struct ip)); 2768 if (m == NULL) { 2769 *m_head = NULL; 2770 return (ENOBUFS); 2771 } 2772 ip = (struct ip *)(mtod(m, char *) + ip_off); 2773 poff = ip_off + (ip->ip_hl << 2); 2774 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 2775 m = m_pullup(m, poff + sizeof(struct tcphdr)); 2776 if (m == NULL) { 2777 *m_head = NULL; 2778 return (ENOBUFS); 2779 } 2780 tcp = (struct tcphdr *)(mtod(m, char *) + poff); 2781 m = m_pullup(m, poff + (tcp->th_off << 2)); 2782 if (m == NULL) { 2783 *m_head = NULL; 2784 return (ENOBUFS); 2785 } 2786 /* 2787 * Due to strict adherence of Microsoft NDIS 2788 * Large Send specification, hardware expects 2789 * a pseudo TCP checksum inserted by upper 2790 * stack. Unfortunately the pseudo TCP 2791 * checksum that NDIS refers to does not include 2792 * TCP payload length so driver should recompute 2793 * the pseudo checksum here. Hopefully this 2794 * wouldn't be much burden on modern CPUs. 2795 * 2796 * Reset IP checksum and recompute TCP pseudo 2797 * checksum as NDIS specification said. 2798 */ 2799 ip = (struct ip *)(mtod(m, char *) + ip_off); 2800 tcp = (struct tcphdr *)(mtod(m, char *) + poff); 2801 ip->ip_sum = 0; 2802 tcp->th_sum = in_pseudo(ip->ip_src.s_addr, 2803 ip->ip_dst.s_addr, htons(IPPROTO_TCP)); 2804 } 2805 *m_head = m; 2806 } 2807 2808 prod = sc->alc_cdata.alc_tx_prod; 2809 txd = &sc->alc_cdata.alc_txdesc[prod]; 2810 txd_last = txd; 2811 map = txd->tx_dmamap; 2812 2813 error = bus_dmamap_load_mbuf_sg(sc->alc_cdata.alc_tx_tag, map, 2814 *m_head, txsegs, &nsegs, 0); 2815 if (error == EFBIG) { 2816 m = m_collapse(*m_head, M_NOWAIT, ALC_MAXTXSEGS); 2817 if (m == NULL) { 2818 m_freem(*m_head); 2819 *m_head = NULL; 2820 return (ENOMEM); 2821 } 2822 *m_head = m; 2823 error = bus_dmamap_load_mbuf_sg(sc->alc_cdata.alc_tx_tag, map, 2824 *m_head, txsegs, &nsegs, 0); 2825 if (error != 0) { 2826 m_freem(*m_head); 2827 *m_head = NULL; 2828 return (error); 2829 } 2830 } else if (error != 0) 2831 return (error); 2832 if (nsegs == 0) { 2833 m_freem(*m_head); 2834 *m_head = NULL; 2835 return (EIO); 2836 } 2837 2838 /* Check descriptor overrun. */ 2839 if (sc->alc_cdata.alc_tx_cnt + nsegs >= ALC_TX_RING_CNT - 3) { 2840 bus_dmamap_unload(sc->alc_cdata.alc_tx_tag, map); 2841 return (ENOBUFS); 2842 } 2843 bus_dmamap_sync(sc->alc_cdata.alc_tx_tag, map, BUS_DMASYNC_PREWRITE); 2844 2845 m = *m_head; 2846 cflags = TD_ETHERNET; 2847 vtag = 0; 2848 desc = NULL; 2849 idx = 0; 2850 /* Configure VLAN hardware tag insertion. */ 2851 if ((m->m_flags & M_VLANTAG) != 0) { 2852 vtag = htons(m->m_pkthdr.ether_vtag); 2853 vtag = (vtag << TD_VLAN_SHIFT) & TD_VLAN_MASK; 2854 cflags |= TD_INS_VLAN_TAG; 2855 } 2856 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 2857 /* Request TSO and set MSS. */ 2858 cflags |= TD_TSO | TD_TSO_DESCV1; 2859 cflags |= ((uint32_t)m->m_pkthdr.tso_segsz << TD_MSS_SHIFT) & 2860 TD_MSS_MASK; 2861 /* Set TCP header offset. */ 2862 cflags |= (poff << TD_TCPHDR_OFFSET_SHIFT) & 2863 TD_TCPHDR_OFFSET_MASK; 2864 /* 2865 * AR81[3567]x requires the first buffer should 2866 * only hold IP/TCP header data. Payload should 2867 * be handled in other descriptors. 2868 */ 2869 hdrlen = poff + (tcp->th_off << 2); 2870 desc = &sc->alc_rdata.alc_tx_ring[prod]; 2871 desc->len = htole32(TX_BYTES(hdrlen | vtag)); 2872 desc->flags = htole32(cflags); 2873 desc->addr = htole64(txsegs[0].ds_addr); 2874 sc->alc_cdata.alc_tx_cnt++; 2875 ALC_DESC_INC(prod, ALC_TX_RING_CNT); 2876 if (m->m_len - hdrlen > 0) { 2877 /* Handle remaining payload of the first fragment. */ 2878 desc = &sc->alc_rdata.alc_tx_ring[prod]; 2879 desc->len = htole32(TX_BYTES((m->m_len - hdrlen) | 2880 vtag)); 2881 desc->flags = htole32(cflags); 2882 desc->addr = htole64(txsegs[0].ds_addr + hdrlen); 2883 sc->alc_cdata.alc_tx_cnt++; 2884 ALC_DESC_INC(prod, ALC_TX_RING_CNT); 2885 } 2886 /* Handle remaining fragments. */ 2887 idx = 1; 2888 } else if ((m->m_pkthdr.csum_flags & ALC_CSUM_FEATURES) != 0) { 2889 /* Configure Tx checksum offload. */ 2890#ifdef ALC_USE_CUSTOM_CSUM 2891 cflags |= TD_CUSTOM_CSUM; 2892 /* Set checksum start offset. */ 2893 cflags |= ((poff >> 1) << TD_PLOAD_OFFSET_SHIFT) & 2894 TD_PLOAD_OFFSET_MASK; 2895 /* Set checksum insertion position of TCP/UDP. */ 2896 cflags |= (((poff + m->m_pkthdr.csum_data) >> 1) << 2897 TD_CUSTOM_CSUM_OFFSET_SHIFT) & TD_CUSTOM_CSUM_OFFSET_MASK; 2898#else 2899 if ((m->m_pkthdr.csum_flags & CSUM_IP) != 0) 2900 cflags |= TD_IPCSUM; 2901 if ((m->m_pkthdr.csum_flags & CSUM_TCP) != 0) 2902 cflags |= TD_TCPCSUM; 2903 if ((m->m_pkthdr.csum_flags & CSUM_UDP) != 0) 2904 cflags |= TD_UDPCSUM; 2905 /* Set TCP/UDP header offset. */ 2906 cflags |= (poff << TD_L4HDR_OFFSET_SHIFT) & 2907 TD_L4HDR_OFFSET_MASK; 2908#endif 2909 } 2910 for (; idx < nsegs; idx++) { 2911 desc = &sc->alc_rdata.alc_tx_ring[prod]; 2912 desc->len = htole32(TX_BYTES(txsegs[idx].ds_len) | vtag); 2913 desc->flags = htole32(cflags); 2914 desc->addr = htole64(txsegs[idx].ds_addr); 2915 sc->alc_cdata.alc_tx_cnt++; 2916 ALC_DESC_INC(prod, ALC_TX_RING_CNT); 2917 } 2918 /* Update producer index. */ 2919 sc->alc_cdata.alc_tx_prod = prod; 2920 2921 /* Finally set EOP on the last descriptor. */ 2922 prod = (prod + ALC_TX_RING_CNT - 1) % ALC_TX_RING_CNT; 2923 desc = &sc->alc_rdata.alc_tx_ring[prod]; 2924 desc->flags |= htole32(TD_EOP); 2925 2926 /* Swap dmamap of the first and the last. */ 2927 txd = &sc->alc_cdata.alc_txdesc[prod]; 2928 map = txd_last->tx_dmamap; 2929 txd_last->tx_dmamap = txd->tx_dmamap; 2930 txd->tx_dmamap = map; 2931 txd->tx_m = m; 2932 2933 return (0); 2934} 2935 2936static void 2937alc_start(struct ifnet *ifp) 2938{ 2939 struct alc_softc *sc; 2940 2941 sc = ifp->if_softc; 2942 ALC_LOCK(sc); 2943 alc_start_locked(ifp); 2944 ALC_UNLOCK(sc); 2945} 2946 2947static void 2948alc_start_locked(struct ifnet *ifp) 2949{ 2950 struct alc_softc *sc; 2951 struct mbuf *m_head; 2952 int enq; 2953 2954 sc = ifp->if_softc; 2955 2956 ALC_LOCK_ASSERT(sc); 2957 2958 /* Reclaim transmitted frames. */ 2959 if (sc->alc_cdata.alc_tx_cnt >= ALC_TX_DESC_HIWAT) 2960 alc_txeof(sc); 2961 2962 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 2963 IFF_DRV_RUNNING || (sc->alc_flags & ALC_FLAG_LINK) == 0) 2964 return; 2965 2966 for (enq = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd); ) { 2967 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 2968 if (m_head == NULL) 2969 break; 2970 /* 2971 * Pack the data into the transmit ring. If we 2972 * don't have room, set the OACTIVE flag and wait 2973 * for the NIC to drain the ring. 2974 */ 2975 if (alc_encap(sc, &m_head)) { 2976 if (m_head == NULL) 2977 break; 2978 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 2979 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 2980 break; 2981 } 2982 2983 enq++; 2984 /* 2985 * If there's a BPF listener, bounce a copy of this frame 2986 * to him. 2987 */ 2988 ETHER_BPF_MTAP(ifp, m_head); 2989 } 2990 2991 if (enq > 0) 2992 alc_start_tx(sc); 2993} 2994 2995static void 2996alc_start_tx(struct alc_softc *sc) 2997{ 2998 2999 /* Sync descriptors. */ 3000 bus_dmamap_sync(sc->alc_cdata.alc_tx_ring_tag, 3001 sc->alc_cdata.alc_tx_ring_map, BUS_DMASYNC_PREWRITE); 3002 /* Kick. Assume we're using normal Tx priority queue. */ 3003 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 3004 CSR_WRITE_2(sc, ALC_MBOX_TD_PRI0_PROD_IDX, 3005 (uint16_t)sc->alc_cdata.alc_tx_prod); 3006 else 3007 CSR_WRITE_4(sc, ALC_MBOX_TD_PROD_IDX, 3008 (sc->alc_cdata.alc_tx_prod << 3009 MBOX_TD_PROD_LO_IDX_SHIFT) & 3010 MBOX_TD_PROD_LO_IDX_MASK); 3011 /* Set a timeout in case the chip goes out to lunch. */ 3012 sc->alc_watchdog_timer = ALC_TX_TIMEOUT; 3013} 3014 3015static void 3016alc_watchdog(struct alc_softc *sc) 3017{ 3018 struct ifnet *ifp; 3019 3020 ALC_LOCK_ASSERT(sc); 3021 3022 if (sc->alc_watchdog_timer == 0 || --sc->alc_watchdog_timer) 3023 return; 3024 3025 ifp = sc->alc_ifp; 3026 if ((sc->alc_flags & ALC_FLAG_LINK) == 0) { 3027 if_printf(sc->alc_ifp, "watchdog timeout (lost link)\n"); 3028 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 3029 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 3030 alc_init_locked(sc); 3031 return; 3032 } 3033 if_printf(sc->alc_ifp, "watchdog timeout -- resetting\n"); 3034 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 3035 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 3036 alc_init_locked(sc); 3037 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 3038 alc_start_locked(ifp); 3039} 3040 3041static int 3042alc_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 3043{ 3044 struct alc_softc *sc; 3045 struct ifreq *ifr; 3046 struct mii_data *mii; 3047 int error, mask; 3048 3049 sc = ifp->if_softc; 3050 ifr = (struct ifreq *)data; 3051 error = 0; 3052 switch (cmd) { 3053 case SIOCSIFMTU: 3054 if (ifr->ifr_mtu < ETHERMIN || 3055 ifr->ifr_mtu > (sc->alc_ident->max_framelen - 3056 sizeof(struct ether_vlan_header) - ETHER_CRC_LEN) || 3057 ((sc->alc_flags & ALC_FLAG_JUMBO) == 0 && 3058 ifr->ifr_mtu > ETHERMTU)) 3059 error = EINVAL; 3060 else if (ifp->if_mtu != ifr->ifr_mtu) { 3061 ALC_LOCK(sc); 3062 ifp->if_mtu = ifr->ifr_mtu; 3063 /* AR81[3567]x has 13 bits MSS field. */ 3064 if (ifp->if_mtu > ALC_TSO_MTU && 3065 (ifp->if_capenable & IFCAP_TSO4) != 0) { 3066 ifp->if_capenable &= ~IFCAP_TSO4; 3067 ifp->if_hwassist &= ~CSUM_TSO; 3068 VLAN_CAPABILITIES(ifp); 3069 } 3070 ALC_UNLOCK(sc); 3071 } 3072 break; 3073 case SIOCSIFFLAGS: 3074 ALC_LOCK(sc); 3075 if ((ifp->if_flags & IFF_UP) != 0) { 3076 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0 && 3077 ((ifp->if_flags ^ sc->alc_if_flags) & 3078 (IFF_PROMISC | IFF_ALLMULTI)) != 0) 3079 alc_rxfilter(sc); 3080 else 3081 alc_init_locked(sc); 3082 } else if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 3083 alc_stop(sc); 3084 sc->alc_if_flags = ifp->if_flags; 3085 ALC_UNLOCK(sc); 3086 break; 3087 case SIOCADDMULTI: 3088 case SIOCDELMULTI: 3089 ALC_LOCK(sc); 3090 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 3091 alc_rxfilter(sc); 3092 ALC_UNLOCK(sc); 3093 break; 3094 case SIOCSIFMEDIA: 3095 case SIOCGIFMEDIA: 3096 mii = device_get_softc(sc->alc_miibus); 3097 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd); 3098 break; 3099 case SIOCSIFCAP: 3100 ALC_LOCK(sc); 3101 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 3102 if ((mask & IFCAP_TXCSUM) != 0 && 3103 (ifp->if_capabilities & IFCAP_TXCSUM) != 0) { 3104 ifp->if_capenable ^= IFCAP_TXCSUM; 3105 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0) 3106 ifp->if_hwassist |= ALC_CSUM_FEATURES; 3107 else 3108 ifp->if_hwassist &= ~ALC_CSUM_FEATURES; 3109 } 3110 if ((mask & IFCAP_TSO4) != 0 && 3111 (ifp->if_capabilities & IFCAP_TSO4) != 0) { 3112 ifp->if_capenable ^= IFCAP_TSO4; 3113 if ((ifp->if_capenable & IFCAP_TSO4) != 0) { 3114 /* AR81[3567]x has 13 bits MSS field. */ 3115 if (ifp->if_mtu > ALC_TSO_MTU) { 3116 ifp->if_capenable &= ~IFCAP_TSO4; 3117 ifp->if_hwassist &= ~CSUM_TSO; 3118 } else 3119 ifp->if_hwassist |= CSUM_TSO; 3120 } else 3121 ifp->if_hwassist &= ~CSUM_TSO; 3122 } 3123 if ((mask & IFCAP_WOL_MCAST) != 0 && 3124 (ifp->if_capabilities & IFCAP_WOL_MCAST) != 0) 3125 ifp->if_capenable ^= IFCAP_WOL_MCAST; 3126 if ((mask & IFCAP_WOL_MAGIC) != 0 && 3127 (ifp->if_capabilities & IFCAP_WOL_MAGIC) != 0) 3128 ifp->if_capenable ^= IFCAP_WOL_MAGIC; 3129 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 && 3130 (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) != 0) { 3131 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 3132 alc_rxvlan(sc); 3133 } 3134 if ((mask & IFCAP_VLAN_HWCSUM) != 0 && 3135 (ifp->if_capabilities & IFCAP_VLAN_HWCSUM) != 0) 3136 ifp->if_capenable ^= IFCAP_VLAN_HWCSUM; 3137 if ((mask & IFCAP_VLAN_HWTSO) != 0 && 3138 (ifp->if_capabilities & IFCAP_VLAN_HWTSO) != 0) 3139 ifp->if_capenable ^= IFCAP_VLAN_HWTSO; 3140 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) == 0) 3141 ifp->if_capenable &= 3142 ~(IFCAP_VLAN_HWTSO | IFCAP_VLAN_HWCSUM); 3143 ALC_UNLOCK(sc); 3144 VLAN_CAPABILITIES(ifp); 3145 break; 3146 default: 3147 error = ether_ioctl(ifp, cmd, data); 3148 break; 3149 } 3150 3151 return (error); 3152} 3153 3154static void 3155alc_mac_config(struct alc_softc *sc) 3156{ 3157 struct mii_data *mii; 3158 uint32_t reg; 3159 3160 ALC_LOCK_ASSERT(sc); 3161 3162 mii = device_get_softc(sc->alc_miibus); 3163 reg = CSR_READ_4(sc, ALC_MAC_CFG); 3164 reg &= ~(MAC_CFG_FULL_DUPLEX | MAC_CFG_TX_FC | MAC_CFG_RX_FC | 3165 MAC_CFG_SPEED_MASK); 3166 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0 || 3167 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151 || 3168 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151_V2 || 3169 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B2) 3170 reg |= MAC_CFG_HASH_ALG_CRC32 | MAC_CFG_SPEED_MODE_SW; 3171 /* Reprogram MAC with resolved speed/duplex. */ 3172 switch (IFM_SUBTYPE(mii->mii_media_active)) { 3173 case IFM_10_T: 3174 case IFM_100_TX: 3175 reg |= MAC_CFG_SPEED_10_100; 3176 break; 3177 case IFM_1000_T: 3178 reg |= MAC_CFG_SPEED_1000; 3179 break; 3180 } 3181 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 3182 reg |= MAC_CFG_FULL_DUPLEX; 3183 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0) 3184 reg |= MAC_CFG_TX_FC; 3185 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0) 3186 reg |= MAC_CFG_RX_FC; 3187 } 3188 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 3189} 3190 3191static void 3192alc_stats_clear(struct alc_softc *sc) 3193{ 3194 struct smb sb, *smb; 3195 uint32_t *reg; 3196 int i; 3197 3198 if ((sc->alc_flags & ALC_FLAG_SMB_BUG) == 0) { 3199 bus_dmamap_sync(sc->alc_cdata.alc_smb_tag, 3200 sc->alc_cdata.alc_smb_map, 3201 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 3202 smb = sc->alc_rdata.alc_smb; 3203 /* Update done, clear. */ 3204 smb->updated = 0; 3205 bus_dmamap_sync(sc->alc_cdata.alc_smb_tag, 3206 sc->alc_cdata.alc_smb_map, 3207 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3208 } else { 3209 for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered; 3210 reg++) { 3211 CSR_READ_4(sc, ALC_RX_MIB_BASE + i); 3212 i += sizeof(uint32_t); 3213 } 3214 /* Read Tx statistics. */ 3215 for (reg = &sb.tx_frames, i = 0; reg <= &sb.tx_mcast_bytes; 3216 reg++) { 3217 CSR_READ_4(sc, ALC_TX_MIB_BASE + i); 3218 i += sizeof(uint32_t); 3219 } 3220 } 3221} 3222 3223static void 3224alc_stats_update(struct alc_softc *sc) 3225{ 3226 struct alc_hw_stats *stat; 3227 struct smb sb, *smb; 3228 struct ifnet *ifp; 3229 uint32_t *reg; 3230 int i; 3231 3232 ALC_LOCK_ASSERT(sc); 3233 3234 ifp = sc->alc_ifp; 3235 stat = &sc->alc_stats; 3236 if ((sc->alc_flags & ALC_FLAG_SMB_BUG) == 0) { 3237 bus_dmamap_sync(sc->alc_cdata.alc_smb_tag, 3238 sc->alc_cdata.alc_smb_map, 3239 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 3240 smb = sc->alc_rdata.alc_smb; 3241 if (smb->updated == 0) 3242 return; 3243 } else { 3244 smb = &sb; 3245 /* Read Rx statistics. */ 3246 for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered; 3247 reg++) { 3248 *reg = CSR_READ_4(sc, ALC_RX_MIB_BASE + i); 3249 i += sizeof(uint32_t); 3250 } 3251 /* Read Tx statistics. */ 3252 for (reg = &sb.tx_frames, i = 0; reg <= &sb.tx_mcast_bytes; 3253 reg++) { 3254 *reg = CSR_READ_4(sc, ALC_TX_MIB_BASE + i); 3255 i += sizeof(uint32_t); 3256 } 3257 } 3258 3259 /* Rx stats. */ 3260 stat->rx_frames += smb->rx_frames; 3261 stat->rx_bcast_frames += smb->rx_bcast_frames; 3262 stat->rx_mcast_frames += smb->rx_mcast_frames; 3263 stat->rx_pause_frames += smb->rx_pause_frames; 3264 stat->rx_control_frames += smb->rx_control_frames; 3265 stat->rx_crcerrs += smb->rx_crcerrs; 3266 stat->rx_lenerrs += smb->rx_lenerrs; 3267 stat->rx_bytes += smb->rx_bytes; 3268 stat->rx_runts += smb->rx_runts; 3269 stat->rx_fragments += smb->rx_fragments; 3270 stat->rx_pkts_64 += smb->rx_pkts_64; 3271 stat->rx_pkts_65_127 += smb->rx_pkts_65_127; 3272 stat->rx_pkts_128_255 += smb->rx_pkts_128_255; 3273 stat->rx_pkts_256_511 += smb->rx_pkts_256_511; 3274 stat->rx_pkts_512_1023 += smb->rx_pkts_512_1023; 3275 stat->rx_pkts_1024_1518 += smb->rx_pkts_1024_1518; 3276 stat->rx_pkts_1519_max += smb->rx_pkts_1519_max; 3277 stat->rx_pkts_truncated += smb->rx_pkts_truncated; 3278 stat->rx_fifo_oflows += smb->rx_fifo_oflows; 3279 stat->rx_rrs_errs += smb->rx_rrs_errs; 3280 stat->rx_alignerrs += smb->rx_alignerrs; 3281 stat->rx_bcast_bytes += smb->rx_bcast_bytes; 3282 stat->rx_mcast_bytes += smb->rx_mcast_bytes; 3283 stat->rx_pkts_filtered += smb->rx_pkts_filtered; 3284 3285 /* Tx stats. */ 3286 stat->tx_frames += smb->tx_frames; 3287 stat->tx_bcast_frames += smb->tx_bcast_frames; 3288 stat->tx_mcast_frames += smb->tx_mcast_frames; 3289 stat->tx_pause_frames += smb->tx_pause_frames; 3290 stat->tx_excess_defer += smb->tx_excess_defer; 3291 stat->tx_control_frames += smb->tx_control_frames; 3292 stat->tx_deferred += smb->tx_deferred; 3293 stat->tx_bytes += smb->tx_bytes; 3294 stat->tx_pkts_64 += smb->tx_pkts_64; 3295 stat->tx_pkts_65_127 += smb->tx_pkts_65_127; 3296 stat->tx_pkts_128_255 += smb->tx_pkts_128_255; 3297 stat->tx_pkts_256_511 += smb->tx_pkts_256_511; 3298 stat->tx_pkts_512_1023 += smb->tx_pkts_512_1023; 3299 stat->tx_pkts_1024_1518 += smb->tx_pkts_1024_1518; 3300 stat->tx_pkts_1519_max += smb->tx_pkts_1519_max; 3301 stat->tx_single_colls += smb->tx_single_colls; 3302 stat->tx_multi_colls += smb->tx_multi_colls; 3303 stat->tx_late_colls += smb->tx_late_colls; 3304 stat->tx_excess_colls += smb->tx_excess_colls; 3305 stat->tx_underrun += smb->tx_underrun; 3306 stat->tx_desc_underrun += smb->tx_desc_underrun; 3307 stat->tx_lenerrs += smb->tx_lenerrs; 3308 stat->tx_pkts_truncated += smb->tx_pkts_truncated; 3309 stat->tx_bcast_bytes += smb->tx_bcast_bytes; 3310 stat->tx_mcast_bytes += smb->tx_mcast_bytes; 3311 3312 /* Update counters in ifnet. */ 3313 if_inc_counter(ifp, IFCOUNTER_OPACKETS, smb->tx_frames); 3314 3315 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, smb->tx_single_colls + 3316 smb->tx_multi_colls * 2 + smb->tx_late_colls + 3317 smb->tx_excess_colls * HDPX_CFG_RETRY_DEFAULT); 3318 3319 if_inc_counter(ifp, IFCOUNTER_OERRORS, smb->tx_late_colls + 3320 smb->tx_excess_colls + smb->tx_underrun + smb->tx_pkts_truncated); 3321 3322 if_inc_counter(ifp, IFCOUNTER_IPACKETS, smb->rx_frames); 3323 3324 if_inc_counter(ifp, IFCOUNTER_IERRORS, 3325 smb->rx_crcerrs + smb->rx_lenerrs + 3326 smb->rx_runts + smb->rx_pkts_truncated + 3327 smb->rx_fifo_oflows + smb->rx_rrs_errs + 3328 smb->rx_alignerrs); 3329 3330 if ((sc->alc_flags & ALC_FLAG_SMB_BUG) == 0) { 3331 /* Update done, clear. */ 3332 smb->updated = 0; 3333 bus_dmamap_sync(sc->alc_cdata.alc_smb_tag, 3334 sc->alc_cdata.alc_smb_map, 3335 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3336 } 3337} 3338 3339static int 3340alc_intr(void *arg) 3341{ 3342 struct alc_softc *sc; 3343 uint32_t status; 3344 3345 sc = (struct alc_softc *)arg; 3346 3347 if (sc->alc_flags & ALC_FLAG_MT) { 3348 taskqueue_enqueue(sc->alc_tq, &sc->alc_int_task); 3349 return (FILTER_HANDLED); 3350 } 3351 3352 status = CSR_READ_4(sc, ALC_INTR_STATUS); 3353 if ((status & ALC_INTRS) == 0) 3354 return (FILTER_STRAY); 3355 /* Disable interrupts. */ 3356 CSR_WRITE_4(sc, ALC_INTR_STATUS, INTR_DIS_INT); 3357 taskqueue_enqueue(sc->alc_tq, &sc->alc_int_task); 3358 3359 return (FILTER_HANDLED); 3360} 3361 3362static void 3363alc_int_task(void *arg, int pending) 3364{ 3365 struct alc_softc *sc; 3366 struct ifnet *ifp; 3367 uint32_t status; 3368 int more; 3369 3370 sc = (struct alc_softc *)arg; 3371 ifp = sc->alc_ifp; 3372 3373 status = CSR_READ_4(sc, ALC_INTR_STATUS); 3374 ALC_LOCK(sc); 3375 if (sc->alc_morework != 0) { 3376 sc->alc_morework = 0; 3377 status |= INTR_RX_PKT; 3378 } 3379 if ((status & ALC_INTRS) == 0) 3380 goto done; 3381 3382 /* Acknowledge interrupts but still disable interrupts. */ 3383 CSR_WRITE_4(sc, ALC_INTR_STATUS, status | INTR_DIS_INT); 3384 3385 more = 0; 3386 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 3387 if ((status & INTR_RX_PKT) != 0) { 3388 more = alc_rxintr(sc, sc->alc_process_limit); 3389 if (more == EAGAIN) 3390 sc->alc_morework = 1; 3391 else if (more == EIO) { 3392 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 3393 alc_init_locked(sc); 3394 ALC_UNLOCK(sc); 3395 return; 3396 } 3397 } 3398 if ((status & (INTR_DMA_RD_TO_RST | INTR_DMA_WR_TO_RST | 3399 INTR_TXQ_TO_RST)) != 0) { 3400 if ((status & INTR_DMA_RD_TO_RST) != 0) 3401 device_printf(sc->alc_dev, 3402 "DMA read error! -- resetting\n"); 3403 if ((status & INTR_DMA_WR_TO_RST) != 0) 3404 device_printf(sc->alc_dev, 3405 "DMA write error! -- resetting\n"); 3406 if ((status & INTR_TXQ_TO_RST) != 0) 3407 device_printf(sc->alc_dev, 3408 "TxQ reset! -- resetting\n"); 3409 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 3410 alc_init_locked(sc); 3411 ALC_UNLOCK(sc); 3412 return; 3413 } 3414 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0 && 3415 !IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 3416 alc_start_locked(ifp); 3417 } 3418 3419 if (more == EAGAIN || 3420 (CSR_READ_4(sc, ALC_INTR_STATUS) & ALC_INTRS) != 0) { 3421 ALC_UNLOCK(sc); 3422 taskqueue_enqueue(sc->alc_tq, &sc->alc_int_task); 3423 return; 3424 } 3425 3426done: 3427 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 3428 /* Re-enable interrupts if we're running. */ 3429 if (sc->alc_flags & ALC_FLAG_MT) 3430 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0); 3431 else 3432 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0x7FFFFFFF); 3433 } 3434 ALC_UNLOCK(sc); 3435} 3436 3437static void 3438alc_txeof(struct alc_softc *sc) 3439{ 3440 struct ifnet *ifp; 3441 struct alc_txdesc *txd; 3442 uint32_t cons, prod; 3443 int prog; 3444 3445 ALC_LOCK_ASSERT(sc); 3446 3447 ifp = sc->alc_ifp; 3448 3449 if (sc->alc_cdata.alc_tx_cnt == 0) 3450 return; 3451 bus_dmamap_sync(sc->alc_cdata.alc_tx_ring_tag, 3452 sc->alc_cdata.alc_tx_ring_map, BUS_DMASYNC_POSTWRITE); 3453 if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0) { 3454 bus_dmamap_sync(sc->alc_cdata.alc_cmb_tag, 3455 sc->alc_cdata.alc_cmb_map, BUS_DMASYNC_POSTREAD); 3456 prod = sc->alc_rdata.alc_cmb->cons; 3457 } else { 3458 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 3459 prod = CSR_READ_2(sc, ALC_MBOX_TD_PRI0_CONS_IDX); 3460 else { 3461 prod = CSR_READ_4(sc, ALC_MBOX_TD_CONS_IDX); 3462 /* Assume we're using normal Tx priority queue. */ 3463 prod = (prod & MBOX_TD_CONS_LO_IDX_MASK) >> 3464 MBOX_TD_CONS_LO_IDX_SHIFT; 3465 } 3466 } 3467 cons = sc->alc_cdata.alc_tx_cons; 3468 /* 3469 * Go through our Tx list and free mbufs for those 3470 * frames which have been transmitted. 3471 */ 3472 for (prog = 0; cons != prod; prog++, 3473 ALC_DESC_INC(cons, ALC_TX_RING_CNT)) { 3474 if (sc->alc_cdata.alc_tx_cnt <= 0) 3475 break; 3476 prog++; 3477 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 3478 sc->alc_cdata.alc_tx_cnt--; 3479 txd = &sc->alc_cdata.alc_txdesc[cons]; 3480 if (txd->tx_m != NULL) { 3481 /* Reclaim transmitted mbufs. */ 3482 bus_dmamap_sync(sc->alc_cdata.alc_tx_tag, 3483 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 3484 bus_dmamap_unload(sc->alc_cdata.alc_tx_tag, 3485 txd->tx_dmamap); 3486 m_freem(txd->tx_m); 3487 txd->tx_m = NULL; 3488 } 3489 } 3490 3491 if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0) 3492 bus_dmamap_sync(sc->alc_cdata.alc_cmb_tag, 3493 sc->alc_cdata.alc_cmb_map, BUS_DMASYNC_PREREAD); 3494 sc->alc_cdata.alc_tx_cons = cons; 3495 /* 3496 * Unarm watchdog timer only when there is no pending 3497 * frames in Tx queue. 3498 */ 3499 if (sc->alc_cdata.alc_tx_cnt == 0) 3500 sc->alc_watchdog_timer = 0; 3501} 3502 3503static int 3504alc_newbuf(struct alc_softc *sc, struct alc_rxdesc *rxd) 3505{ 3506 struct mbuf *m; 3507 bus_dma_segment_t segs[1]; 3508 bus_dmamap_t map; 3509 int nsegs; 3510 3511 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 3512 if (m == NULL) 3513 return (ENOBUFS); 3514 m->m_len = m->m_pkthdr.len = RX_BUF_SIZE_MAX; 3515#ifndef __NO_STRICT_ALIGNMENT 3516 m_adj(m, sizeof(uint64_t)); 3517#endif 3518 3519 if (bus_dmamap_load_mbuf_sg(sc->alc_cdata.alc_rx_tag, 3520 sc->alc_cdata.alc_rx_sparemap, m, segs, &nsegs, 0) != 0) { 3521 m_freem(m); 3522 return (ENOBUFS); 3523 } 3524 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 3525 3526 if (rxd->rx_m != NULL) { 3527 bus_dmamap_sync(sc->alc_cdata.alc_rx_tag, rxd->rx_dmamap, 3528 BUS_DMASYNC_POSTREAD); 3529 bus_dmamap_unload(sc->alc_cdata.alc_rx_tag, rxd->rx_dmamap); 3530 } 3531 map = rxd->rx_dmamap; 3532 rxd->rx_dmamap = sc->alc_cdata.alc_rx_sparemap; 3533 sc->alc_cdata.alc_rx_sparemap = map; 3534 bus_dmamap_sync(sc->alc_cdata.alc_rx_tag, rxd->rx_dmamap, 3535 BUS_DMASYNC_PREREAD); 3536 rxd->rx_m = m; 3537 rxd->rx_desc->addr = htole64(segs[0].ds_addr); 3538 return (0); 3539} 3540 3541static int 3542alc_rxintr(struct alc_softc *sc, int count) 3543{ 3544 struct ifnet *ifp; 3545 struct rx_rdesc *rrd; 3546 uint32_t nsegs, status; 3547 int rr_cons, prog; 3548 3549 bus_dmamap_sync(sc->alc_cdata.alc_rr_ring_tag, 3550 sc->alc_cdata.alc_rr_ring_map, 3551 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 3552 bus_dmamap_sync(sc->alc_cdata.alc_rx_ring_tag, 3553 sc->alc_cdata.alc_rx_ring_map, BUS_DMASYNC_POSTWRITE); 3554 rr_cons = sc->alc_cdata.alc_rr_cons; 3555 ifp = sc->alc_ifp; 3556 for (prog = 0; (ifp->if_drv_flags & IFF_DRV_RUNNING) != 0;) { 3557 if (count-- <= 0) 3558 break; 3559 rrd = &sc->alc_rdata.alc_rr_ring[rr_cons]; 3560 status = le32toh(rrd->status); 3561 if ((status & RRD_VALID) == 0) 3562 break; 3563 nsegs = RRD_RD_CNT(le32toh(rrd->rdinfo)); 3564 if (nsegs == 0) { 3565 /* This should not happen! */ 3566 device_printf(sc->alc_dev, 3567 "unexpected segment count -- resetting\n"); 3568 return (EIO); 3569 } 3570 alc_rxeof(sc, rrd); 3571 /* Clear Rx return status. */ 3572 rrd->status = 0; 3573 ALC_DESC_INC(rr_cons, ALC_RR_RING_CNT); 3574 sc->alc_cdata.alc_rx_cons += nsegs; 3575 sc->alc_cdata.alc_rx_cons %= ALC_RR_RING_CNT; 3576 prog += nsegs; 3577 } 3578 3579 if (prog > 0) { 3580 /* Update the consumer index. */ 3581 sc->alc_cdata.alc_rr_cons = rr_cons; 3582 /* Sync Rx return descriptors. */ 3583 bus_dmamap_sync(sc->alc_cdata.alc_rr_ring_tag, 3584 sc->alc_cdata.alc_rr_ring_map, 3585 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3586 /* 3587 * Sync updated Rx descriptors such that controller see 3588 * modified buffer addresses. 3589 */ 3590 bus_dmamap_sync(sc->alc_cdata.alc_rx_ring_tag, 3591 sc->alc_cdata.alc_rx_ring_map, BUS_DMASYNC_PREWRITE); 3592 /* 3593 * Let controller know availability of new Rx buffers. 3594 * Since alc(4) use RXQ_CFG_RD_BURST_DEFAULT descriptors 3595 * it may be possible to update ALC_MBOX_RD0_PROD_IDX 3596 * only when Rx buffer pre-fetching is required. In 3597 * addition we already set ALC_RX_RD_FREE_THRESH to 3598 * RX_RD_FREE_THRESH_LO_DEFAULT descriptors. However 3599 * it still seems that pre-fetching needs more 3600 * experimentation. 3601 */ 3602 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 3603 CSR_WRITE_2(sc, ALC_MBOX_RD0_PROD_IDX, 3604 (uint16_t)sc->alc_cdata.alc_rx_cons); 3605 else 3606 CSR_WRITE_4(sc, ALC_MBOX_RD0_PROD_IDX, 3607 sc->alc_cdata.alc_rx_cons); 3608 } 3609 3610 return (count > 0 ? 0 : EAGAIN); 3611} 3612 3613#ifndef __NO_STRICT_ALIGNMENT 3614static struct mbuf * 3615alc_fixup_rx(struct ifnet *ifp, struct mbuf *m) 3616{ 3617 struct mbuf *n; 3618 int i; 3619 uint16_t *src, *dst; 3620 3621 src = mtod(m, uint16_t *); 3622 dst = src - 3; 3623 3624 if (m->m_next == NULL) { 3625 for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++) 3626 *dst++ = *src++; 3627 m->m_data -= 6; 3628 return (m); 3629 } 3630 /* 3631 * Append a new mbuf to received mbuf chain and copy ethernet 3632 * header from the mbuf chain. This can save lots of CPU 3633 * cycles for jumbo frame. 3634 */ 3635 MGETHDR(n, M_NOWAIT, MT_DATA); 3636 if (n == NULL) { 3637 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1); 3638 m_freem(m); 3639 return (NULL); 3640 } 3641 bcopy(m->m_data, n->m_data, ETHER_HDR_LEN); 3642 m->m_data += ETHER_HDR_LEN; 3643 m->m_len -= ETHER_HDR_LEN; 3644 n->m_len = ETHER_HDR_LEN; 3645 M_MOVE_PKTHDR(n, m); 3646 n->m_next = m; 3647 return (n); 3648} 3649#endif 3650 3651/* Receive a frame. */ 3652static void 3653alc_rxeof(struct alc_softc *sc, struct rx_rdesc *rrd) 3654{ 3655 struct alc_rxdesc *rxd; 3656 struct ifnet *ifp; 3657 struct mbuf *mp, *m; 3658 uint32_t rdinfo, status, vtag; 3659 int count, nsegs, rx_cons; 3660 3661 ifp = sc->alc_ifp; 3662 status = le32toh(rrd->status); 3663 rdinfo = le32toh(rrd->rdinfo); 3664 rx_cons = RRD_RD_IDX(rdinfo); 3665 nsegs = RRD_RD_CNT(rdinfo); 3666 3667 sc->alc_cdata.alc_rxlen = RRD_BYTES(status); 3668 if ((status & (RRD_ERR_SUM | RRD_ERR_LENGTH)) != 0) { 3669 /* 3670 * We want to pass the following frames to upper 3671 * layer regardless of error status of Rx return 3672 * ring. 3673 * 3674 * o IP/TCP/UDP checksum is bad. 3675 * o frame length and protocol specific length 3676 * does not match. 3677 * 3678 * Force network stack compute checksum for 3679 * errored frames. 3680 */ 3681 status |= RRD_TCP_UDPCSUM_NOK | RRD_IPCSUM_NOK; 3682 if ((status & (RRD_ERR_CRC | RRD_ERR_ALIGN | 3683 RRD_ERR_TRUNC | RRD_ERR_RUNT)) != 0) 3684 return; 3685 } 3686 3687 for (count = 0; count < nsegs; count++, 3688 ALC_DESC_INC(rx_cons, ALC_RX_RING_CNT)) { 3689 rxd = &sc->alc_cdata.alc_rxdesc[rx_cons]; 3690 mp = rxd->rx_m; 3691 /* Add a new receive buffer to the ring. */ 3692 if (alc_newbuf(sc, rxd) != 0) { 3693 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1); 3694 /* Reuse Rx buffers. */ 3695 if (sc->alc_cdata.alc_rxhead != NULL) 3696 m_freem(sc->alc_cdata.alc_rxhead); 3697 break; 3698 } 3699 3700 /* 3701 * Assume we've received a full sized frame. 3702 * Actual size is fixed when we encounter the end of 3703 * multi-segmented frame. 3704 */ 3705 mp->m_len = sc->alc_buf_size; 3706 3707 /* Chain received mbufs. */ 3708 if (sc->alc_cdata.alc_rxhead == NULL) { 3709 sc->alc_cdata.alc_rxhead = mp; 3710 sc->alc_cdata.alc_rxtail = mp; 3711 } else { 3712 mp->m_flags &= ~M_PKTHDR; 3713 sc->alc_cdata.alc_rxprev_tail = 3714 sc->alc_cdata.alc_rxtail; 3715 sc->alc_cdata.alc_rxtail->m_next = mp; 3716 sc->alc_cdata.alc_rxtail = mp; 3717 } 3718 3719 if (count == nsegs - 1) { 3720 /* Last desc. for this frame. */ 3721 m = sc->alc_cdata.alc_rxhead; 3722 m->m_flags |= M_PKTHDR; 3723 /* 3724 * It seems that L1C/L2C controller has no way 3725 * to tell hardware to strip CRC bytes. 3726 */ 3727 m->m_pkthdr.len = 3728 sc->alc_cdata.alc_rxlen - ETHER_CRC_LEN; 3729 if (nsegs > 1) { 3730 /* Set last mbuf size. */ 3731 mp->m_len = sc->alc_cdata.alc_rxlen - 3732 (nsegs - 1) * sc->alc_buf_size; 3733 /* Remove the CRC bytes in chained mbufs. */ 3734 if (mp->m_len <= ETHER_CRC_LEN) { 3735 sc->alc_cdata.alc_rxtail = 3736 sc->alc_cdata.alc_rxprev_tail; 3737 sc->alc_cdata.alc_rxtail->m_len -= 3738 (ETHER_CRC_LEN - mp->m_len); 3739 sc->alc_cdata.alc_rxtail->m_next = NULL; 3740 m_freem(mp); 3741 } else { 3742 mp->m_len -= ETHER_CRC_LEN; 3743 } 3744 } else 3745 m->m_len = m->m_pkthdr.len; 3746 m->m_pkthdr.rcvif = ifp; 3747 /* 3748 * Due to hardware bugs, Rx checksum offloading 3749 * was intentionally disabled. 3750 */ 3751 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0 && 3752 (status & RRD_VLAN_TAG) != 0) { 3753 vtag = RRD_VLAN(le32toh(rrd->vtag)); 3754 m->m_pkthdr.ether_vtag = ntohs(vtag); 3755 m->m_flags |= M_VLANTAG; 3756 } 3757#ifndef __NO_STRICT_ALIGNMENT 3758 m = alc_fixup_rx(ifp, m); 3759 if (m != NULL) 3760#endif 3761 { 3762 /* Pass it on. */ 3763 ALC_UNLOCK(sc); 3764 (*ifp->if_input)(ifp, m); 3765 ALC_LOCK(sc); 3766 } 3767 } 3768 } 3769 /* Reset mbuf chains. */ 3770 ALC_RXCHAIN_RESET(sc); 3771} 3772 3773static void 3774alc_tick(void *arg) 3775{ 3776 struct alc_softc *sc; 3777 struct mii_data *mii; 3778 3779 sc = (struct alc_softc *)arg; 3780 3781 ALC_LOCK_ASSERT(sc); 3782 3783 mii = device_get_softc(sc->alc_miibus); 3784 mii_tick(mii); 3785 alc_stats_update(sc); 3786 /* 3787 * alc(4) does not rely on Tx completion interrupts to reclaim 3788 * transferred buffers. Instead Tx completion interrupts are 3789 * used to hint for scheduling Tx task. So it's necessary to 3790 * release transmitted buffers by kicking Tx completion 3791 * handler. This limits the maximum reclamation delay to a hz. 3792 */ 3793 alc_txeof(sc); 3794 alc_watchdog(sc); 3795 callout_reset(&sc->alc_tick_ch, hz, alc_tick, sc); 3796} 3797 3798static void 3799alc_osc_reset(struct alc_softc *sc) 3800{ 3801 uint32_t reg; 3802 3803 reg = CSR_READ_4(sc, ALC_MISC3); 3804 reg &= ~MISC3_25M_BY_SW; 3805 reg |= MISC3_25M_NOTO_INTNL; 3806 CSR_WRITE_4(sc, ALC_MISC3, reg); 3807 3808 reg = CSR_READ_4(sc, ALC_MISC); 3809 if (AR816X_REV(sc->alc_rev) >= AR816X_REV_B0) { 3810 /* 3811 * Restore over-current protection default value. 3812 * This value could be reset by MAC reset. 3813 */ 3814 reg &= ~MISC_PSW_OCP_MASK; 3815 reg |= (MISC_PSW_OCP_DEFAULT << MISC_PSW_OCP_SHIFT); 3816 reg &= ~MISC_INTNLOSC_OPEN; 3817 CSR_WRITE_4(sc, ALC_MISC, reg); 3818 CSR_WRITE_4(sc, ALC_MISC, reg | MISC_INTNLOSC_OPEN); 3819 reg = CSR_READ_4(sc, ALC_MISC2); 3820 reg &= ~MISC2_CALB_START; 3821 CSR_WRITE_4(sc, ALC_MISC2, reg); 3822 CSR_WRITE_4(sc, ALC_MISC2, reg | MISC2_CALB_START); 3823 3824 } else { 3825 reg &= ~MISC_INTNLOSC_OPEN; 3826 /* Disable isolate for revision A devices. */ 3827 if (AR816X_REV(sc->alc_rev) <= AR816X_REV_A1) 3828 reg &= ~MISC_ISO_ENB; 3829 CSR_WRITE_4(sc, ALC_MISC, reg | MISC_INTNLOSC_OPEN); 3830 CSR_WRITE_4(sc, ALC_MISC, reg); 3831 } 3832 3833 DELAY(20); 3834} 3835 3836static void 3837alc_reset(struct alc_softc *sc) 3838{ 3839 uint32_t pmcfg, reg; 3840 int i; 3841 3842 pmcfg = 0; 3843 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 3844 /* Reset workaround. */ 3845 CSR_WRITE_4(sc, ALC_MBOX_RD0_PROD_IDX, 1); 3846 if (AR816X_REV(sc->alc_rev) <= AR816X_REV_A1 && 3847 (sc->alc_rev & 0x01) != 0) { 3848 /* Disable L0s/L1s before reset. */ 3849 pmcfg = CSR_READ_4(sc, ALC_PM_CFG); 3850 if ((pmcfg & (PM_CFG_ASPM_L0S_ENB | PM_CFG_ASPM_L1_ENB)) 3851 != 0) { 3852 pmcfg &= ~(PM_CFG_ASPM_L0S_ENB | 3853 PM_CFG_ASPM_L1_ENB); 3854 CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg); 3855 } 3856 } 3857 } 3858 reg = CSR_READ_4(sc, ALC_MASTER_CFG); 3859 reg |= MASTER_OOB_DIS_OFF | MASTER_RESET; 3860 CSR_WRITE_4(sc, ALC_MASTER_CFG, reg); 3861 3862 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 3863 for (i = ALC_RESET_TIMEOUT; i > 0; i--) { 3864 DELAY(10); 3865 if (CSR_READ_4(sc, ALC_MBOX_RD0_PROD_IDX) == 0) 3866 break; 3867 } 3868 if (i == 0) 3869 device_printf(sc->alc_dev, "MAC reset timeout!\n"); 3870 } 3871 for (i = ALC_RESET_TIMEOUT; i > 0; i--) { 3872 DELAY(10); 3873 if ((CSR_READ_4(sc, ALC_MASTER_CFG) & MASTER_RESET) == 0) 3874 break; 3875 } 3876 if (i == 0) 3877 device_printf(sc->alc_dev, "master reset timeout!\n"); 3878 3879 for (i = ALC_RESET_TIMEOUT; i > 0; i--) { 3880 reg = CSR_READ_4(sc, ALC_IDLE_STATUS); 3881 if ((reg & (IDLE_STATUS_RXMAC | IDLE_STATUS_TXMAC | 3882 IDLE_STATUS_RXQ | IDLE_STATUS_TXQ)) == 0) 3883 break; 3884 DELAY(10); 3885 } 3886 if (i == 0) 3887 device_printf(sc->alc_dev, "reset timeout(0x%08x)!\n", reg); 3888 3889 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 3890 if (AR816X_REV(sc->alc_rev) <= AR816X_REV_A1 && 3891 (sc->alc_rev & 0x01) != 0) { 3892 reg = CSR_READ_4(sc, ALC_MASTER_CFG); 3893 reg |= MASTER_CLK_SEL_DIS; 3894 CSR_WRITE_4(sc, ALC_MASTER_CFG, reg); 3895 /* Restore L0s/L1s config. */ 3896 if ((pmcfg & (PM_CFG_ASPM_L0S_ENB | PM_CFG_ASPM_L1_ENB)) 3897 != 0) 3898 CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg); 3899 } 3900 3901 alc_osc_reset(sc); 3902 reg = CSR_READ_4(sc, ALC_MISC3); 3903 reg &= ~MISC3_25M_BY_SW; 3904 reg |= MISC3_25M_NOTO_INTNL; 3905 CSR_WRITE_4(sc, ALC_MISC3, reg); 3906 reg = CSR_READ_4(sc, ALC_MISC); 3907 reg &= ~MISC_INTNLOSC_OPEN; 3908 if (AR816X_REV(sc->alc_rev) <= AR816X_REV_A1) 3909 reg &= ~MISC_ISO_ENB; 3910 CSR_WRITE_4(sc, ALC_MISC, reg); 3911 DELAY(20); 3912 } 3913 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0 || 3914 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B || 3915 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151_V2) 3916 CSR_WRITE_4(sc, ALC_SERDES_LOCK, 3917 CSR_READ_4(sc, ALC_SERDES_LOCK) | SERDES_MAC_CLK_SLOWDOWN | 3918 SERDES_PHY_CLK_SLOWDOWN); 3919} 3920 3921static void 3922alc_init(void *xsc) 3923{ 3924 struct alc_softc *sc; 3925 3926 sc = (struct alc_softc *)xsc; 3927 ALC_LOCK(sc); 3928 alc_init_locked(sc); 3929 ALC_UNLOCK(sc); 3930} 3931 3932static void 3933alc_init_locked(struct alc_softc *sc) 3934{ 3935 struct ifnet *ifp; 3936 struct mii_data *mii; 3937 uint8_t eaddr[ETHER_ADDR_LEN]; 3938 bus_addr_t paddr; 3939 uint32_t reg, rxf_hi, rxf_lo; 3940 3941 ALC_LOCK_ASSERT(sc); 3942 3943 ifp = sc->alc_ifp; 3944 mii = device_get_softc(sc->alc_miibus); 3945 3946 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 3947 return; 3948 /* 3949 * Cancel any pending I/O. 3950 */ 3951 alc_stop(sc); 3952 /* 3953 * Reset the chip to a known state. 3954 */ 3955 alc_reset(sc); 3956 3957 /* Initialize Rx descriptors. */ 3958 if (alc_init_rx_ring(sc) != 0) { 3959 device_printf(sc->alc_dev, "no memory for Rx buffers.\n"); 3960 alc_stop(sc); 3961 return; 3962 } 3963 alc_init_rr_ring(sc); 3964 alc_init_tx_ring(sc); 3965 alc_init_cmb(sc); 3966 alc_init_smb(sc); 3967 3968 /* Enable all clocks. */ 3969 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 3970 CSR_WRITE_4(sc, ALC_CLK_GATING_CFG, CLK_GATING_DMAW_ENB | 3971 CLK_GATING_DMAR_ENB | CLK_GATING_TXQ_ENB | 3972 CLK_GATING_RXQ_ENB | CLK_GATING_TXMAC_ENB | 3973 CLK_GATING_RXMAC_ENB); 3974 if (AR816X_REV(sc->alc_rev) >= AR816X_REV_B0) 3975 CSR_WRITE_4(sc, ALC_IDLE_DECISN_TIMER, 3976 IDLE_DECISN_TIMER_DEFAULT_1MS); 3977 } else 3978 CSR_WRITE_4(sc, ALC_CLK_GATING_CFG, 0); 3979 3980 /* Reprogram the station address. */ 3981 bcopy(IF_LLADDR(ifp), eaddr, ETHER_ADDR_LEN); 3982 CSR_WRITE_4(sc, ALC_PAR0, 3983 eaddr[2] << 24 | eaddr[3] << 16 | eaddr[4] << 8 | eaddr[5]); 3984 CSR_WRITE_4(sc, ALC_PAR1, eaddr[0] << 8 | eaddr[1]); 3985 /* 3986 * Clear WOL status and disable all WOL feature as WOL 3987 * would interfere Rx operation under normal environments. 3988 */ 3989 CSR_READ_4(sc, ALC_WOL_CFG); 3990 CSR_WRITE_4(sc, ALC_WOL_CFG, 0); 3991 /* Set Tx descriptor base addresses. */ 3992 paddr = sc->alc_rdata.alc_tx_ring_paddr; 3993 CSR_WRITE_4(sc, ALC_TX_BASE_ADDR_HI, ALC_ADDR_HI(paddr)); 3994 CSR_WRITE_4(sc, ALC_TDL_HEAD_ADDR_LO, ALC_ADDR_LO(paddr)); 3995 /* We don't use high priority ring. */ 3996 CSR_WRITE_4(sc, ALC_TDH_HEAD_ADDR_LO, 0); 3997 /* Set Tx descriptor counter. */ 3998 CSR_WRITE_4(sc, ALC_TD_RING_CNT, 3999 (ALC_TX_RING_CNT << TD_RING_CNT_SHIFT) & TD_RING_CNT_MASK); 4000 /* Set Rx descriptor base addresses. */ 4001 paddr = sc->alc_rdata.alc_rx_ring_paddr; 4002 CSR_WRITE_4(sc, ALC_RX_BASE_ADDR_HI, ALC_ADDR_HI(paddr)); 4003 CSR_WRITE_4(sc, ALC_RD0_HEAD_ADDR_LO, ALC_ADDR_LO(paddr)); 4004 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 4005 /* We use one Rx ring. */ 4006 CSR_WRITE_4(sc, ALC_RD1_HEAD_ADDR_LO, 0); 4007 CSR_WRITE_4(sc, ALC_RD2_HEAD_ADDR_LO, 0); 4008 CSR_WRITE_4(sc, ALC_RD3_HEAD_ADDR_LO, 0); 4009 } 4010 /* Set Rx descriptor counter. */ 4011 CSR_WRITE_4(sc, ALC_RD_RING_CNT, 4012 (ALC_RX_RING_CNT << RD_RING_CNT_SHIFT) & RD_RING_CNT_MASK); 4013 4014 /* 4015 * Let hardware split jumbo frames into alc_max_buf_sized chunks. 4016 * if it do not fit the buffer size. Rx return descriptor holds 4017 * a counter that indicates how many fragments were made by the 4018 * hardware. The buffer size should be multiple of 8 bytes. 4019 * Since hardware has limit on the size of buffer size, always 4020 * use the maximum value. 4021 * For strict-alignment architectures make sure to reduce buffer 4022 * size by 8 bytes to make room for alignment fixup. 4023 */ 4024#ifndef __NO_STRICT_ALIGNMENT 4025 sc->alc_buf_size = RX_BUF_SIZE_MAX - sizeof(uint64_t); 4026#else 4027 sc->alc_buf_size = RX_BUF_SIZE_MAX; 4028#endif 4029 CSR_WRITE_4(sc, ALC_RX_BUF_SIZE, sc->alc_buf_size); 4030 4031 paddr = sc->alc_rdata.alc_rr_ring_paddr; 4032 /* Set Rx return descriptor base addresses. */ 4033 CSR_WRITE_4(sc, ALC_RRD0_HEAD_ADDR_LO, ALC_ADDR_LO(paddr)); 4034 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 4035 /* We use one Rx return ring. */ 4036 CSR_WRITE_4(sc, ALC_RRD1_HEAD_ADDR_LO, 0); 4037 CSR_WRITE_4(sc, ALC_RRD2_HEAD_ADDR_LO, 0); 4038 CSR_WRITE_4(sc, ALC_RRD3_HEAD_ADDR_LO, 0); 4039 } 4040 /* Set Rx return descriptor counter. */ 4041 CSR_WRITE_4(sc, ALC_RRD_RING_CNT, 4042 (ALC_RR_RING_CNT << RRD_RING_CNT_SHIFT) & RRD_RING_CNT_MASK); 4043 paddr = sc->alc_rdata.alc_cmb_paddr; 4044 CSR_WRITE_4(sc, ALC_CMB_BASE_ADDR_LO, ALC_ADDR_LO(paddr)); 4045 paddr = sc->alc_rdata.alc_smb_paddr; 4046 CSR_WRITE_4(sc, ALC_SMB_BASE_ADDR_HI, ALC_ADDR_HI(paddr)); 4047 CSR_WRITE_4(sc, ALC_SMB_BASE_ADDR_LO, ALC_ADDR_LO(paddr)); 4048 4049 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B) { 4050 /* Reconfigure SRAM - Vendor magic. */ 4051 CSR_WRITE_4(sc, ALC_SRAM_RX_FIFO_LEN, 0x000002A0); 4052 CSR_WRITE_4(sc, ALC_SRAM_TX_FIFO_LEN, 0x00000100); 4053 CSR_WRITE_4(sc, ALC_SRAM_RX_FIFO_ADDR, 0x029F0000); 4054 CSR_WRITE_4(sc, ALC_SRAM_RD0_ADDR, 0x02BF02A0); 4055 CSR_WRITE_4(sc, ALC_SRAM_TX_FIFO_ADDR, 0x03BF02C0); 4056 CSR_WRITE_4(sc, ALC_SRAM_TD_ADDR, 0x03DF03C0); 4057 CSR_WRITE_4(sc, ALC_TXF_WATER_MARK, 0x00000000); 4058 CSR_WRITE_4(sc, ALC_RD_DMA_CFG, 0x00000000); 4059 } 4060 4061 /* Tell hardware that we're ready to load DMA blocks. */ 4062 CSR_WRITE_4(sc, ALC_DMA_BLOCK, DMA_BLOCK_LOAD); 4063 4064 /* Configure interrupt moderation timer. */ 4065 reg = ALC_USECS(sc->alc_int_rx_mod) << IM_TIMER_RX_SHIFT; 4066 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) 4067 reg |= ALC_USECS(sc->alc_int_tx_mod) << IM_TIMER_TX_SHIFT; 4068 CSR_WRITE_4(sc, ALC_IM_TIMER, reg); 4069 /* 4070 * We don't want to automatic interrupt clear as task queue 4071 * for the interrupt should know interrupt status. 4072 */ 4073 reg = CSR_READ_4(sc, ALC_MASTER_CFG); 4074 reg &= ~(MASTER_IM_RX_TIMER_ENB | MASTER_IM_TX_TIMER_ENB); 4075 reg |= MASTER_SA_TIMER_ENB; 4076 if (ALC_USECS(sc->alc_int_rx_mod) != 0) 4077 reg |= MASTER_IM_RX_TIMER_ENB; 4078 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0 && 4079 ALC_USECS(sc->alc_int_tx_mod) != 0) 4080 reg |= MASTER_IM_TX_TIMER_ENB; 4081 CSR_WRITE_4(sc, ALC_MASTER_CFG, reg); 4082 /* 4083 * Disable interrupt re-trigger timer. We don't want automatic 4084 * re-triggering of un-ACKed interrupts. 4085 */ 4086 CSR_WRITE_4(sc, ALC_INTR_RETRIG_TIMER, ALC_USECS(0)); 4087 /* Configure CMB. */ 4088 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 4089 CSR_WRITE_4(sc, ALC_CMB_TD_THRESH, ALC_TX_RING_CNT / 3); 4090 CSR_WRITE_4(sc, ALC_CMB_TX_TIMER, 4091 ALC_USECS(sc->alc_int_tx_mod)); 4092 } else { 4093 if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0) { 4094 CSR_WRITE_4(sc, ALC_CMB_TD_THRESH, 4); 4095 CSR_WRITE_4(sc, ALC_CMB_TX_TIMER, ALC_USECS(5000)); 4096 } else 4097 CSR_WRITE_4(sc, ALC_CMB_TX_TIMER, ALC_USECS(0)); 4098 } 4099 /* 4100 * Hardware can be configured to issue SMB interrupt based 4101 * on programmed interval. Since there is a callout that is 4102 * invoked for every hz in driver we use that instead of 4103 * relying on periodic SMB interrupt. 4104 */ 4105 CSR_WRITE_4(sc, ALC_SMB_STAT_TIMER, ALC_USECS(0)); 4106 /* Clear MAC statistics. */ 4107 alc_stats_clear(sc); 4108 4109 /* 4110 * Always use maximum frame size that controller can support. 4111 * Otherwise received frames that has larger frame length 4112 * than alc(4) MTU would be silently dropped in hardware. This 4113 * would make path-MTU discovery hard as sender wouldn't get 4114 * any responses from receiver. alc(4) supports 4115 * multi-fragmented frames on Rx path so it has no issue on 4116 * assembling fragmented frames. Using maximum frame size also 4117 * removes the need to reinitialize hardware when interface 4118 * MTU configuration was changed. 4119 * 4120 * Be conservative in what you do, be liberal in what you 4121 * accept from others - RFC 793. 4122 */ 4123 CSR_WRITE_4(sc, ALC_FRAME_SIZE, sc->alc_ident->max_framelen); 4124 4125 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 4126 /* Disable header split(?) */ 4127 CSR_WRITE_4(sc, ALC_HDS_CFG, 0); 4128 4129 /* Configure IPG/IFG parameters. */ 4130 CSR_WRITE_4(sc, ALC_IPG_IFG_CFG, 4131 ((IPG_IFG_IPGT_DEFAULT << IPG_IFG_IPGT_SHIFT) & 4132 IPG_IFG_IPGT_MASK) | 4133 ((IPG_IFG_MIFG_DEFAULT << IPG_IFG_MIFG_SHIFT) & 4134 IPG_IFG_MIFG_MASK) | 4135 ((IPG_IFG_IPG1_DEFAULT << IPG_IFG_IPG1_SHIFT) & 4136 IPG_IFG_IPG1_MASK) | 4137 ((IPG_IFG_IPG2_DEFAULT << IPG_IFG_IPG2_SHIFT) & 4138 IPG_IFG_IPG2_MASK)); 4139 /* Set parameters for half-duplex media. */ 4140 CSR_WRITE_4(sc, ALC_HDPX_CFG, 4141 ((HDPX_CFG_LCOL_DEFAULT << HDPX_CFG_LCOL_SHIFT) & 4142 HDPX_CFG_LCOL_MASK) | 4143 ((HDPX_CFG_RETRY_DEFAULT << HDPX_CFG_RETRY_SHIFT) & 4144 HDPX_CFG_RETRY_MASK) | HDPX_CFG_EXC_DEF_EN | 4145 ((HDPX_CFG_ABEBT_DEFAULT << HDPX_CFG_ABEBT_SHIFT) & 4146 HDPX_CFG_ABEBT_MASK) | 4147 ((HDPX_CFG_JAMIPG_DEFAULT << HDPX_CFG_JAMIPG_SHIFT) & 4148 HDPX_CFG_JAMIPG_MASK)); 4149 } 4150 4151 /* 4152 * Set TSO/checksum offload threshold. For frames that is 4153 * larger than this threshold, hardware wouldn't do 4154 * TSO/checksum offloading. 4155 */ 4156 reg = (sc->alc_ident->max_framelen >> TSO_OFFLOAD_THRESH_UNIT_SHIFT) & 4157 TSO_OFFLOAD_THRESH_MASK; 4158 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 4159 reg |= TSO_OFFLOAD_ERRLGPKT_DROP_ENB; 4160 CSR_WRITE_4(sc, ALC_TSO_OFFLOAD_THRESH, reg); 4161 /* Configure TxQ. */ 4162 reg = (alc_dma_burst[sc->alc_dma_rd_burst] << 4163 TXQ_CFG_TX_FIFO_BURST_SHIFT) & TXQ_CFG_TX_FIFO_BURST_MASK; 4164 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B || 4165 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B2) 4166 reg >>= 1; 4167 reg |= (TXQ_CFG_TD_BURST_DEFAULT << TXQ_CFG_TD_BURST_SHIFT) & 4168 TXQ_CFG_TD_BURST_MASK; 4169 reg |= TXQ_CFG_IP_OPTION_ENB | TXQ_CFG_8023_ENB; 4170 CSR_WRITE_4(sc, ALC_TXQ_CFG, reg | TXQ_CFG_ENHANCED_MODE); 4171 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 4172 reg = (TXQ_CFG_TD_BURST_DEFAULT << HQTD_CFG_Q1_BURST_SHIFT | 4173 TXQ_CFG_TD_BURST_DEFAULT << HQTD_CFG_Q2_BURST_SHIFT | 4174 TXQ_CFG_TD_BURST_DEFAULT << HQTD_CFG_Q3_BURST_SHIFT | 4175 HQTD_CFG_BURST_ENB); 4176 CSR_WRITE_4(sc, ALC_HQTD_CFG, reg); 4177 reg = WRR_PRI_RESTRICT_NONE; 4178 reg |= (WRR_PRI_DEFAULT << WRR_PRI0_SHIFT | 4179 WRR_PRI_DEFAULT << WRR_PRI1_SHIFT | 4180 WRR_PRI_DEFAULT << WRR_PRI2_SHIFT | 4181 WRR_PRI_DEFAULT << WRR_PRI3_SHIFT); 4182 CSR_WRITE_4(sc, ALC_WRR, reg); 4183 } else { 4184 /* Configure Rx free descriptor pre-fetching. */ 4185 CSR_WRITE_4(sc, ALC_RX_RD_FREE_THRESH, 4186 ((RX_RD_FREE_THRESH_HI_DEFAULT << 4187 RX_RD_FREE_THRESH_HI_SHIFT) & RX_RD_FREE_THRESH_HI_MASK) | 4188 ((RX_RD_FREE_THRESH_LO_DEFAULT << 4189 RX_RD_FREE_THRESH_LO_SHIFT) & RX_RD_FREE_THRESH_LO_MASK)); 4190 } 4191 4192 /* 4193 * Configure flow control parameters. 4194 * XON : 80% of Rx FIFO 4195 * XOFF : 30% of Rx FIFO 4196 */ 4197 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 4198 reg = CSR_READ_4(sc, ALC_SRAM_RX_FIFO_LEN); 4199 reg &= SRAM_RX_FIFO_LEN_MASK; 4200 reg *= 8; 4201 if (reg > 8 * 1024) 4202 reg -= RX_FIFO_PAUSE_816X_RSVD; 4203 else 4204 reg -= RX_BUF_SIZE_MAX; 4205 reg /= 8; 4206 CSR_WRITE_4(sc, ALC_RX_FIFO_PAUSE_THRESH, 4207 ((reg << RX_FIFO_PAUSE_THRESH_LO_SHIFT) & 4208 RX_FIFO_PAUSE_THRESH_LO_MASK) | 4209 (((RX_FIFO_PAUSE_816X_RSVD / 8) << 4210 RX_FIFO_PAUSE_THRESH_HI_SHIFT) & 4211 RX_FIFO_PAUSE_THRESH_HI_MASK)); 4212 } else if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8131 || 4213 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8132) { 4214 reg = CSR_READ_4(sc, ALC_SRAM_RX_FIFO_LEN); 4215 rxf_hi = (reg * 8) / 10; 4216 rxf_lo = (reg * 3) / 10; 4217 CSR_WRITE_4(sc, ALC_RX_FIFO_PAUSE_THRESH, 4218 ((rxf_lo << RX_FIFO_PAUSE_THRESH_LO_SHIFT) & 4219 RX_FIFO_PAUSE_THRESH_LO_MASK) | 4220 ((rxf_hi << RX_FIFO_PAUSE_THRESH_HI_SHIFT) & 4221 RX_FIFO_PAUSE_THRESH_HI_MASK)); 4222 } 4223 4224 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 4225 /* Disable RSS until I understand L1C/L2C's RSS logic. */ 4226 CSR_WRITE_4(sc, ALC_RSS_IDT_TABLE0, 0); 4227 CSR_WRITE_4(sc, ALC_RSS_CPU, 0); 4228 } 4229 4230 /* Configure RxQ. */ 4231 reg = (RXQ_CFG_RD_BURST_DEFAULT << RXQ_CFG_RD_BURST_SHIFT) & 4232 RXQ_CFG_RD_BURST_MASK; 4233 reg |= RXQ_CFG_RSS_MODE_DIS; 4234 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 4235 reg |= (RXQ_CFG_816X_IDT_TBL_SIZE_DEFAULT << 4236 RXQ_CFG_816X_IDT_TBL_SIZE_SHIFT) & 4237 RXQ_CFG_816X_IDT_TBL_SIZE_MASK; 4238 if ((sc->alc_flags & ALC_FLAG_FASTETHER) == 0) 4239 reg |= RXQ_CFG_ASPM_THROUGHPUT_LIMIT_100M; 4240 } else { 4241 if ((sc->alc_flags & ALC_FLAG_FASTETHER) == 0 && 4242 sc->alc_ident->deviceid != DEVICEID_ATHEROS_AR8151_V2) 4243 reg |= RXQ_CFG_ASPM_THROUGHPUT_LIMIT_100M; 4244 } 4245 CSR_WRITE_4(sc, ALC_RXQ_CFG, reg); 4246 4247 /* Configure DMA parameters. */ 4248 reg = DMA_CFG_OUT_ORDER | DMA_CFG_RD_REQ_PRI; 4249 reg |= sc->alc_rcb; 4250 if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0) 4251 reg |= DMA_CFG_CMB_ENB; 4252 if ((sc->alc_flags & ALC_FLAG_SMB_BUG) == 0) 4253 reg |= DMA_CFG_SMB_ENB; 4254 else 4255 reg |= DMA_CFG_SMB_DIS; 4256 reg |= (sc->alc_dma_rd_burst & DMA_CFG_RD_BURST_MASK) << 4257 DMA_CFG_RD_BURST_SHIFT; 4258 reg |= (sc->alc_dma_wr_burst & DMA_CFG_WR_BURST_MASK) << 4259 DMA_CFG_WR_BURST_SHIFT; 4260 reg |= (DMA_CFG_RD_DELAY_CNT_DEFAULT << DMA_CFG_RD_DELAY_CNT_SHIFT) & 4261 DMA_CFG_RD_DELAY_CNT_MASK; 4262 reg |= (DMA_CFG_WR_DELAY_CNT_DEFAULT << DMA_CFG_WR_DELAY_CNT_SHIFT) & 4263 DMA_CFG_WR_DELAY_CNT_MASK; 4264 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 4265 switch (AR816X_REV(sc->alc_rev)) { 4266 case AR816X_REV_A0: 4267 case AR816X_REV_A1: 4268 reg |= DMA_CFG_RD_CHNL_SEL_2; 4269 break; 4270 case AR816X_REV_B0: 4271 /* FALLTHROUGH */ 4272 default: 4273 reg |= DMA_CFG_RD_CHNL_SEL_4; 4274 break; 4275 } 4276 } 4277 CSR_WRITE_4(sc, ALC_DMA_CFG, reg); 4278 4279 /* 4280 * Configure Tx/Rx MACs. 4281 * - Auto-padding for short frames. 4282 * - Enable CRC generation. 4283 * Actual reconfiguration of MAC for resolved speed/duplex 4284 * is followed after detection of link establishment. 4285 * AR813x/AR815x always does checksum computation regardless 4286 * of MAC_CFG_RXCSUM_ENB bit. Also the controller is known to 4287 * have bug in protocol field in Rx return structure so 4288 * these controllers can't handle fragmented frames. Disable 4289 * Rx checksum offloading until there is a newer controller 4290 * that has sane implementation. 4291 */ 4292 reg = MAC_CFG_TX_CRC_ENB | MAC_CFG_TX_AUTO_PAD | MAC_CFG_FULL_DUPLEX | 4293 ((MAC_CFG_PREAMBLE_DEFAULT << MAC_CFG_PREAMBLE_SHIFT) & 4294 MAC_CFG_PREAMBLE_MASK); 4295 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0 || 4296 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151 || 4297 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151_V2 || 4298 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B2) 4299 reg |= MAC_CFG_HASH_ALG_CRC32 | MAC_CFG_SPEED_MODE_SW; 4300 if ((sc->alc_flags & ALC_FLAG_FASTETHER) != 0) 4301 reg |= MAC_CFG_SPEED_10_100; 4302 else 4303 reg |= MAC_CFG_SPEED_1000; 4304 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 4305 4306 /* Set up the receive filter. */ 4307 alc_rxfilter(sc); 4308 alc_rxvlan(sc); 4309 4310 /* Acknowledge all pending interrupts and clear it. */ 4311 CSR_WRITE_4(sc, ALC_INTR_MASK, ALC_INTRS); 4312 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0xFFFFFFFF); 4313 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0); 4314 4315 ifp->if_drv_flags |= IFF_DRV_RUNNING; 4316 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 4317 4318 sc->alc_flags &= ~ALC_FLAG_LINK; 4319 /* Switch to the current media. */ 4320 alc_mediachange_locked(sc); 4321 4322 callout_reset(&sc->alc_tick_ch, hz, alc_tick, sc); 4323} 4324 4325static void 4326alc_stop(struct alc_softc *sc) 4327{ 4328 struct ifnet *ifp; 4329 struct alc_txdesc *txd; 4330 struct alc_rxdesc *rxd; 4331 uint32_t reg; 4332 int i; 4333 4334 ALC_LOCK_ASSERT(sc); 4335 /* 4336 * Mark the interface down and cancel the watchdog timer. 4337 */ 4338 ifp = sc->alc_ifp; 4339 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 4340 sc->alc_flags &= ~ALC_FLAG_LINK; 4341 callout_stop(&sc->alc_tick_ch); 4342 sc->alc_watchdog_timer = 0; 4343 alc_stats_update(sc); 4344 /* Disable interrupts. */ 4345 CSR_WRITE_4(sc, ALC_INTR_MASK, 0); 4346 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0xFFFFFFFF); 4347 /* Disable DMA. */ 4348 reg = CSR_READ_4(sc, ALC_DMA_CFG); 4349 reg &= ~(DMA_CFG_CMB_ENB | DMA_CFG_SMB_ENB); 4350 reg |= DMA_CFG_SMB_DIS; 4351 CSR_WRITE_4(sc, ALC_DMA_CFG, reg); 4352 DELAY(1000); 4353 /* Stop Rx/Tx MACs. */ 4354 alc_stop_mac(sc); 4355 /* Disable interrupts which might be touched in taskq handler. */ 4356 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0xFFFFFFFF); 4357 /* Disable L0s/L1s */ 4358 alc_aspm(sc, 0, IFM_UNKNOWN); 4359 /* Reclaim Rx buffers that have been processed. */ 4360 if (sc->alc_cdata.alc_rxhead != NULL) 4361 m_freem(sc->alc_cdata.alc_rxhead); 4362 ALC_RXCHAIN_RESET(sc); 4363 /* 4364 * Free Tx/Rx mbufs still in the queues. 4365 */ 4366 for (i = 0; i < ALC_RX_RING_CNT; i++) { 4367 rxd = &sc->alc_cdata.alc_rxdesc[i]; 4368 if (rxd->rx_m != NULL) { 4369 bus_dmamap_sync(sc->alc_cdata.alc_rx_tag, 4370 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 4371 bus_dmamap_unload(sc->alc_cdata.alc_rx_tag, 4372 rxd->rx_dmamap); 4373 m_freem(rxd->rx_m); 4374 rxd->rx_m = NULL; 4375 } 4376 } 4377 for (i = 0; i < ALC_TX_RING_CNT; i++) { 4378 txd = &sc->alc_cdata.alc_txdesc[i]; 4379 if (txd->tx_m != NULL) { 4380 bus_dmamap_sync(sc->alc_cdata.alc_tx_tag, 4381 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 4382 bus_dmamap_unload(sc->alc_cdata.alc_tx_tag, 4383 txd->tx_dmamap); 4384 m_freem(txd->tx_m); 4385 txd->tx_m = NULL; 4386 } 4387 } 4388} 4389 4390static void 4391alc_stop_mac(struct alc_softc *sc) 4392{ 4393 uint32_t reg; 4394 int i; 4395 4396 alc_stop_queue(sc); 4397 /* Disable Rx/Tx MAC. */ 4398 reg = CSR_READ_4(sc, ALC_MAC_CFG); 4399 if ((reg & (MAC_CFG_TX_ENB | MAC_CFG_RX_ENB)) != 0) { 4400 reg &= ~(MAC_CFG_TX_ENB | MAC_CFG_RX_ENB); 4401 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 4402 } 4403 for (i = ALC_TIMEOUT; i > 0; i--) { 4404 reg = CSR_READ_4(sc, ALC_IDLE_STATUS); 4405 if ((reg & (IDLE_STATUS_RXMAC | IDLE_STATUS_TXMAC)) == 0) 4406 break; 4407 DELAY(10); 4408 } 4409 if (i == 0) 4410 device_printf(sc->alc_dev, 4411 "could not disable Rx/Tx MAC(0x%08x)!\n", reg); 4412} 4413 4414static void 4415alc_start_queue(struct alc_softc *sc) 4416{ 4417 uint32_t qcfg[] = { 4418 0, 4419 RXQ_CFG_QUEUE0_ENB, 4420 RXQ_CFG_QUEUE0_ENB | RXQ_CFG_QUEUE1_ENB, 4421 RXQ_CFG_QUEUE0_ENB | RXQ_CFG_QUEUE1_ENB | RXQ_CFG_QUEUE2_ENB, 4422 RXQ_CFG_ENB 4423 }; 4424 uint32_t cfg; 4425 4426 ALC_LOCK_ASSERT(sc); 4427 4428 /* Enable RxQ. */ 4429 cfg = CSR_READ_4(sc, ALC_RXQ_CFG); 4430 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 4431 cfg &= ~RXQ_CFG_ENB; 4432 cfg |= qcfg[1]; 4433 } else 4434 cfg |= RXQ_CFG_QUEUE0_ENB; 4435 CSR_WRITE_4(sc, ALC_RXQ_CFG, cfg); 4436 /* Enable TxQ. */ 4437 cfg = CSR_READ_4(sc, ALC_TXQ_CFG); 4438 cfg |= TXQ_CFG_ENB; 4439 CSR_WRITE_4(sc, ALC_TXQ_CFG, cfg); 4440} 4441 4442static void 4443alc_stop_queue(struct alc_softc *sc) 4444{ 4445 uint32_t reg; 4446 int i; 4447 4448 /* Disable RxQ. */ 4449 reg = CSR_READ_4(sc, ALC_RXQ_CFG); 4450 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 4451 if ((reg & RXQ_CFG_ENB) != 0) { 4452 reg &= ~RXQ_CFG_ENB; 4453 CSR_WRITE_4(sc, ALC_RXQ_CFG, reg); 4454 } 4455 } else { 4456 if ((reg & RXQ_CFG_QUEUE0_ENB) != 0) { 4457 reg &= ~RXQ_CFG_QUEUE0_ENB; 4458 CSR_WRITE_4(sc, ALC_RXQ_CFG, reg); 4459 } 4460 } 4461 /* Disable TxQ. */ 4462 reg = CSR_READ_4(sc, ALC_TXQ_CFG); 4463 if ((reg & TXQ_CFG_ENB) != 0) { 4464 reg &= ~TXQ_CFG_ENB; 4465 CSR_WRITE_4(sc, ALC_TXQ_CFG, reg); 4466 } 4467 DELAY(40); 4468 for (i = ALC_TIMEOUT; i > 0; i--) { 4469 reg = CSR_READ_4(sc, ALC_IDLE_STATUS); 4470 if ((reg & (IDLE_STATUS_RXQ | IDLE_STATUS_TXQ)) == 0) 4471 break; 4472 DELAY(10); 4473 } 4474 if (i == 0) 4475 device_printf(sc->alc_dev, 4476 "could not disable RxQ/TxQ (0x%08x)!\n", reg); 4477} 4478 4479static void 4480alc_init_tx_ring(struct alc_softc *sc) 4481{ 4482 struct alc_ring_data *rd; 4483 struct alc_txdesc *txd; 4484 int i; 4485 4486 ALC_LOCK_ASSERT(sc); 4487 4488 sc->alc_cdata.alc_tx_prod = 0; 4489 sc->alc_cdata.alc_tx_cons = 0; 4490 sc->alc_cdata.alc_tx_cnt = 0; 4491 4492 rd = &sc->alc_rdata; 4493 bzero(rd->alc_tx_ring, ALC_TX_RING_SZ); 4494 for (i = 0; i < ALC_TX_RING_CNT; i++) { 4495 txd = &sc->alc_cdata.alc_txdesc[i]; 4496 txd->tx_m = NULL; 4497 } 4498 4499 bus_dmamap_sync(sc->alc_cdata.alc_tx_ring_tag, 4500 sc->alc_cdata.alc_tx_ring_map, BUS_DMASYNC_PREWRITE); 4501} 4502 4503static int 4504alc_init_rx_ring(struct alc_softc *sc) 4505{ 4506 struct alc_ring_data *rd; 4507 struct alc_rxdesc *rxd; 4508 int i; 4509 4510 ALC_LOCK_ASSERT(sc); 4511 4512 sc->alc_cdata.alc_rx_cons = ALC_RX_RING_CNT - 1; 4513 sc->alc_morework = 0; 4514 rd = &sc->alc_rdata; 4515 bzero(rd->alc_rx_ring, ALC_RX_RING_SZ); 4516 for (i = 0; i < ALC_RX_RING_CNT; i++) { 4517 rxd = &sc->alc_cdata.alc_rxdesc[i]; 4518 rxd->rx_m = NULL; 4519 rxd->rx_desc = &rd->alc_rx_ring[i]; 4520 if (alc_newbuf(sc, rxd) != 0) 4521 return (ENOBUFS); 4522 } 4523 4524 /* 4525 * Since controller does not update Rx descriptors, driver 4526 * does have to read Rx descriptors back so BUS_DMASYNC_PREWRITE 4527 * is enough to ensure coherence. 4528 */ 4529 bus_dmamap_sync(sc->alc_cdata.alc_rx_ring_tag, 4530 sc->alc_cdata.alc_rx_ring_map, BUS_DMASYNC_PREWRITE); 4531 /* Let controller know availability of new Rx buffers. */ 4532 CSR_WRITE_4(sc, ALC_MBOX_RD0_PROD_IDX, sc->alc_cdata.alc_rx_cons); 4533 4534 return (0); 4535} 4536 4537static void 4538alc_init_rr_ring(struct alc_softc *sc) 4539{ 4540 struct alc_ring_data *rd; 4541 4542 ALC_LOCK_ASSERT(sc); 4543 4544 sc->alc_cdata.alc_rr_cons = 0; 4545 ALC_RXCHAIN_RESET(sc); 4546 4547 rd = &sc->alc_rdata; 4548 bzero(rd->alc_rr_ring, ALC_RR_RING_SZ); 4549 bus_dmamap_sync(sc->alc_cdata.alc_rr_ring_tag, 4550 sc->alc_cdata.alc_rr_ring_map, 4551 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4552} 4553 4554static void 4555alc_init_cmb(struct alc_softc *sc) 4556{ 4557 struct alc_ring_data *rd; 4558 4559 ALC_LOCK_ASSERT(sc); 4560 4561 rd = &sc->alc_rdata; 4562 bzero(rd->alc_cmb, ALC_CMB_SZ); 4563 bus_dmamap_sync(sc->alc_cdata.alc_cmb_tag, sc->alc_cdata.alc_cmb_map, 4564 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4565} 4566 4567static void 4568alc_init_smb(struct alc_softc *sc) 4569{ 4570 struct alc_ring_data *rd; 4571 4572 ALC_LOCK_ASSERT(sc); 4573 4574 rd = &sc->alc_rdata; 4575 bzero(rd->alc_smb, ALC_SMB_SZ); 4576 bus_dmamap_sync(sc->alc_cdata.alc_smb_tag, sc->alc_cdata.alc_smb_map, 4577 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4578} 4579 4580static void 4581alc_rxvlan(struct alc_softc *sc) 4582{ 4583 struct ifnet *ifp; 4584 uint32_t reg; 4585 4586 ALC_LOCK_ASSERT(sc); 4587 4588 ifp = sc->alc_ifp; 4589 reg = CSR_READ_4(sc, ALC_MAC_CFG); 4590 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) 4591 reg |= MAC_CFG_VLAN_TAG_STRIP; 4592 else 4593 reg &= ~MAC_CFG_VLAN_TAG_STRIP; 4594 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 4595} 4596 4597static u_int 4598alc_hash_maddr(void *arg, struct sockaddr_dl *sdl, u_int cnt) 4599{ 4600 uint32_t *mchash = arg; 4601 uint32_t crc; 4602 4603 crc = ether_crc32_be(LLADDR(sdl), ETHER_ADDR_LEN); 4604 mchash[crc >> 31] |= 1 << ((crc >> 26) & 0x1f); 4605 4606 return (1); 4607} 4608 4609static void 4610alc_rxfilter(struct alc_softc *sc) 4611{ 4612 struct ifnet *ifp; 4613 uint32_t mchash[2]; 4614 uint32_t rxcfg; 4615 4616 ALC_LOCK_ASSERT(sc); 4617 4618 ifp = sc->alc_ifp; 4619 4620 bzero(mchash, sizeof(mchash)); 4621 rxcfg = CSR_READ_4(sc, ALC_MAC_CFG); 4622 rxcfg &= ~(MAC_CFG_ALLMULTI | MAC_CFG_BCAST | MAC_CFG_PROMISC); 4623 if ((ifp->if_flags & IFF_BROADCAST) != 0) 4624 rxcfg |= MAC_CFG_BCAST; 4625 if ((ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) != 0) { 4626 if ((ifp->if_flags & IFF_PROMISC) != 0) 4627 rxcfg |= MAC_CFG_PROMISC; 4628 if ((ifp->if_flags & IFF_ALLMULTI) != 0) 4629 rxcfg |= MAC_CFG_ALLMULTI; 4630 mchash[0] = 0xFFFFFFFF; 4631 mchash[1] = 0xFFFFFFFF; 4632 goto chipit; 4633 } 4634 4635 if_foreach_llmaddr(ifp, alc_hash_maddr, mchash); 4636 4637chipit: 4638 CSR_WRITE_4(sc, ALC_MAR0, mchash[0]); 4639 CSR_WRITE_4(sc, ALC_MAR1, mchash[1]); 4640 CSR_WRITE_4(sc, ALC_MAC_CFG, rxcfg); 4641} 4642 4643static int 4644sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high) 4645{ 4646 int error, value; 4647 4648 if (arg1 == NULL) 4649 return (EINVAL); 4650 value = *(int *)arg1; 4651 error = sysctl_handle_int(oidp, &value, 0, req); 4652 if (error || req->newptr == NULL) 4653 return (error); 4654 if (value < low || value > high) 4655 return (EINVAL); 4656 *(int *)arg1 = value; 4657 4658 return (0); 4659} 4660 4661static int 4662sysctl_hw_alc_proc_limit(SYSCTL_HANDLER_ARGS) 4663{ 4664 return (sysctl_int_range(oidp, arg1, arg2, req, 4665 ALC_PROC_MIN, ALC_PROC_MAX)); 4666} 4667 4668static int 4669sysctl_hw_alc_int_mod(SYSCTL_HANDLER_ARGS) 4670{ 4671 4672 return (sysctl_int_range(oidp, arg1, arg2, req, 4673 ALC_IM_TIMER_MIN, ALC_IM_TIMER_MAX)); 4674} 4675 4676#ifdef DEBUGNET 4677static void 4678alc_debugnet_init(struct ifnet *ifp, int *nrxr, int *ncl, int *clsize) 4679{ 4680 struct alc_softc *sc; 4681 4682 sc = if_getsoftc(ifp); 4683 KASSERT(sc->alc_buf_size <= MCLBYTES, ("incorrect cluster size")); 4684 4685 *nrxr = ALC_RX_RING_CNT; 4686 *ncl = DEBUGNET_MAX_IN_FLIGHT; 4687 *clsize = MCLBYTES; 4688} 4689 4690static void 4691alc_debugnet_event(struct ifnet *ifp __unused, enum debugnet_ev event __unused) 4692{ 4693} 4694 4695static int 4696alc_debugnet_transmit(struct ifnet *ifp, struct mbuf *m) 4697{ 4698 struct alc_softc *sc; 4699 int error; 4700 4701 sc = if_getsoftc(ifp); 4702 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 4703 IFF_DRV_RUNNING) 4704 return (EBUSY); 4705 4706 error = alc_encap(sc, &m); 4707 if (error == 0) 4708 alc_start_tx(sc); 4709 return (error); 4710} 4711 4712static int 4713alc_debugnet_poll(struct ifnet *ifp, int count) 4714{ 4715 struct alc_softc *sc; 4716 4717 sc = if_getsoftc(ifp); 4718 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 4719 IFF_DRV_RUNNING) 4720 return (EBUSY); 4721 4722 alc_txeof(sc); 4723 return (alc_rxintr(sc, count)); 4724} 4725#endif /* DEBUGNET */ 4726