Searched refs:mpcc_inst (Results 1 - 25 of 29) sorted by relevance

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/linux-master/drivers/gpu/drm/amd/display/dc/inc/hw/
H A Dpg_cntl.h45 void (*mpcc_pg_control)(struct pg_cntl *pg_cntl, unsigned int mpcc_inst, bool power_on);
H A Dmpc.h287 int mpcc_inst,
/linux-master/drivers/gpu/drm/amd/display/dc/dcn201/
H A Ddcn201_mpc.c62 static void mpc201_init_mpcc(struct mpcc *mpcc, int mpcc_inst) argument
64 mpcc->mpcc_id = mpcc_inst;
/linux-master/drivers/gpu/drm/amd/display/dc/dcn20/
H A Ddcn20_mpc.c511 static void mpc2_init_mpcc(struct mpcc *mpcc, int mpcc_inst) argument
513 mpcc->mpcc_id = mpcc_inst;
547 int mpcc_inst,
552 REG_GET(MPCC_OPP_ID[mpcc_inst], MPCC_OPP_ID, &s->opp_id);
553 REG_GET(MPCC_TOP_SEL[mpcc_inst], MPCC_TOP_SEL, &s->dpp_id);
554 REG_GET(MPCC_BOT_SEL[mpcc_inst], MPCC_BOT_SEL, &s->bot_mpcc_id);
555 REG_GET_4(MPCC_CONTROL[mpcc_inst], MPCC_MODE, &s->mode,
559 REG_GET_2(MPCC_STATUS[mpcc_inst], MPCC_IDLE, &s->idle,
563 REG_GET(MPCC_OGAM_LUT_RAM_CONTROL[mpcc_inst],
545 mpc2_read_mpcc_state( struct mpc *mpc, int mpcc_inst, struct mpcc_state *s) argument
/linux-master/drivers/gpu/drm/amd/display/dc/dcn10/
H A Ddcn10_mpc.c352 static void mpc1_init_mpcc(struct mpcc *mpcc, int mpcc_inst) argument
354 mpcc->mpcc_id = mpcc_inst;
460 int mpcc_inst,
465 REG_GET(MPCC_OPP_ID[mpcc_inst], MPCC_OPP_ID, &s->opp_id);
466 REG_GET(MPCC_TOP_SEL[mpcc_inst], MPCC_TOP_SEL, &s->dpp_id);
467 REG_GET(MPCC_BOT_SEL[mpcc_inst], MPCC_BOT_SEL, &s->bot_mpcc_id);
468 REG_GET_4(MPCC_CONTROL[mpcc_inst], MPCC_MODE, &s->mode,
472 REG_GET_2(MPCC_STATUS[mpcc_inst], MPCC_IDLE, &s->idle,
458 mpc1_read_mpcc_state( struct mpc *mpc, int mpcc_inst, struct mpcc_state *s) argument
H A Ddcn10_mpc.h198 int mpcc_inst,
/linux-master/drivers/gpu/drm/amd/display/dc/dcn35/
H A Ddcn35_pg_cntl.c357 unsigned int mpcc_inst, bool power_on)
362 if (mpcc_inst >= 0 && mpcc_inst < MAX_PIPES)
363 pg_cntl->pg_pipe_res_enable[PG_MPCC][mpcc_inst] = power_on;
356 pg_cntl35_mpcc_pg_control(struct pg_cntl *pg_cntl, unsigned int mpcc_inst, bool power_on) argument
H A Ddcn35_pg_cntl.h179 unsigned int mpcc_inst, bool power_on);
/linux-master/drivers/gpu/drm/amd/display/dc/hwss/dcn30/
H A Ddcn30_hwseq.c417 ASSERT(wb_info->mpcc_inst >= 0);
418 ASSERT(wb_info->mpcc_inst < dc->res_pool->mpcc_count);
424 wb_info->dwb_pipe_inst, wb_info->mpcc_inst);
437 DC_LOG_DWB("%s dwb_pipe_inst = %d, mpcc_inst = %d",\
439 wb_info->mpcc_inst);
516 DC_LOG_DWB("%s dwb_pipe_inst = %d, mpcc_inst = %d",\
518 wb_info->mpcc_inst);
577 /* copy writeback info to local non-const so mpcc_inst can be set */
582 wb_info.mpcc_inst = -1;
590 wb_info.mpcc_inst
[all...]
/linux-master/drivers/gpu/drm/amd/display/dc/dcn30/
H A Ddcn30_mpc.c1032 void mpc3_init_mpcc(struct mpcc *mpcc, int mpcc_inst) argument
1034 mpcc->mpcc_id = mpcc_inst;
1456 int mpcc_inst,
1462 REG_GET(MPCC_OPP_ID[mpcc_inst], MPCC_OPP_ID, &s->opp_id);
1463 REG_GET(MPCC_TOP_SEL[mpcc_inst], MPCC_TOP_SEL, &s->dpp_id);
1464 REG_GET(MPCC_BOT_SEL[mpcc_inst], MPCC_BOT_SEL, &s->bot_mpcc_id);
1465 REG_GET_4(MPCC_CONTROL[mpcc_inst], MPCC_MODE, &s->mode,
1469 REG_GET_2(MPCC_STATUS[mpcc_inst], MPCC_IDLE, &s->idle,
1475 if (rmu_status == mpcc_inst) {
1495 REG_GET_2(MPCC_OGAM_CONTROL[mpcc_inst],
1454 mpc3_read_mpcc_state( struct mpc *mpc, int mpcc_inst, struct mpcc_state *s) argument
[all...]
H A Ddcn30_mpc.h1092 void mpc3_init_mpcc(struct mpcc *mpcc, int mpcc_inst);
/linux-master/drivers/gpu/drm/amd/display/dc/hwss/dcn201/
H A Ddcn201_hwseq.c312 pipe_ctx->plane_res.mpcc_inst = dpp->inst;
320 res_pool->opps[i]->mpcc_disconnect_pending[pipe_ctx->plane_res.mpcc_inst] = true;
409 opp->mpcc_disconnect_pending[pipe_ctx->plane_res.mpcc_inst] = true;
/linux-master/drivers/gpu/drm/amd/display/dc/hwss/dcn10/
H A Ddcn10_hwseq.c1258 opp->mpcc_disconnect_pending[pipe_ctx->plane_res.mpcc_inst] = true;
1463 pipe_ctx->plane_res.mpcc_inst = dpp->inst;
1470 dc->res_pool->opps[i]->mpcc_disconnect_pending[pipe_ctx->plane_res.mpcc_inst] = true;
3322 static struct hubp *get_hubp_by_inst(struct resource_pool *res_pool, int mpcc_inst) argument
3327 if (res_pool->hubps[i]->inst == mpcc_inst)
3340 int mpcc_inst; local
3349 for (mpcc_inst = 0; mpcc_inst < MAX_PIPES; mpcc_inst++) {
3350 if (pipe_ctx->stream_res.opp->mpcc_disconnect_pending[mpcc_inst]) {
[all...]
/linux-master/drivers/gpu/drm/amd/display/dc/dce/
H A Ddmub_psr.c339 copy_settings_data->mpcc_inst = pipe_ctx->plane_res.mpcc_inst;
/linux-master/drivers/gpu/drm/amd/display/dc/
H A Ddc_stream.h103 int mpcc_inst; member in struct:dc_writeback_info
H A Ddc.h1487 int mpcc_inst);
/linux-master/drivers/gpu/drm/amd/display/dc/hwss/dcn35/
H A Ddcn35_hwseq.c776 pipe_ctx->plane_res.mpcc_inst = dpp->inst;
783 dc->res_pool->opps[i]->mpcc_disconnect_pending[pipe_ctx->plane_res.mpcc_inst] = true;
982 pipe_ctx->plane_res.mpcc_inst >= 0)
983 update_state->pg_pipe_res_update[PG_MPCC][pipe_ctx->plane_res.mpcc_inst] = false;
1037 update_state->pg_pipe_res_update[j][new_pipe->plane_res.mpcc_inst] = true;
/linux-master/drivers/gpu/drm/amd/display/dc/inc/
H A Dcore_types.h345 uint8_t mpcc_inst; member in struct:plane_resource
/linux-master/drivers/gpu/drm/amd/display/dc/core/
H A Ddc_resource.c2314 split_pipe->plane_res.mpcc_inst = pool->dpps[i]->inst;
3275 pipe_ctx->plane_res.mpcc_inst = pool->dpps[id_src[i]]->inst;
3280 pool->mpc->funcs->read_mpcc_state(pool->mpc, pipe_ctx->plane_res.mpcc_inst, &s);
3283 pool->mpc->mpcc_array[pipe_ctx->plane_res.mpcc_inst].dpp_id =
3287 pool->mpc->mpcc_array[pipe_ctx->plane_res.mpcc_inst].mpcc_bot =
3393 pipe_ctx->plane_res.mpcc_inst = pool->dpps[pipe_idx]->inst;
4921 sec_pipe->plane_res.mpcc_inst = pool->dpps[pipe_idx]->inst;
H A Ddc.c3565 int mpcc_inst; local
3581 mpcc_inst = hubp->inst;
3585 (dc->res_pool->opps[opp_inst]->mpcc_disconnect_pending[mpcc_inst])) {
3586 dc->res_pool->mpc->funcs->wait_for_idle(dc->res_pool->mpc, mpcc_inst);
3587 dc->res_pool->opps[opp_inst]->mpcc_disconnect_pending[mpcc_inst] = false;
/linux-master/drivers/gpu/drm/amd/display/dc/resource/dcn20/
H A Ddcn20_resource.c1482 next_odm_pipe->plane_res.mpcc_inst = pool->dpps[next_odm_pipe->pipe_idx]->inst;
1567 secondary_pipe->plane_res.mpcc_inst = pool->dpps[secondary_pipe->pipe_idx]->inst;
2183 sec_dpp_pipe->plane_res.mpcc_inst = pool->dpps[sec_dpp_pipe->pipe_idx]->inst;
/linux-master/drivers/gpu/drm/amd/display/dc/resource/dcn32/
H A Ddcn32_resource.c2623 idle_pipe->plane_res.mpcc_inst = pool->dpps[idle_pipe->pipe_idx]->inst;
2682 free_pipe->plane_res.mpcc_inst =
2715 free_pipe->plane_res.mpcc_inst = pool->dpps[free_pipe_idx]->inst;
/linux-master/drivers/gpu/drm/amd/display/dc/resource/dcn201/
H A Ddcn201_resource.c1019 idle_pipe->plane_res.mpcc_inst = pool->dpps[idle_pipe->pipe_idx]->inst;
/linux-master/drivers/gpu/drm/amd/display/dc/resource/dcn10/
H A Ddcn10_resource.c1116 idle_pipe->plane_res.mpcc_inst = pool->dpps[idle_pipe->pipe_idx]->inst;
/linux-master/drivers/gpu/drm/amd/display/dmub/inc/
H A Ddmub_cmd.h2358 uint8_t mpcc_inst; member in struct:dmub_cmd_psr_copy_settings_data

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