1/* 2* Copyright 2016 Advanced Micro Devices, Inc. 3 * Copyright 2019 Raptor Engineering, LLC 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: AMD 24 * 25 */ 26 27#include "dm_services.h" 28#include "dc.h" 29 30#include "dcn20/dcn20_init.h" 31 32#include "resource.h" 33#include "include/irq_service_interface.h" 34#include "dcn20/dcn20_resource.h" 35 36#include "dml/dcn20/dcn20_fpu.h" 37 38#include "dcn10/dcn10_hubp.h" 39#include "dcn10/dcn10_ipp.h" 40#include "dcn20/dcn20_hubbub.h" 41#include "dcn20/dcn20_mpc.h" 42#include "dcn20/dcn20_hubp.h" 43#include "irq/dcn20/irq_service_dcn20.h" 44#include "dcn20/dcn20_dpp.h" 45#include "dcn20/dcn20_optc.h" 46#include "dcn20/dcn20_hwseq.h" 47#include "dce110/dce110_hwseq.h" 48#include "dcn10/dcn10_resource.h" 49#include "dcn20/dcn20_opp.h" 50 51#include "dcn20/dcn20_dsc.h" 52 53#include "dcn20/dcn20_link_encoder.h" 54#include "dcn20/dcn20_stream_encoder.h" 55#include "dce/dce_clock_source.h" 56#include "dce/dce_audio.h" 57#include "dce/dce_hwseq.h" 58#include "virtual/virtual_stream_encoder.h" 59#include "dce110/dce110_resource.h" 60#include "dml/display_mode_vba.h" 61#include "dcn20/dcn20_dccg.h" 62#include "dcn20/dcn20_vmid.h" 63#include "dce/dce_panel_cntl.h" 64 65#include "navi10_ip_offset.h" 66 67#include "dcn/dcn_2_0_0_offset.h" 68#include "dcn/dcn_2_0_0_sh_mask.h" 69#include "dpcs/dpcs_2_0_0_offset.h" 70#include "dpcs/dpcs_2_0_0_sh_mask.h" 71 72#include "nbio/nbio_2_3_offset.h" 73 74#include "dcn20/dcn20_dwb.h" 75#include "dcn20/dcn20_mmhubbub.h" 76 77#include "mmhub/mmhub_2_0_0_offset.h" 78#include "mmhub/mmhub_2_0_0_sh_mask.h" 79 80#include "reg_helper.h" 81#include "dce/dce_abm.h" 82#include "dce/dce_dmcu.h" 83#include "dce/dce_aux.h" 84#include "dce/dce_i2c.h" 85#include "vm_helper.h" 86#include "link_enc_cfg.h" 87 88#include "amdgpu_socbb.h" 89 90#include "link.h" 91#define DC_LOGGER_INIT(logger) 92 93#ifndef mmDP0_DP_DPHY_INTERNAL_CTRL 94 #define mmDP0_DP_DPHY_INTERNAL_CTRL 0x210f 95 #define mmDP0_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 96 #define mmDP1_DP_DPHY_INTERNAL_CTRL 0x220f 97 #define mmDP1_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 98 #define mmDP2_DP_DPHY_INTERNAL_CTRL 0x230f 99 #define mmDP2_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 100 #define mmDP3_DP_DPHY_INTERNAL_CTRL 0x240f 101 #define mmDP3_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 102 #define mmDP4_DP_DPHY_INTERNAL_CTRL 0x250f 103 #define mmDP4_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 104 #define mmDP5_DP_DPHY_INTERNAL_CTRL 0x260f 105 #define mmDP5_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 106 #define mmDP6_DP_DPHY_INTERNAL_CTRL 0x270f 107 #define mmDP6_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2 108#endif 109 110 111enum dcn20_clk_src_array_id { 112 DCN20_CLK_SRC_PLL0, 113 DCN20_CLK_SRC_PLL1, 114 DCN20_CLK_SRC_PLL2, 115 DCN20_CLK_SRC_PLL3, 116 DCN20_CLK_SRC_PLL4, 117 DCN20_CLK_SRC_PLL5, 118 DCN20_CLK_SRC_TOTAL 119}; 120 121/* begin ********************* 122 * macros to expend register list macro defined in HW object header file */ 123 124/* DCN */ 125#define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg 126 127#define BASE(seg) BASE_INNER(seg) 128 129#define SR(reg_name)\ 130 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \ 131 mm ## reg_name 132 133#define SRI(reg_name, block, id)\ 134 .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 135 mm ## block ## id ## _ ## reg_name 136 137#define SRI2_DWB(reg_name, block, id)\ 138 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \ 139 mm ## reg_name 140#define SF_DWB(reg_name, field_name, post_fix)\ 141 .field_name = reg_name ## __ ## field_name ## post_fix 142 143#define SF_DWB2(reg_name, block, id, field_name, post_fix) \ 144 .field_name = reg_name ## __ ## field_name ## post_fix 145 146#define SRIR(var_name, reg_name, block, id)\ 147 .var_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 148 mm ## block ## id ## _ ## reg_name 149 150#define SRII(reg_name, block, id)\ 151 .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 152 mm ## block ## id ## _ ## reg_name 153 154#define DCCG_SRII(reg_name, block, id)\ 155 .block ## _ ## reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 156 mm ## block ## id ## _ ## reg_name 157 158#define VUPDATE_SRII(reg_name, block, id)\ 159 .reg_name[id] = BASE(mm ## reg_name ## _ ## block ## id ## _BASE_IDX) + \ 160 mm ## reg_name ## _ ## block ## id 161 162/* NBIO */ 163#define NBIO_BASE_INNER(seg) \ 164 NBIO_BASE__INST0_SEG ## seg 165 166#define NBIO_BASE(seg) \ 167 NBIO_BASE_INNER(seg) 168 169#define NBIO_SR(reg_name)\ 170 .reg_name = NBIO_BASE(mm ## reg_name ## _BASE_IDX) + \ 171 mm ## reg_name 172 173/* MMHUB */ 174#define MMHUB_BASE_INNER(seg) \ 175 MMHUB_BASE__INST0_SEG ## seg 176 177#define MMHUB_BASE(seg) \ 178 MMHUB_BASE_INNER(seg) 179 180#define MMHUB_SR(reg_name)\ 181 .reg_name = MMHUB_BASE(mmMM ## reg_name ## _BASE_IDX) + \ 182 mmMM ## reg_name 183 184static const struct bios_registers bios_regs = { 185 NBIO_SR(BIOS_SCRATCH_3), 186 NBIO_SR(BIOS_SCRATCH_6) 187}; 188 189#define clk_src_regs(index, pllid)\ 190[index] = {\ 191 CS_COMMON_REG_LIST_DCN2_0(index, pllid),\ 192} 193 194static const struct dce110_clk_src_regs clk_src_regs[] = { 195 clk_src_regs(0, A), 196 clk_src_regs(1, B), 197 clk_src_regs(2, C), 198 clk_src_regs(3, D), 199 clk_src_regs(4, E), 200 clk_src_regs(5, F) 201}; 202 203static const struct dce110_clk_src_shift cs_shift = { 204 CS_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT) 205}; 206 207static const struct dce110_clk_src_mask cs_mask = { 208 CS_COMMON_MASK_SH_LIST_DCN2_0(_MASK) 209}; 210 211static const struct dce_dmcu_registers dmcu_regs = { 212 DMCU_DCN10_REG_LIST() 213}; 214 215static const struct dce_dmcu_shift dmcu_shift = { 216 DMCU_MASK_SH_LIST_DCN10(__SHIFT) 217}; 218 219static const struct dce_dmcu_mask dmcu_mask = { 220 DMCU_MASK_SH_LIST_DCN10(_MASK) 221}; 222 223static const struct dce_abm_registers abm_regs = { 224 ABM_DCN20_REG_LIST() 225}; 226 227static const struct dce_abm_shift abm_shift = { 228 ABM_MASK_SH_LIST_DCN20(__SHIFT) 229}; 230 231static const struct dce_abm_mask abm_mask = { 232 ABM_MASK_SH_LIST_DCN20(_MASK) 233}; 234 235#define audio_regs(id)\ 236[id] = {\ 237 AUD_COMMON_REG_LIST(id)\ 238} 239 240static const struct dce_audio_registers audio_regs[] = { 241 audio_regs(0), 242 audio_regs(1), 243 audio_regs(2), 244 audio_regs(3), 245 audio_regs(4), 246 audio_regs(5), 247 audio_regs(6), 248}; 249 250#define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\ 251 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\ 252 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\ 253 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh) 254 255static const struct dce_audio_shift audio_shift = { 256 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT) 257}; 258 259static const struct dce_audio_mask audio_mask = { 260 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK) 261}; 262 263#define stream_enc_regs(id)\ 264[id] = {\ 265 SE_DCN2_REG_LIST(id)\ 266} 267 268static const struct dcn10_stream_enc_registers stream_enc_regs[] = { 269 stream_enc_regs(0), 270 stream_enc_regs(1), 271 stream_enc_regs(2), 272 stream_enc_regs(3), 273 stream_enc_regs(4), 274 stream_enc_regs(5), 275}; 276 277static const struct dcn10_stream_encoder_shift se_shift = { 278 SE_COMMON_MASK_SH_LIST_DCN20(__SHIFT) 279}; 280 281static const struct dcn10_stream_encoder_mask se_mask = { 282 SE_COMMON_MASK_SH_LIST_DCN20(_MASK) 283}; 284 285 286#define aux_regs(id)\ 287[id] = {\ 288 DCN2_AUX_REG_LIST(id)\ 289} 290 291static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = { 292 aux_regs(0), 293 aux_regs(1), 294 aux_regs(2), 295 aux_regs(3), 296 aux_regs(4), 297 aux_regs(5) 298}; 299 300#define hpd_regs(id)\ 301[id] = {\ 302 HPD_REG_LIST(id)\ 303} 304 305static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = { 306 hpd_regs(0), 307 hpd_regs(1), 308 hpd_regs(2), 309 hpd_regs(3), 310 hpd_regs(4), 311 hpd_regs(5) 312}; 313 314#define link_regs(id, phyid)\ 315[id] = {\ 316 LE_DCN10_REG_LIST(id), \ 317 UNIPHY_DCN2_REG_LIST(phyid), \ 318 DPCS_DCN2_REG_LIST(id), \ 319 SRI(DP_DPHY_INTERNAL_CTRL, DP, id) \ 320} 321 322static const struct dcn10_link_enc_registers link_enc_regs[] = { 323 link_regs(0, A), 324 link_regs(1, B), 325 link_regs(2, C), 326 link_regs(3, D), 327 link_regs(4, E), 328 link_regs(5, F) 329}; 330 331static const struct dcn10_link_enc_shift le_shift = { 332 LINK_ENCODER_MASK_SH_LIST_DCN20(__SHIFT),\ 333 DPCS_DCN2_MASK_SH_LIST(__SHIFT) 334}; 335 336static const struct dcn10_link_enc_mask le_mask = { 337 LINK_ENCODER_MASK_SH_LIST_DCN20(_MASK),\ 338 DPCS_DCN2_MASK_SH_LIST(_MASK) 339}; 340 341static const struct dce_panel_cntl_registers panel_cntl_regs[] = { 342 { DCN_PANEL_CNTL_REG_LIST() } 343}; 344 345static const struct dce_panel_cntl_shift panel_cntl_shift = { 346 DCE_PANEL_CNTL_MASK_SH_LIST(__SHIFT) 347}; 348 349static const struct dce_panel_cntl_mask panel_cntl_mask = { 350 DCE_PANEL_CNTL_MASK_SH_LIST(_MASK) 351}; 352 353#define ipp_regs(id)\ 354[id] = {\ 355 IPP_REG_LIST_DCN20(id),\ 356} 357 358static const struct dcn10_ipp_registers ipp_regs[] = { 359 ipp_regs(0), 360 ipp_regs(1), 361 ipp_regs(2), 362 ipp_regs(3), 363 ipp_regs(4), 364 ipp_regs(5), 365}; 366 367static const struct dcn10_ipp_shift ipp_shift = { 368 IPP_MASK_SH_LIST_DCN20(__SHIFT) 369}; 370 371static const struct dcn10_ipp_mask ipp_mask = { 372 IPP_MASK_SH_LIST_DCN20(_MASK), 373}; 374 375#define opp_regs(id)\ 376[id] = {\ 377 OPP_REG_LIST_DCN20(id),\ 378} 379 380static const struct dcn20_opp_registers opp_regs[] = { 381 opp_regs(0), 382 opp_regs(1), 383 opp_regs(2), 384 opp_regs(3), 385 opp_regs(4), 386 opp_regs(5), 387}; 388 389static const struct dcn20_opp_shift opp_shift = { 390 OPP_MASK_SH_LIST_DCN20(__SHIFT) 391}; 392 393static const struct dcn20_opp_mask opp_mask = { 394 OPP_MASK_SH_LIST_DCN20(_MASK) 395}; 396 397#define aux_engine_regs(id)\ 398[id] = {\ 399 AUX_COMMON_REG_LIST0(id), \ 400 .AUXN_IMPCAL = 0, \ 401 .AUXP_IMPCAL = 0, \ 402 .AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK, \ 403} 404 405static const struct dce110_aux_registers aux_engine_regs[] = { 406 aux_engine_regs(0), 407 aux_engine_regs(1), 408 aux_engine_regs(2), 409 aux_engine_regs(3), 410 aux_engine_regs(4), 411 aux_engine_regs(5) 412}; 413 414#define tf_regs(id)\ 415[id] = {\ 416 TF_REG_LIST_DCN20(id),\ 417 TF_REG_LIST_DCN20_COMMON_APPEND(id),\ 418} 419 420static const struct dcn2_dpp_registers tf_regs[] = { 421 tf_regs(0), 422 tf_regs(1), 423 tf_regs(2), 424 tf_regs(3), 425 tf_regs(4), 426 tf_regs(5), 427}; 428 429static const struct dcn2_dpp_shift tf_shift = { 430 TF_REG_LIST_SH_MASK_DCN20(__SHIFT), 431 TF_DEBUG_REG_LIST_SH_DCN20 432}; 433 434static const struct dcn2_dpp_mask tf_mask = { 435 TF_REG_LIST_SH_MASK_DCN20(_MASK), 436 TF_DEBUG_REG_LIST_MASK_DCN20 437}; 438 439#define dwbc_regs_dcn2(id)\ 440[id] = {\ 441 DWBC_COMMON_REG_LIST_DCN2_0(id),\ 442 } 443 444static const struct dcn20_dwbc_registers dwbc20_regs[] = { 445 dwbc_regs_dcn2(0), 446}; 447 448static const struct dcn20_dwbc_shift dwbc20_shift = { 449 DWBC_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT) 450}; 451 452static const struct dcn20_dwbc_mask dwbc20_mask = { 453 DWBC_COMMON_MASK_SH_LIST_DCN2_0(_MASK) 454}; 455 456#define mcif_wb_regs_dcn2(id)\ 457[id] = {\ 458 MCIF_WB_COMMON_REG_LIST_DCN2_0(id),\ 459 } 460 461static const struct dcn20_mmhubbub_registers mcif_wb20_regs[] = { 462 mcif_wb_regs_dcn2(0), 463}; 464 465static const struct dcn20_mmhubbub_shift mcif_wb20_shift = { 466 MCIF_WB_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT) 467}; 468 469static const struct dcn20_mmhubbub_mask mcif_wb20_mask = { 470 MCIF_WB_COMMON_MASK_SH_LIST_DCN2_0(_MASK) 471}; 472 473static const struct dcn20_mpc_registers mpc_regs = { 474 MPC_REG_LIST_DCN2_0(0), 475 MPC_REG_LIST_DCN2_0(1), 476 MPC_REG_LIST_DCN2_0(2), 477 MPC_REG_LIST_DCN2_0(3), 478 MPC_REG_LIST_DCN2_0(4), 479 MPC_REG_LIST_DCN2_0(5), 480 MPC_OUT_MUX_REG_LIST_DCN2_0(0), 481 MPC_OUT_MUX_REG_LIST_DCN2_0(1), 482 MPC_OUT_MUX_REG_LIST_DCN2_0(2), 483 MPC_OUT_MUX_REG_LIST_DCN2_0(3), 484 MPC_OUT_MUX_REG_LIST_DCN2_0(4), 485 MPC_OUT_MUX_REG_LIST_DCN2_0(5), 486 MPC_DBG_REG_LIST_DCN2_0() 487}; 488 489static const struct dcn20_mpc_shift mpc_shift = { 490 MPC_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT), 491 MPC_DEBUG_REG_LIST_SH_DCN20 492}; 493 494static const struct dcn20_mpc_mask mpc_mask = { 495 MPC_COMMON_MASK_SH_LIST_DCN2_0(_MASK), 496 MPC_DEBUG_REG_LIST_MASK_DCN20 497}; 498 499#define tg_regs(id)\ 500[id] = {TG_COMMON_REG_LIST_DCN2_0(id)} 501 502 503static const struct dcn_optc_registers tg_regs[] = { 504 tg_regs(0), 505 tg_regs(1), 506 tg_regs(2), 507 tg_regs(3), 508 tg_regs(4), 509 tg_regs(5) 510}; 511 512static const struct dcn_optc_shift tg_shift = { 513 TG_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT) 514}; 515 516static const struct dcn_optc_mask tg_mask = { 517 TG_COMMON_MASK_SH_LIST_DCN2_0(_MASK) 518}; 519 520#define hubp_regs(id)\ 521[id] = {\ 522 HUBP_REG_LIST_DCN20(id)\ 523} 524 525static const struct dcn_hubp2_registers hubp_regs[] = { 526 hubp_regs(0), 527 hubp_regs(1), 528 hubp_regs(2), 529 hubp_regs(3), 530 hubp_regs(4), 531 hubp_regs(5) 532}; 533 534static const struct dcn_hubp2_shift hubp_shift = { 535 HUBP_MASK_SH_LIST_DCN20(__SHIFT) 536}; 537 538static const struct dcn_hubp2_mask hubp_mask = { 539 HUBP_MASK_SH_LIST_DCN20(_MASK) 540}; 541 542static const struct dcn_hubbub_registers hubbub_reg = { 543 HUBBUB_REG_LIST_DCN20(0) 544}; 545 546static const struct dcn_hubbub_shift hubbub_shift = { 547 HUBBUB_MASK_SH_LIST_DCN20(__SHIFT) 548}; 549 550static const struct dcn_hubbub_mask hubbub_mask = { 551 HUBBUB_MASK_SH_LIST_DCN20(_MASK) 552}; 553 554#define vmid_regs(id)\ 555[id] = {\ 556 DCN20_VMID_REG_LIST(id)\ 557} 558 559static const struct dcn_vmid_registers vmid_regs[] = { 560 vmid_regs(0), 561 vmid_regs(1), 562 vmid_regs(2), 563 vmid_regs(3), 564 vmid_regs(4), 565 vmid_regs(5), 566 vmid_regs(6), 567 vmid_regs(7), 568 vmid_regs(8), 569 vmid_regs(9), 570 vmid_regs(10), 571 vmid_regs(11), 572 vmid_regs(12), 573 vmid_regs(13), 574 vmid_regs(14), 575 vmid_regs(15) 576}; 577 578static const struct dcn20_vmid_shift vmid_shifts = { 579 DCN20_VMID_MASK_SH_LIST(__SHIFT) 580}; 581 582static const struct dcn20_vmid_mask vmid_masks = { 583 DCN20_VMID_MASK_SH_LIST(_MASK) 584}; 585 586static const struct dce110_aux_registers_shift aux_shift = { 587 DCN_AUX_MASK_SH_LIST(__SHIFT) 588}; 589 590static const struct dce110_aux_registers_mask aux_mask = { 591 DCN_AUX_MASK_SH_LIST(_MASK) 592}; 593 594static int map_transmitter_id_to_phy_instance( 595 enum transmitter transmitter) 596{ 597 switch (transmitter) { 598 case TRANSMITTER_UNIPHY_A: 599 return 0; 600 break; 601 case TRANSMITTER_UNIPHY_B: 602 return 1; 603 break; 604 case TRANSMITTER_UNIPHY_C: 605 return 2; 606 break; 607 case TRANSMITTER_UNIPHY_D: 608 return 3; 609 break; 610 case TRANSMITTER_UNIPHY_E: 611 return 4; 612 break; 613 case TRANSMITTER_UNIPHY_F: 614 return 5; 615 break; 616 default: 617 ASSERT(0); 618 return 0; 619 } 620} 621 622#define dsc_regsDCN20(id)\ 623[id] = {\ 624 DSC_REG_LIST_DCN20(id)\ 625} 626 627static const struct dcn20_dsc_registers dsc_regs[] = { 628 dsc_regsDCN20(0), 629 dsc_regsDCN20(1), 630 dsc_regsDCN20(2), 631 dsc_regsDCN20(3), 632 dsc_regsDCN20(4), 633 dsc_regsDCN20(5) 634}; 635 636static const struct dcn20_dsc_shift dsc_shift = { 637 DSC_REG_LIST_SH_MASK_DCN20(__SHIFT) 638}; 639 640static const struct dcn20_dsc_mask dsc_mask = { 641 DSC_REG_LIST_SH_MASK_DCN20(_MASK) 642}; 643 644static const struct dccg_registers dccg_regs = { 645 DCCG_REG_LIST_DCN2() 646}; 647 648static const struct dccg_shift dccg_shift = { 649 DCCG_MASK_SH_LIST_DCN2(__SHIFT) 650}; 651 652static const struct dccg_mask dccg_mask = { 653 DCCG_MASK_SH_LIST_DCN2(_MASK) 654}; 655 656static const struct resource_caps res_cap_nv10 = { 657 .num_timing_generator = 6, 658 .num_opp = 6, 659 .num_video_plane = 6, 660 .num_audio = 7, 661 .num_stream_encoder = 6, 662 .num_pll = 6, 663 .num_dwb = 1, 664 .num_ddc = 6, 665 .num_vmid = 16, 666 .num_dsc = 6, 667}; 668 669static const struct dc_plane_cap plane_cap = { 670 .type = DC_PLANE_TYPE_DCN_UNIVERSAL, 671 .per_pixel_alpha = true, 672 673 .pixel_format_support = { 674 .argb8888 = true, 675 .nv12 = true, 676 .fp16 = true, 677 .p010 = true 678 }, 679 680 .max_upscale_factor = { 681 .argb8888 = 16000, 682 .nv12 = 16000, 683 .fp16 = 1 684 }, 685 686 .max_downscale_factor = { 687 .argb8888 = 250, 688 .nv12 = 250, 689 .fp16 = 1 690 }, 691 16, 692 16 693}; 694static const struct resource_caps res_cap_nv14 = { 695 .num_timing_generator = 5, 696 .num_opp = 5, 697 .num_video_plane = 5, 698 .num_audio = 6, 699 .num_stream_encoder = 5, 700 .num_pll = 5, 701 .num_dwb = 1, 702 .num_ddc = 5, 703 .num_vmid = 16, 704 .num_dsc = 5, 705}; 706 707static const struct dc_debug_options debug_defaults_drv = { 708 .disable_dmcu = false, 709 .force_abm_enable = false, 710 .timing_trace = false, 711 .clock_trace = true, 712 .disable_pplib_clock_request = true, 713 .pipe_split_policy = MPC_SPLIT_AVOID_MULT_DISP, 714 .force_single_disp_pipe_split = false, 715 .disable_dcc = DCC_ENABLE, 716 .vsr_support = true, 717 .performance_trace = false, 718 .max_downscale_src_width = 5120,/*upto 5K*/ 719 .disable_pplib_wm_range = false, 720 .scl_reset_length10 = true, 721 .sanity_checks = false, 722 .underflow_assert_delay_us = 0xFFFFFFFF, 723 .enable_legacy_fast_update = true, 724 .using_dml2 = false, 725}; 726 727void dcn20_dpp_destroy(struct dpp **dpp) 728{ 729 kfree(TO_DCN20_DPP(*dpp)); 730 *dpp = NULL; 731} 732 733struct dpp *dcn20_dpp_create( 734 struct dc_context *ctx, 735 uint32_t inst) 736{ 737 struct dcn20_dpp *dpp = 738 kzalloc(sizeof(struct dcn20_dpp), GFP_ATOMIC); 739 740 if (!dpp) 741 return NULL; 742 743 if (dpp2_construct(dpp, ctx, inst, 744 &tf_regs[inst], &tf_shift, &tf_mask)) 745 return &dpp->base; 746 747 BREAK_TO_DEBUGGER(); 748 kfree(dpp); 749 return NULL; 750} 751 752struct input_pixel_processor *dcn20_ipp_create( 753 struct dc_context *ctx, uint32_t inst) 754{ 755 struct dcn10_ipp *ipp = 756 kzalloc(sizeof(struct dcn10_ipp), GFP_ATOMIC); 757 758 if (!ipp) { 759 BREAK_TO_DEBUGGER(); 760 return NULL; 761 } 762 763 dcn20_ipp_construct(ipp, ctx, inst, 764 &ipp_regs[inst], &ipp_shift, &ipp_mask); 765 return &ipp->base; 766} 767 768 769struct output_pixel_processor *dcn20_opp_create( 770 struct dc_context *ctx, uint32_t inst) 771{ 772 struct dcn20_opp *opp = 773 kzalloc(sizeof(struct dcn20_opp), GFP_ATOMIC); 774 775 if (!opp) { 776 BREAK_TO_DEBUGGER(); 777 return NULL; 778 } 779 780 dcn20_opp_construct(opp, ctx, inst, 781 &opp_regs[inst], &opp_shift, &opp_mask); 782 return &opp->base; 783} 784 785struct dce_aux *dcn20_aux_engine_create( 786 struct dc_context *ctx, 787 uint32_t inst) 788{ 789 struct aux_engine_dce110 *aux_engine = 790 kzalloc(sizeof(struct aux_engine_dce110), GFP_ATOMIC); 791 792 if (!aux_engine) 793 return NULL; 794 795 dce110_aux_engine_construct(aux_engine, ctx, inst, 796 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD, 797 &aux_engine_regs[inst], 798 &aux_mask, 799 &aux_shift, 800 ctx->dc->caps.extended_aux_timeout_support); 801 802 return &aux_engine->base; 803} 804#define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) } 805 806static const struct dce_i2c_registers i2c_hw_regs[] = { 807 i2c_inst_regs(1), 808 i2c_inst_regs(2), 809 i2c_inst_regs(3), 810 i2c_inst_regs(4), 811 i2c_inst_regs(5), 812 i2c_inst_regs(6), 813}; 814 815static const struct dce_i2c_shift i2c_shifts = { 816 I2C_COMMON_MASK_SH_LIST_DCN2(__SHIFT) 817}; 818 819static const struct dce_i2c_mask i2c_masks = { 820 I2C_COMMON_MASK_SH_LIST_DCN2(_MASK) 821}; 822 823struct dce_i2c_hw *dcn20_i2c_hw_create( 824 struct dc_context *ctx, 825 uint32_t inst) 826{ 827 struct dce_i2c_hw *dce_i2c_hw = 828 kzalloc(sizeof(struct dce_i2c_hw), GFP_ATOMIC); 829 830 if (!dce_i2c_hw) 831 return NULL; 832 833 dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst, 834 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks); 835 836 return dce_i2c_hw; 837} 838struct mpc *dcn20_mpc_create(struct dc_context *ctx) 839{ 840 struct dcn20_mpc *mpc20 = kzalloc(sizeof(struct dcn20_mpc), 841 GFP_ATOMIC); 842 843 if (!mpc20) 844 return NULL; 845 846 dcn20_mpc_construct(mpc20, ctx, 847 &mpc_regs, 848 &mpc_shift, 849 &mpc_mask, 850 6); 851 852 return &mpc20->base; 853} 854 855struct hubbub *dcn20_hubbub_create(struct dc_context *ctx) 856{ 857 int i; 858 struct dcn20_hubbub *hubbub = kzalloc(sizeof(struct dcn20_hubbub), 859 GFP_ATOMIC); 860 861 if (!hubbub) 862 return NULL; 863 864 hubbub2_construct(hubbub, ctx, 865 &hubbub_reg, 866 &hubbub_shift, 867 &hubbub_mask); 868 869 for (i = 0; i < res_cap_nv10.num_vmid; i++) { 870 struct dcn20_vmid *vmid = &hubbub->vmid[i]; 871 872 vmid->ctx = ctx; 873 874 vmid->regs = &vmid_regs[i]; 875 vmid->shifts = &vmid_shifts; 876 vmid->masks = &vmid_masks; 877 } 878 879 return &hubbub->base; 880} 881 882struct timing_generator *dcn20_timing_generator_create( 883 struct dc_context *ctx, 884 uint32_t instance) 885{ 886 struct optc *tgn10 = 887 kzalloc(sizeof(struct optc), GFP_ATOMIC); 888 889 if (!tgn10) 890 return NULL; 891 892 tgn10->base.inst = instance; 893 tgn10->base.ctx = ctx; 894 895 tgn10->tg_regs = &tg_regs[instance]; 896 tgn10->tg_shift = &tg_shift; 897 tgn10->tg_mask = &tg_mask; 898 899 dcn20_timing_generator_init(tgn10); 900 901 return &tgn10->base; 902} 903 904static const struct encoder_feature_support link_enc_feature = { 905 .max_hdmi_deep_color = COLOR_DEPTH_121212, 906 .max_hdmi_pixel_clock = 600000, 907 .hdmi_ycbcr420_supported = true, 908 .dp_ycbcr420_supported = true, 909 .fec_supported = true, 910 .flags.bits.IS_HBR2_CAPABLE = true, 911 .flags.bits.IS_HBR3_CAPABLE = true, 912 .flags.bits.IS_TPS3_CAPABLE = true, 913 .flags.bits.IS_TPS4_CAPABLE = true 914}; 915 916struct link_encoder *dcn20_link_encoder_create( 917 struct dc_context *ctx, 918 const struct encoder_init_data *enc_init_data) 919{ 920 struct dcn20_link_encoder *enc20 = 921 kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL); 922 int link_regs_id; 923 924 if (!enc20) 925 return NULL; 926 927 link_regs_id = 928 map_transmitter_id_to_phy_instance(enc_init_data->transmitter); 929 930 dcn20_link_encoder_construct(enc20, 931 enc_init_data, 932 &link_enc_feature, 933 &link_enc_regs[link_regs_id], 934 &link_enc_aux_regs[enc_init_data->channel - 1], 935 &link_enc_hpd_regs[enc_init_data->hpd_source], 936 &le_shift, 937 &le_mask); 938 939 return &enc20->enc10.base; 940} 941 942static struct panel_cntl *dcn20_panel_cntl_create(const struct panel_cntl_init_data *init_data) 943{ 944 struct dce_panel_cntl *panel_cntl = 945 kzalloc(sizeof(struct dce_panel_cntl), GFP_KERNEL); 946 947 if (!panel_cntl) 948 return NULL; 949 950 dce_panel_cntl_construct(panel_cntl, 951 init_data, 952 &panel_cntl_regs[init_data->inst], 953 &panel_cntl_shift, 954 &panel_cntl_mask); 955 956 return &panel_cntl->base; 957} 958 959static struct clock_source *dcn20_clock_source_create( 960 struct dc_context *ctx, 961 struct dc_bios *bios, 962 enum clock_source_id id, 963 const struct dce110_clk_src_regs *regs, 964 bool dp_clk_src) 965{ 966 struct dce110_clk_src *clk_src = 967 kzalloc(sizeof(struct dce110_clk_src), GFP_ATOMIC); 968 969 if (!clk_src) 970 return NULL; 971 972 if (dcn20_clk_src_construct(clk_src, ctx, bios, id, 973 regs, &cs_shift, &cs_mask)) { 974 clk_src->base.dp_clk_src = dp_clk_src; 975 return &clk_src->base; 976 } 977 978 kfree(clk_src); 979 BREAK_TO_DEBUGGER(); 980 return NULL; 981} 982 983static void read_dce_straps( 984 struct dc_context *ctx, 985 struct resource_straps *straps) 986{ 987 generic_reg_get(ctx, mmDC_PINSTRAPS + BASE(mmDC_PINSTRAPS_BASE_IDX), 988 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio); 989} 990 991static struct audio *dcn20_create_audio( 992 struct dc_context *ctx, unsigned int inst) 993{ 994 return dce_audio_create(ctx, inst, 995 &audio_regs[inst], &audio_shift, &audio_mask); 996} 997 998struct stream_encoder *dcn20_stream_encoder_create( 999 enum engine_id eng_id, 1000 struct dc_context *ctx) 1001{ 1002 struct dcn10_stream_encoder *enc1 = 1003 kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL); 1004 1005 if (!enc1) 1006 return NULL; 1007 1008 if (ASICREV_IS_NAVI14_M(ctx->asic_id.hw_internal_rev)) { 1009 if (eng_id >= ENGINE_ID_DIGD) 1010 eng_id++; 1011 } 1012 1013 dcn20_stream_encoder_construct(enc1, ctx, ctx->dc_bios, eng_id, 1014 &stream_enc_regs[eng_id], 1015 &se_shift, &se_mask); 1016 1017 return &enc1->base; 1018} 1019 1020static const struct dce_hwseq_registers hwseq_reg = { 1021 HWSEQ_DCN2_REG_LIST() 1022}; 1023 1024static const struct dce_hwseq_shift hwseq_shift = { 1025 HWSEQ_DCN2_MASK_SH_LIST(__SHIFT) 1026}; 1027 1028static const struct dce_hwseq_mask hwseq_mask = { 1029 HWSEQ_DCN2_MASK_SH_LIST(_MASK) 1030}; 1031 1032struct dce_hwseq *dcn20_hwseq_create( 1033 struct dc_context *ctx) 1034{ 1035 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL); 1036 1037 if (hws) { 1038 hws->ctx = ctx; 1039 hws->regs = &hwseq_reg; 1040 hws->shifts = &hwseq_shift; 1041 hws->masks = &hwseq_mask; 1042 } 1043 return hws; 1044} 1045 1046static const struct resource_create_funcs res_create_funcs = { 1047 .read_dce_straps = read_dce_straps, 1048 .create_audio = dcn20_create_audio, 1049 .create_stream_encoder = dcn20_stream_encoder_create, 1050 .create_hwseq = dcn20_hwseq_create, 1051}; 1052 1053static void dcn20_pp_smu_destroy(struct pp_smu_funcs **pp_smu); 1054 1055void dcn20_clock_source_destroy(struct clock_source **clk_src) 1056{ 1057 kfree(TO_DCE110_CLK_SRC(*clk_src)); 1058 *clk_src = NULL; 1059} 1060 1061 1062struct display_stream_compressor *dcn20_dsc_create( 1063 struct dc_context *ctx, uint32_t inst) 1064{ 1065 struct dcn20_dsc *dsc = 1066 kzalloc(sizeof(struct dcn20_dsc), GFP_ATOMIC); 1067 1068 if (!dsc) { 1069 BREAK_TO_DEBUGGER(); 1070 return NULL; 1071 } 1072 1073 dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask); 1074 return &dsc->base; 1075} 1076 1077void dcn20_dsc_destroy(struct display_stream_compressor **dsc) 1078{ 1079 kfree(container_of(*dsc, struct dcn20_dsc, base)); 1080 *dsc = NULL; 1081} 1082 1083 1084static void dcn20_resource_destruct(struct dcn20_resource_pool *pool) 1085{ 1086 unsigned int i; 1087 1088 for (i = 0; i < pool->base.stream_enc_count; i++) { 1089 if (pool->base.stream_enc[i] != NULL) { 1090 kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i])); 1091 pool->base.stream_enc[i] = NULL; 1092 } 1093 } 1094 1095 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { 1096 if (pool->base.dscs[i] != NULL) 1097 dcn20_dsc_destroy(&pool->base.dscs[i]); 1098 } 1099 1100 if (pool->base.mpc != NULL) { 1101 kfree(TO_DCN20_MPC(pool->base.mpc)); 1102 pool->base.mpc = NULL; 1103 } 1104 if (pool->base.hubbub != NULL) { 1105 kfree(pool->base.hubbub); 1106 pool->base.hubbub = NULL; 1107 } 1108 for (i = 0; i < pool->base.pipe_count; i++) { 1109 if (pool->base.dpps[i] != NULL) 1110 dcn20_dpp_destroy(&pool->base.dpps[i]); 1111 1112 if (pool->base.ipps[i] != NULL) 1113 pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]); 1114 1115 if (pool->base.hubps[i] != NULL) { 1116 kfree(TO_DCN20_HUBP(pool->base.hubps[i])); 1117 pool->base.hubps[i] = NULL; 1118 } 1119 1120 if (pool->base.irqs != NULL) { 1121 dal_irq_service_destroy(&pool->base.irqs); 1122 } 1123 } 1124 1125 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 1126 if (pool->base.engines[i] != NULL) 1127 dce110_engine_destroy(&pool->base.engines[i]); 1128 if (pool->base.hw_i2cs[i] != NULL) { 1129 kfree(pool->base.hw_i2cs[i]); 1130 pool->base.hw_i2cs[i] = NULL; 1131 } 1132 if (pool->base.sw_i2cs[i] != NULL) { 1133 kfree(pool->base.sw_i2cs[i]); 1134 pool->base.sw_i2cs[i] = NULL; 1135 } 1136 } 1137 1138 for (i = 0; i < pool->base.res_cap->num_opp; i++) { 1139 if (pool->base.opps[i] != NULL) 1140 pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]); 1141 } 1142 1143 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { 1144 if (pool->base.timing_generators[i] != NULL) { 1145 kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i])); 1146 pool->base.timing_generators[i] = NULL; 1147 } 1148 } 1149 1150 for (i = 0; i < pool->base.res_cap->num_dwb; i++) { 1151 if (pool->base.dwbc[i] != NULL) { 1152 kfree(TO_DCN20_DWBC(pool->base.dwbc[i])); 1153 pool->base.dwbc[i] = NULL; 1154 } 1155 if (pool->base.mcif_wb[i] != NULL) { 1156 kfree(TO_DCN20_MMHUBBUB(pool->base.mcif_wb[i])); 1157 pool->base.mcif_wb[i] = NULL; 1158 } 1159 } 1160 1161 for (i = 0; i < pool->base.audio_count; i++) { 1162 if (pool->base.audios[i]) 1163 dce_aud_destroy(&pool->base.audios[i]); 1164 } 1165 1166 for (i = 0; i < pool->base.clk_src_count; i++) { 1167 if (pool->base.clock_sources[i] != NULL) { 1168 dcn20_clock_source_destroy(&pool->base.clock_sources[i]); 1169 pool->base.clock_sources[i] = NULL; 1170 } 1171 } 1172 1173 if (pool->base.dp_clock_source != NULL) { 1174 dcn20_clock_source_destroy(&pool->base.dp_clock_source); 1175 pool->base.dp_clock_source = NULL; 1176 } 1177 1178 1179 if (pool->base.abm != NULL) 1180 dce_abm_destroy(&pool->base.abm); 1181 1182 if (pool->base.dmcu != NULL) 1183 dce_dmcu_destroy(&pool->base.dmcu); 1184 1185 if (pool->base.dccg != NULL) 1186 dcn_dccg_destroy(&pool->base.dccg); 1187 1188 if (pool->base.pp_smu != NULL) 1189 dcn20_pp_smu_destroy(&pool->base.pp_smu); 1190 1191 if (pool->base.oem_device != NULL) { 1192 struct dc *dc = pool->base.oem_device->ctx->dc; 1193 1194 dc->link_srv->destroy_ddc_service(&pool->base.oem_device); 1195 } 1196} 1197 1198struct hubp *dcn20_hubp_create( 1199 struct dc_context *ctx, 1200 uint32_t inst) 1201{ 1202 struct dcn20_hubp *hubp2 = 1203 kzalloc(sizeof(struct dcn20_hubp), GFP_ATOMIC); 1204 1205 if (!hubp2) 1206 return NULL; 1207 1208 if (hubp2_construct(hubp2, ctx, inst, 1209 &hubp_regs[inst], &hubp_shift, &hubp_mask)) 1210 return &hubp2->base; 1211 1212 BREAK_TO_DEBUGGER(); 1213 kfree(hubp2); 1214 return NULL; 1215} 1216 1217static void get_pixel_clock_parameters( 1218 struct pipe_ctx *pipe_ctx, 1219 struct pixel_clk_params *pixel_clk_params) 1220{ 1221 const struct dc_stream_state *stream = pipe_ctx->stream; 1222 struct pipe_ctx *odm_pipe; 1223 int opp_cnt = 1; 1224 struct dc_link *link = stream->link; 1225 struct link_encoder *link_enc = NULL; 1226 struct dc *dc = pipe_ctx->stream->ctx->dc; 1227 struct dce_hwseq *hws = dc->hwseq; 1228 1229 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) 1230 opp_cnt++; 1231 1232 pixel_clk_params->requested_pix_clk_100hz = stream->timing.pix_clk_100hz; 1233 1234 link_enc = link_enc_cfg_get_link_enc(link); 1235 if (link_enc) 1236 pixel_clk_params->encoder_object_id = link_enc->id; 1237 1238 pixel_clk_params->signal_type = pipe_ctx->stream->signal; 1239 pixel_clk_params->controller_id = pipe_ctx->stream_res.tg->inst + 1; 1240 /* TODO: un-hardcode*/ 1241 /* TODO - DP2.0 HW: calculate requested_sym_clk for UHBR rates */ 1242 pixel_clk_params->requested_sym_clk = LINK_RATE_LOW * 1243 LINK_RATE_REF_FREQ_IN_KHZ; 1244 pixel_clk_params->flags.ENABLE_SS = 0; 1245 pixel_clk_params->color_depth = 1246 stream->timing.display_color_depth; 1247 pixel_clk_params->flags.DISPLAY_BLANKED = 1; 1248 pixel_clk_params->pixel_encoding = stream->timing.pixel_encoding; 1249 1250 if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR422) 1251 pixel_clk_params->color_depth = COLOR_DEPTH_888; 1252 1253 if (opp_cnt == 4) 1254 pixel_clk_params->requested_pix_clk_100hz /= 4; 1255 else if (optc2_is_two_pixels_per_containter(&stream->timing) || opp_cnt == 2) 1256 pixel_clk_params->requested_pix_clk_100hz /= 2; 1257 else if (hws->funcs.is_dp_dig_pixel_rate_div_policy) { 1258 if (hws->funcs.is_dp_dig_pixel_rate_div_policy(pipe_ctx)) 1259 pixel_clk_params->requested_pix_clk_100hz /= 2; 1260 } 1261 1262 if (stream->timing.timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING) 1263 pixel_clk_params->requested_pix_clk_100hz *= 2; 1264 1265} 1266 1267static void build_clamping_params(struct dc_stream_state *stream) 1268{ 1269 stream->clamping.clamping_level = CLAMPING_FULL_RANGE; 1270 stream->clamping.c_depth = stream->timing.display_color_depth; 1271 stream->clamping.pixel_encoding = stream->timing.pixel_encoding; 1272} 1273 1274void dcn20_build_pipe_pix_clk_params(struct pipe_ctx *pipe_ctx) 1275{ 1276 get_pixel_clock_parameters(pipe_ctx, &pipe_ctx->stream_res.pix_clk_params); 1277 pipe_ctx->clock_source->funcs->get_pix_clk_dividers( 1278 pipe_ctx->clock_source, 1279 &pipe_ctx->stream_res.pix_clk_params, 1280 &pipe_ctx->pll_settings); 1281} 1282 1283static enum dc_status build_pipe_hw_param(struct pipe_ctx *pipe_ctx) 1284{ 1285 1286 dcn20_build_pipe_pix_clk_params(pipe_ctx); 1287 1288 pipe_ctx->stream->clamping.pixel_encoding = pipe_ctx->stream->timing.pixel_encoding; 1289 1290 resource_build_bit_depth_reduction_params(pipe_ctx->stream, 1291 &pipe_ctx->stream->bit_depth_params); 1292 build_clamping_params(pipe_ctx->stream); 1293 1294 return DC_OK; 1295} 1296 1297enum dc_status dcn20_build_mapped_resource(const struct dc *dc, struct dc_state *context, struct dc_stream_state *stream) 1298{ 1299 enum dc_status status = DC_OK; 1300 struct pipe_ctx *pipe_ctx = resource_get_otg_master_for_stream(&context->res_ctx, stream); 1301 1302 if (!pipe_ctx) 1303 return DC_ERROR_UNEXPECTED; 1304 1305 1306 status = build_pipe_hw_param(pipe_ctx); 1307 1308 return status; 1309} 1310 1311 1312void dcn20_acquire_dsc(const struct dc *dc, 1313 struct resource_context *res_ctx, 1314 struct display_stream_compressor **dsc, 1315 int pipe_idx) 1316{ 1317 int i; 1318 const struct resource_pool *pool = dc->res_pool; 1319 struct display_stream_compressor *dsc_old = dc->current_state->res_ctx.pipe_ctx[pipe_idx].stream_res.dsc; 1320 1321 ASSERT(*dsc == NULL); /* If this ASSERT fails, dsc was not released properly */ 1322 *dsc = NULL; 1323 1324 /* Always do 1-to-1 mapping when number of DSCs is same as number of pipes */ 1325 if (pool->res_cap->num_dsc == pool->res_cap->num_opp) { 1326 *dsc = pool->dscs[pipe_idx]; 1327 res_ctx->is_dsc_acquired[pipe_idx] = true; 1328 return; 1329 } 1330 1331 /* Return old DSC to avoid the need for re-programming */ 1332 if (dsc_old && !res_ctx->is_dsc_acquired[dsc_old->inst]) { 1333 *dsc = dsc_old; 1334 res_ctx->is_dsc_acquired[dsc_old->inst] = true; 1335 return ; 1336 } 1337 1338 /* Find first free DSC */ 1339 for (i = 0; i < pool->res_cap->num_dsc; i++) 1340 if (!res_ctx->is_dsc_acquired[i]) { 1341 *dsc = pool->dscs[i]; 1342 res_ctx->is_dsc_acquired[i] = true; 1343 break; 1344 } 1345} 1346 1347void dcn20_release_dsc(struct resource_context *res_ctx, 1348 const struct resource_pool *pool, 1349 struct display_stream_compressor **dsc) 1350{ 1351 int i; 1352 1353 for (i = 0; i < pool->res_cap->num_dsc; i++) 1354 if (pool->dscs[i] == *dsc) { 1355 res_ctx->is_dsc_acquired[i] = false; 1356 *dsc = NULL; 1357 break; 1358 } 1359} 1360 1361 1362 1363enum dc_status dcn20_add_dsc_to_stream_resource(struct dc *dc, 1364 struct dc_state *dc_ctx, 1365 struct dc_stream_state *dc_stream) 1366{ 1367 enum dc_status result = DC_OK; 1368 int i; 1369 1370 /* Get a DSC if required and available */ 1371 for (i = 0; i < dc->res_pool->pipe_count; i++) { 1372 struct pipe_ctx *pipe_ctx = &dc_ctx->res_ctx.pipe_ctx[i]; 1373 1374 if (pipe_ctx->top_pipe) 1375 continue; 1376 1377 if (pipe_ctx->stream != dc_stream) 1378 continue; 1379 1380 if (pipe_ctx->stream_res.dsc) 1381 continue; 1382 1383 dcn20_acquire_dsc(dc, &dc_ctx->res_ctx, &pipe_ctx->stream_res.dsc, i); 1384 1385 /* The number of DSCs can be less than the number of pipes */ 1386 if (!pipe_ctx->stream_res.dsc) { 1387 result = DC_NO_DSC_RESOURCE; 1388 } 1389 1390 break; 1391 } 1392 1393 return result; 1394} 1395 1396 1397static enum dc_status remove_dsc_from_stream_resource(struct dc *dc, 1398 struct dc_state *new_ctx, 1399 struct dc_stream_state *dc_stream) 1400{ 1401 struct pipe_ctx *pipe_ctx = NULL; 1402 int i; 1403 1404 for (i = 0; i < MAX_PIPES; i++) { 1405 if (new_ctx->res_ctx.pipe_ctx[i].stream == dc_stream && !new_ctx->res_ctx.pipe_ctx[i].top_pipe) { 1406 pipe_ctx = &new_ctx->res_ctx.pipe_ctx[i]; 1407 1408 if (pipe_ctx->stream_res.dsc) 1409 dcn20_release_dsc(&new_ctx->res_ctx, dc->res_pool, &pipe_ctx->stream_res.dsc); 1410 } 1411 } 1412 1413 if (!pipe_ctx) 1414 return DC_ERROR_UNEXPECTED; 1415 else 1416 return DC_OK; 1417} 1418 1419 1420enum dc_status dcn20_add_stream_to_ctx(struct dc *dc, struct dc_state *new_ctx, struct dc_stream_state *dc_stream) 1421{ 1422 enum dc_status result = DC_ERROR_UNEXPECTED; 1423 1424 result = resource_map_pool_resources(dc, new_ctx, dc_stream); 1425 1426 if (result == DC_OK) 1427 result = resource_map_phy_clock_resources(dc, new_ctx, dc_stream); 1428 1429 /* Get a DSC if required and available */ 1430 if (result == DC_OK && dc_stream->timing.flags.DSC) 1431 result = dcn20_add_dsc_to_stream_resource(dc, new_ctx, dc_stream); 1432 1433 if (result == DC_OK) 1434 result = dcn20_build_mapped_resource(dc, new_ctx, dc_stream); 1435 1436 return result; 1437} 1438 1439 1440enum dc_status dcn20_remove_stream_from_ctx(struct dc *dc, struct dc_state *new_ctx, struct dc_stream_state *dc_stream) 1441{ 1442 enum dc_status result = DC_OK; 1443 1444 result = remove_dsc_from_stream_resource(dc, new_ctx, dc_stream); 1445 1446 return result; 1447} 1448 1449/** 1450 * dcn20_split_stream_for_odm - Check if stream can be splited for ODM 1451 * 1452 * @dc: DC object with resource pool info required for pipe split 1453 * @res_ctx: Persistent state of resources 1454 * @prev_odm_pipe: Reference to the previous ODM pipe 1455 * @next_odm_pipe: Reference to the next ODM pipe 1456 * 1457 * This function takes a logically active pipe and a logically free pipe and 1458 * halves all the scaling parameters that need to be halved while populating 1459 * the free pipe with the required resources and configuring the next/previous 1460 * ODM pipe pointers. 1461 * 1462 * Return: 1463 * Return true if split stream for ODM is possible, otherwise, return false. 1464 */ 1465bool dcn20_split_stream_for_odm( 1466 const struct dc *dc, 1467 struct resource_context *res_ctx, 1468 struct pipe_ctx *prev_odm_pipe, 1469 struct pipe_ctx *next_odm_pipe) 1470{ 1471 int pipe_idx = next_odm_pipe->pipe_idx; 1472 const struct resource_pool *pool = dc->res_pool; 1473 1474 *next_odm_pipe = *prev_odm_pipe; 1475 1476 next_odm_pipe->pipe_idx = pipe_idx; 1477 next_odm_pipe->plane_res.mi = pool->mis[next_odm_pipe->pipe_idx]; 1478 next_odm_pipe->plane_res.hubp = pool->hubps[next_odm_pipe->pipe_idx]; 1479 next_odm_pipe->plane_res.ipp = pool->ipps[next_odm_pipe->pipe_idx]; 1480 next_odm_pipe->plane_res.xfm = pool->transforms[next_odm_pipe->pipe_idx]; 1481 next_odm_pipe->plane_res.dpp = pool->dpps[next_odm_pipe->pipe_idx]; 1482 next_odm_pipe->plane_res.mpcc_inst = pool->dpps[next_odm_pipe->pipe_idx]->inst; 1483 next_odm_pipe->stream_res.dsc = NULL; 1484 if (prev_odm_pipe->next_odm_pipe && prev_odm_pipe->next_odm_pipe != next_odm_pipe) { 1485 next_odm_pipe->next_odm_pipe = prev_odm_pipe->next_odm_pipe; 1486 next_odm_pipe->next_odm_pipe->prev_odm_pipe = next_odm_pipe; 1487 } 1488 if (prev_odm_pipe->top_pipe && prev_odm_pipe->top_pipe->next_odm_pipe) { 1489 prev_odm_pipe->top_pipe->next_odm_pipe->bottom_pipe = next_odm_pipe; 1490 next_odm_pipe->top_pipe = prev_odm_pipe->top_pipe->next_odm_pipe; 1491 } 1492 if (prev_odm_pipe->bottom_pipe && prev_odm_pipe->bottom_pipe->next_odm_pipe) { 1493 prev_odm_pipe->bottom_pipe->next_odm_pipe->top_pipe = next_odm_pipe; 1494 next_odm_pipe->bottom_pipe = prev_odm_pipe->bottom_pipe->next_odm_pipe; 1495 } 1496 prev_odm_pipe->next_odm_pipe = next_odm_pipe; 1497 next_odm_pipe->prev_odm_pipe = prev_odm_pipe; 1498 1499 if (prev_odm_pipe->plane_state) { 1500 struct scaler_data *sd = &prev_odm_pipe->plane_res.scl_data; 1501 int new_width; 1502 1503 /* HACTIVE halved for odm combine */ 1504 sd->h_active /= 2; 1505 /* Calculate new vp and recout for left pipe */ 1506 /* Need at least 16 pixels width per side */ 1507 if (sd->recout.x + 16 >= sd->h_active) 1508 return false; 1509 new_width = sd->h_active - sd->recout.x; 1510 sd->viewport.width -= dc_fixpt_floor(dc_fixpt_mul_int( 1511 sd->ratios.horz, sd->recout.width - new_width)); 1512 sd->viewport_c.width -= dc_fixpt_floor(dc_fixpt_mul_int( 1513 sd->ratios.horz_c, sd->recout.width - new_width)); 1514 sd->recout.width = new_width; 1515 1516 /* Calculate new vp and recout for right pipe */ 1517 sd = &next_odm_pipe->plane_res.scl_data; 1518 /* HACTIVE halved for odm combine */ 1519 sd->h_active /= 2; 1520 /* Need at least 16 pixels width per side */ 1521 if (new_width <= 16) 1522 return false; 1523 new_width = sd->recout.width + sd->recout.x - sd->h_active; 1524 sd->viewport.width -= dc_fixpt_floor(dc_fixpt_mul_int( 1525 sd->ratios.horz, sd->recout.width - new_width)); 1526 sd->viewport_c.width -= dc_fixpt_floor(dc_fixpt_mul_int( 1527 sd->ratios.horz_c, sd->recout.width - new_width)); 1528 sd->recout.width = new_width; 1529 sd->viewport.x += dc_fixpt_floor(dc_fixpt_mul_int( 1530 sd->ratios.horz, sd->h_active - sd->recout.x)); 1531 sd->viewport_c.x += dc_fixpt_floor(dc_fixpt_mul_int( 1532 sd->ratios.horz_c, sd->h_active - sd->recout.x)); 1533 sd->recout.x = 0; 1534 } 1535 if (!next_odm_pipe->top_pipe) 1536 next_odm_pipe->stream_res.opp = pool->opps[next_odm_pipe->pipe_idx]; 1537 else 1538 next_odm_pipe->stream_res.opp = next_odm_pipe->top_pipe->stream_res.opp; 1539 if (next_odm_pipe->stream->timing.flags.DSC == 1 && !next_odm_pipe->top_pipe) { 1540 dcn20_acquire_dsc(dc, res_ctx, &next_odm_pipe->stream_res.dsc, next_odm_pipe->pipe_idx); 1541 ASSERT(next_odm_pipe->stream_res.dsc); 1542 if (next_odm_pipe->stream_res.dsc == NULL) 1543 return false; 1544 } 1545 1546 return true; 1547} 1548 1549void dcn20_split_stream_for_mpc( 1550 struct resource_context *res_ctx, 1551 const struct resource_pool *pool, 1552 struct pipe_ctx *primary_pipe, 1553 struct pipe_ctx *secondary_pipe) 1554{ 1555 int pipe_idx = secondary_pipe->pipe_idx; 1556 struct pipe_ctx *sec_bot_pipe = secondary_pipe->bottom_pipe; 1557 1558 *secondary_pipe = *primary_pipe; 1559 secondary_pipe->bottom_pipe = sec_bot_pipe; 1560 1561 secondary_pipe->pipe_idx = pipe_idx; 1562 secondary_pipe->plane_res.mi = pool->mis[secondary_pipe->pipe_idx]; 1563 secondary_pipe->plane_res.hubp = pool->hubps[secondary_pipe->pipe_idx]; 1564 secondary_pipe->plane_res.ipp = pool->ipps[secondary_pipe->pipe_idx]; 1565 secondary_pipe->plane_res.xfm = pool->transforms[secondary_pipe->pipe_idx]; 1566 secondary_pipe->plane_res.dpp = pool->dpps[secondary_pipe->pipe_idx]; 1567 secondary_pipe->plane_res.mpcc_inst = pool->dpps[secondary_pipe->pipe_idx]->inst; 1568 secondary_pipe->stream_res.dsc = NULL; 1569 if (primary_pipe->bottom_pipe && primary_pipe->bottom_pipe != secondary_pipe) { 1570 ASSERT(!secondary_pipe->bottom_pipe); 1571 secondary_pipe->bottom_pipe = primary_pipe->bottom_pipe; 1572 secondary_pipe->bottom_pipe->top_pipe = secondary_pipe; 1573 } 1574 primary_pipe->bottom_pipe = secondary_pipe; 1575 secondary_pipe->top_pipe = primary_pipe; 1576 1577 ASSERT(primary_pipe->plane_state); 1578} 1579 1580unsigned int dcn20_calc_max_scaled_time( 1581 unsigned int time_per_pixel, 1582 enum mmhubbub_wbif_mode mode, 1583 unsigned int urgent_watermark) 1584{ 1585 unsigned int time_per_byte = 0; 1586 unsigned int total_y_free_entry = 0x200; /* two memory piece for luma */ 1587 unsigned int total_c_free_entry = 0x140; /* two memory piece for chroma */ 1588 unsigned int small_free_entry, max_free_entry; 1589 unsigned int buf_lh_capability; 1590 unsigned int max_scaled_time; 1591 1592 if (mode == PACKED_444) /* packed mode */ 1593 time_per_byte = time_per_pixel/4; 1594 else if (mode == PLANAR_420_8BPC) 1595 time_per_byte = time_per_pixel; 1596 else if (mode == PLANAR_420_10BPC) /* p010 */ 1597 time_per_byte = time_per_pixel * 819/1024; 1598 1599 if (time_per_byte == 0) 1600 time_per_byte = 1; 1601 1602 small_free_entry = (total_y_free_entry > total_c_free_entry) ? total_c_free_entry : total_y_free_entry; 1603 max_free_entry = (mode == PACKED_444) ? total_y_free_entry + total_c_free_entry : small_free_entry; 1604 buf_lh_capability = max_free_entry*time_per_byte*32/16; /* there is 4bit fraction */ 1605 max_scaled_time = buf_lh_capability - urgent_watermark; 1606 return max_scaled_time; 1607} 1608 1609void dcn20_set_mcif_arb_params( 1610 struct dc *dc, 1611 struct dc_state *context, 1612 display_e2e_pipe_params_st *pipes, 1613 int pipe_cnt) 1614{ 1615 enum mmhubbub_wbif_mode wbif_mode; 1616 struct mcif_arb_params *wb_arb_params; 1617 int i, j, dwb_pipe; 1618 1619 /* Writeback MCIF_WB arbitration parameters */ 1620 dwb_pipe = 0; 1621 for (i = 0; i < dc->res_pool->pipe_count; i++) { 1622 1623 if (!context->res_ctx.pipe_ctx[i].stream) 1624 continue; 1625 1626 for (j = 0; j < MAX_DWB_PIPES; j++) { 1627 if (context->res_ctx.pipe_ctx[i].stream->writeback_info[j].wb_enabled == false) 1628 continue; 1629 1630 //wb_arb_params = &context->res_ctx.pipe_ctx[i].stream->writeback_info[j].mcif_arb_params; 1631 wb_arb_params = &context->bw_ctx.bw.dcn.bw_writeback.mcif_wb_arb[dwb_pipe]; 1632 1633 if (context->res_ctx.pipe_ctx[i].stream->writeback_info[j].dwb_params.out_format == dwb_scaler_mode_yuv420) { 1634 if (context->res_ctx.pipe_ctx[i].stream->writeback_info[j].dwb_params.output_depth == DWB_OUTPUT_PIXEL_DEPTH_8BPC) 1635 wbif_mode = PLANAR_420_8BPC; 1636 else 1637 wbif_mode = PLANAR_420_10BPC; 1638 } else 1639 wbif_mode = PACKED_444; 1640 1641 DC_FP_START(); 1642 dcn20_fpu_set_wb_arb_params(wb_arb_params, context, pipes, pipe_cnt, i); 1643 DC_FP_END(); 1644 1645 wb_arb_params->slice_lines = 32; 1646 wb_arb_params->arbitration_slice = 2; 1647 wb_arb_params->max_scaled_time = dcn20_calc_max_scaled_time(wb_arb_params->time_per_pixel, 1648 wbif_mode, 1649 wb_arb_params->cli_watermark[0]); /* assume 4 watermark sets have the same value */ 1650 1651 dwb_pipe++; 1652 1653 if (dwb_pipe >= MAX_DWB_PIPES) 1654 return; 1655 } 1656 if (dwb_pipe >= MAX_DWB_PIPES) 1657 return; 1658 } 1659} 1660 1661bool dcn20_validate_dsc(struct dc *dc, struct dc_state *new_ctx) 1662{ 1663 int i; 1664 1665 /* Validate DSC config, dsc count validation is already done */ 1666 for (i = 0; i < dc->res_pool->pipe_count; i++) { 1667 struct pipe_ctx *pipe_ctx = &new_ctx->res_ctx.pipe_ctx[i]; 1668 struct dc_stream_state *stream = pipe_ctx->stream; 1669 struct dsc_config dsc_cfg; 1670 struct pipe_ctx *odm_pipe; 1671 int opp_cnt = 1; 1672 1673 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) 1674 opp_cnt++; 1675 1676 /* Only need to validate top pipe */ 1677 if (pipe_ctx->top_pipe || pipe_ctx->prev_odm_pipe || !stream || !stream->timing.flags.DSC) 1678 continue; 1679 1680 dsc_cfg.pic_width = (stream->timing.h_addressable + stream->timing.h_border_left 1681 + stream->timing.h_border_right) / opp_cnt; 1682 dsc_cfg.pic_height = stream->timing.v_addressable + stream->timing.v_border_top 1683 + stream->timing.v_border_bottom; 1684 dsc_cfg.pixel_encoding = stream->timing.pixel_encoding; 1685 dsc_cfg.color_depth = stream->timing.display_color_depth; 1686 dsc_cfg.is_odm = pipe_ctx->next_odm_pipe ? true : false; 1687 dsc_cfg.dc_dsc_cfg = stream->timing.dsc_cfg; 1688 dsc_cfg.dc_dsc_cfg.num_slices_h /= opp_cnt; 1689 1690 if (!pipe_ctx->stream_res.dsc->funcs->dsc_validate_stream(pipe_ctx->stream_res.dsc, &dsc_cfg)) 1691 return false; 1692 } 1693 return true; 1694} 1695 1696struct pipe_ctx *dcn20_find_secondary_pipe(struct dc *dc, 1697 struct resource_context *res_ctx, 1698 const struct resource_pool *pool, 1699 const struct pipe_ctx *primary_pipe) 1700{ 1701 struct pipe_ctx *secondary_pipe = NULL; 1702 1703 if (dc && primary_pipe) { 1704 int j; 1705 int preferred_pipe_idx = 0; 1706 1707 /* first check the prev dc state: 1708 * if this primary pipe has a bottom pipe in prev. state 1709 * and if the bottom pipe is still available (which it should be), 1710 * pick that pipe as secondary 1711 * Same logic applies for ODM pipes 1712 */ 1713 if (dc->current_state->res_ctx.pipe_ctx[primary_pipe->pipe_idx].next_odm_pipe) { 1714 preferred_pipe_idx = dc->current_state->res_ctx.pipe_ctx[primary_pipe->pipe_idx].next_odm_pipe->pipe_idx; 1715 if (res_ctx->pipe_ctx[preferred_pipe_idx].stream == NULL) { 1716 secondary_pipe = &res_ctx->pipe_ctx[preferred_pipe_idx]; 1717 secondary_pipe->pipe_idx = preferred_pipe_idx; 1718 } 1719 } 1720 if (secondary_pipe == NULL && 1721 dc->current_state->res_ctx.pipe_ctx[primary_pipe->pipe_idx].bottom_pipe) { 1722 preferred_pipe_idx = dc->current_state->res_ctx.pipe_ctx[primary_pipe->pipe_idx].bottom_pipe->pipe_idx; 1723 if (res_ctx->pipe_ctx[preferred_pipe_idx].stream == NULL) { 1724 secondary_pipe = &res_ctx->pipe_ctx[preferred_pipe_idx]; 1725 secondary_pipe->pipe_idx = preferred_pipe_idx; 1726 } 1727 } 1728 1729 /* 1730 * if this primary pipe does not have a bottom pipe in prev. state 1731 * start backward and find a pipe that did not used to be a bottom pipe in 1732 * prev. dc state. This way we make sure we keep the same assignment as 1733 * last state and will not have to reprogram every pipe 1734 */ 1735 if (secondary_pipe == NULL) { 1736 for (j = dc->res_pool->pipe_count - 1; j >= 0; j--) { 1737 if (dc->current_state->res_ctx.pipe_ctx[j].top_pipe == NULL 1738 && dc->current_state->res_ctx.pipe_ctx[j].prev_odm_pipe == NULL) { 1739 preferred_pipe_idx = j; 1740 1741 if (res_ctx->pipe_ctx[preferred_pipe_idx].stream == NULL) { 1742 secondary_pipe = &res_ctx->pipe_ctx[preferred_pipe_idx]; 1743 secondary_pipe->pipe_idx = preferred_pipe_idx; 1744 break; 1745 } 1746 } 1747 } 1748 } 1749 /* 1750 * We should never hit this assert unless assignments are shuffled around 1751 * if this happens we will prob. hit a vsync tdr 1752 */ 1753 ASSERT(secondary_pipe); 1754 /* 1755 * search backwards for the second pipe to keep pipe 1756 * assignment more consistent 1757 */ 1758 if (secondary_pipe == NULL) { 1759 for (j = dc->res_pool->pipe_count - 1; j >= 0; j--) { 1760 preferred_pipe_idx = j; 1761 1762 if (res_ctx->pipe_ctx[preferred_pipe_idx].stream == NULL) { 1763 secondary_pipe = &res_ctx->pipe_ctx[preferred_pipe_idx]; 1764 secondary_pipe->pipe_idx = preferred_pipe_idx; 1765 break; 1766 } 1767 } 1768 } 1769 } 1770 1771 return secondary_pipe; 1772} 1773 1774void dcn20_merge_pipes_for_validate( 1775 struct dc *dc, 1776 struct dc_state *context) 1777{ 1778 int i; 1779 1780 /* merge previously split odm pipes since mode support needs to make the decision */ 1781 for (i = 0; i < dc->res_pool->pipe_count; i++) { 1782 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 1783 struct pipe_ctx *odm_pipe = pipe->next_odm_pipe; 1784 1785 if (pipe->prev_odm_pipe) 1786 continue; 1787 1788 pipe->next_odm_pipe = NULL; 1789 while (odm_pipe) { 1790 struct pipe_ctx *next_odm_pipe = odm_pipe->next_odm_pipe; 1791 1792 odm_pipe->plane_state = NULL; 1793 odm_pipe->stream = NULL; 1794 odm_pipe->top_pipe = NULL; 1795 odm_pipe->bottom_pipe = NULL; 1796 odm_pipe->prev_odm_pipe = NULL; 1797 odm_pipe->next_odm_pipe = NULL; 1798 if (odm_pipe->stream_res.dsc) 1799 dcn20_release_dsc(&context->res_ctx, dc->res_pool, &odm_pipe->stream_res.dsc); 1800 /* Clear plane_res and stream_res */ 1801 memset(&odm_pipe->plane_res, 0, sizeof(odm_pipe->plane_res)); 1802 memset(&odm_pipe->stream_res, 0, sizeof(odm_pipe->stream_res)); 1803 odm_pipe = next_odm_pipe; 1804 } 1805 if (pipe->plane_state) 1806 resource_build_scaling_params(pipe); 1807 } 1808 1809 /* merge previously mpc split pipes since mode support needs to make the decision */ 1810 for (i = 0; i < dc->res_pool->pipe_count; i++) { 1811 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 1812 struct pipe_ctx *hsplit_pipe = pipe->bottom_pipe; 1813 1814 if (!hsplit_pipe || hsplit_pipe->plane_state != pipe->plane_state) 1815 continue; 1816 1817 pipe->bottom_pipe = hsplit_pipe->bottom_pipe; 1818 if (hsplit_pipe->bottom_pipe) 1819 hsplit_pipe->bottom_pipe->top_pipe = pipe; 1820 hsplit_pipe->plane_state = NULL; 1821 hsplit_pipe->stream = NULL; 1822 hsplit_pipe->top_pipe = NULL; 1823 hsplit_pipe->bottom_pipe = NULL; 1824 1825 /* Clear plane_res and stream_res */ 1826 memset(&hsplit_pipe->plane_res, 0, sizeof(hsplit_pipe->plane_res)); 1827 memset(&hsplit_pipe->stream_res, 0, sizeof(hsplit_pipe->stream_res)); 1828 if (pipe->plane_state) 1829 resource_build_scaling_params(pipe); 1830 } 1831} 1832 1833int dcn20_validate_apply_pipe_split_flags( 1834 struct dc *dc, 1835 struct dc_state *context, 1836 int vlevel, 1837 int *split, 1838 bool *merge) 1839{ 1840 int i, pipe_idx, vlevel_split; 1841 int plane_count = 0; 1842 bool force_split = false; 1843 bool avoid_split = dc->debug.pipe_split_policy == MPC_SPLIT_AVOID; 1844 struct vba_vars_st *v = &context->bw_ctx.dml.vba; 1845 int max_mpc_comb = v->maxMpcComb; 1846 1847 if (context->stream_count > 1) { 1848 if (dc->debug.pipe_split_policy == MPC_SPLIT_AVOID_MULT_DISP) 1849 avoid_split = true; 1850 } else if (dc->debug.force_single_disp_pipe_split) 1851 force_split = true; 1852 1853 for (i = 0; i < dc->res_pool->pipe_count; i++) { 1854 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 1855 1856 /** 1857 * Workaround for avoiding pipe-split in cases where we'd split 1858 * planes that are too small, resulting in splits that aren't 1859 * valid for the scaler. 1860 */ 1861 if (pipe->plane_state && 1862 (pipe->plane_state->dst_rect.width <= 16 || 1863 pipe->plane_state->dst_rect.height <= 16 || 1864 pipe->plane_state->src_rect.width <= 16 || 1865 pipe->plane_state->src_rect.height <= 16)) 1866 avoid_split = true; 1867 1868 /* TODO: fix dc bugs and remove this split threshold thing */ 1869 if (pipe->stream && !pipe->prev_odm_pipe && 1870 (!pipe->top_pipe || pipe->top_pipe->plane_state != pipe->plane_state)) 1871 ++plane_count; 1872 } 1873 if (plane_count > dc->res_pool->pipe_count / 2) 1874 avoid_split = true; 1875 1876 /* W/A: Mode timing with borders may not work well with pipe split, avoid for this corner case */ 1877 for (i = 0; i < dc->res_pool->pipe_count; i++) { 1878 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 1879 struct dc_crtc_timing timing; 1880 1881 if (!pipe->stream) 1882 continue; 1883 else { 1884 timing = pipe->stream->timing; 1885 if (timing.h_border_left + timing.h_border_right 1886 + timing.v_border_top + timing.v_border_bottom > 0) { 1887 avoid_split = true; 1888 break; 1889 } 1890 } 1891 } 1892 1893 /* Avoid split loop looks for lowest voltage level that allows most unsplit pipes possible */ 1894 if (avoid_split) { 1895 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { 1896 if (!context->res_ctx.pipe_ctx[i].stream) 1897 continue; 1898 1899 for (vlevel_split = vlevel; vlevel <= context->bw_ctx.dml.soc.num_states; vlevel++) 1900 if (v->NoOfDPP[vlevel][0][pipe_idx] == 1 && 1901 v->ModeSupport[vlevel][0]) 1902 break; 1903 /* Impossible to not split this pipe */ 1904 if (vlevel > context->bw_ctx.dml.soc.num_states) 1905 vlevel = vlevel_split; 1906 else 1907 max_mpc_comb = 0; 1908 pipe_idx++; 1909 } 1910 v->maxMpcComb = max_mpc_comb; 1911 } 1912 1913 /* Split loop sets which pipe should be split based on dml outputs and dc flags */ 1914 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) { 1915 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 1916 int pipe_plane = v->pipe_plane[pipe_idx]; 1917 bool split4mpc = context->stream_count == 1 && plane_count == 1 1918 && dc->config.enable_4to1MPC && dc->res_pool->pipe_count >= 4; 1919 1920 if (!context->res_ctx.pipe_ctx[i].stream) 1921 continue; 1922 1923 if (split4mpc || v->NoOfDPP[vlevel][max_mpc_comb][pipe_plane] == 4) 1924 split[i] = 4; 1925 else if (force_split || v->NoOfDPP[vlevel][max_mpc_comb][pipe_plane] == 2) 1926 split[i] = 2; 1927 1928 if ((pipe->stream->view_format == 1929 VIEW_3D_FORMAT_SIDE_BY_SIDE || 1930 pipe->stream->view_format == 1931 VIEW_3D_FORMAT_TOP_AND_BOTTOM) && 1932 (pipe->stream->timing.timing_3d_format == 1933 TIMING_3D_FORMAT_TOP_AND_BOTTOM || 1934 pipe->stream->timing.timing_3d_format == 1935 TIMING_3D_FORMAT_SIDE_BY_SIDE)) 1936 split[i] = 2; 1937 if (dc->debug.force_odm_combine & (1 << pipe->stream_res.tg->inst)) { 1938 split[i] = 2; 1939 v->ODMCombineEnablePerState[vlevel][pipe_plane] = dm_odm_combine_mode_2to1; 1940 } 1941 if (dc->debug.force_odm_combine_4to1 & (1 << pipe->stream_res.tg->inst)) { 1942 split[i] = 4; 1943 v->ODMCombineEnablePerState[vlevel][pipe_plane] = dm_odm_combine_mode_4to1; 1944 } 1945 /*420 format workaround*/ 1946 if (pipe->stream->timing.h_addressable > 7680 && 1947 pipe->stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420) { 1948 split[i] = 4; 1949 } 1950 v->ODMCombineEnabled[pipe_plane] = 1951 v->ODMCombineEnablePerState[vlevel][pipe_plane]; 1952 1953 if (v->ODMCombineEnabled[pipe_plane] == dm_odm_combine_mode_disabled) { 1954 if (resource_get_mpc_slice_count(pipe) == 2) { 1955 /*If need split for mpc but 2 way split already*/ 1956 if (split[i] == 4) 1957 split[i] = 2; /* 2 -> 4 MPC */ 1958 else if (split[i] == 2) 1959 split[i] = 0; /* 2 -> 2 MPC */ 1960 else if (pipe->top_pipe && pipe->top_pipe->plane_state == pipe->plane_state) 1961 merge[i] = true; /* 2 -> 1 MPC */ 1962 } else if (resource_get_mpc_slice_count(pipe) == 4) { 1963 /*If need split for mpc but 4 way split already*/ 1964 if (split[i] == 2 && ((pipe->top_pipe && !pipe->top_pipe->top_pipe) 1965 || !pipe->bottom_pipe)) { 1966 merge[i] = true; /* 4 -> 2 MPC */ 1967 } else if (split[i] == 0 && pipe->top_pipe && 1968 pipe->top_pipe->plane_state == pipe->plane_state) 1969 merge[i] = true; /* 4 -> 1 MPC */ 1970 split[i] = 0; 1971 } else if (resource_get_odm_slice_count(pipe) > 1) { 1972 /* ODM -> MPC transition */ 1973 if (pipe->prev_odm_pipe) { 1974 split[i] = 0; 1975 merge[i] = true; 1976 } 1977 } 1978 } else { 1979 if (resource_get_odm_slice_count(pipe) == 2) { 1980 /*If need split for odm but 2 way split already*/ 1981 if (split[i] == 4) 1982 split[i] = 2; /* 2 -> 4 ODM */ 1983 else if (split[i] == 2) 1984 split[i] = 0; /* 2 -> 2 ODM */ 1985 else if (pipe->prev_odm_pipe) { 1986 ASSERT(0); /* NOT expected yet */ 1987 merge[i] = true; /* exit ODM */ 1988 } 1989 } else if (resource_get_odm_slice_count(pipe) == 4) { 1990 /*If need split for odm but 4 way split already*/ 1991 if (split[i] == 2 && ((pipe->prev_odm_pipe && !pipe->prev_odm_pipe->prev_odm_pipe) 1992 || !pipe->next_odm_pipe)) { 1993 merge[i] = true; /* 4 -> 2 ODM */ 1994 } else if (split[i] == 0 && pipe->prev_odm_pipe) { 1995 ASSERT(0); /* NOT expected yet */ 1996 merge[i] = true; /* exit ODM */ 1997 } 1998 split[i] = 0; 1999 } else if (resource_get_mpc_slice_count(pipe) > 1) { 2000 /* MPC -> ODM transition */ 2001 ASSERT(0); /* NOT expected yet */ 2002 if (pipe->top_pipe && pipe->top_pipe->plane_state == pipe->plane_state) { 2003 split[i] = 0; 2004 merge[i] = true; 2005 } 2006 } 2007 } 2008 2009 /* Adjust dppclk when split is forced, do not bother with dispclk */ 2010 if (split[i] != 0 && v->NoOfDPP[vlevel][max_mpc_comb][pipe_idx] == 1) { 2011 DC_FP_START(); 2012 dcn20_fpu_adjust_dppclk(v, vlevel, max_mpc_comb, pipe_idx, false); 2013 DC_FP_END(); 2014 } 2015 pipe_idx++; 2016 } 2017 2018 return vlevel; 2019} 2020 2021bool dcn20_fast_validate_bw( 2022 struct dc *dc, 2023 struct dc_state *context, 2024 display_e2e_pipe_params_st *pipes, 2025 int *pipe_cnt_out, 2026 int *pipe_split_from, 2027 int *vlevel_out, 2028 bool fast_validate) 2029{ 2030 bool out = false; 2031 int split[MAX_PIPES] = { 0 }; 2032 int pipe_cnt, i, pipe_idx, vlevel; 2033 2034 ASSERT(pipes); 2035 if (!pipes) 2036 return false; 2037 2038 dcn20_merge_pipes_for_validate(dc, context); 2039 2040 DC_FP_START(); 2041 pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, context, pipes, fast_validate); 2042 DC_FP_END(); 2043 2044 *pipe_cnt_out = pipe_cnt; 2045 2046 if (!pipe_cnt) { 2047 out = true; 2048 goto validate_out; 2049 } 2050 2051 vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt); 2052 2053 if (vlevel > context->bw_ctx.dml.soc.num_states) 2054 goto validate_fail; 2055 2056 vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, vlevel, split, NULL); 2057 2058 /*initialize pipe_just_split_from to invalid idx*/ 2059 for (i = 0; i < MAX_PIPES; i++) 2060 pipe_split_from[i] = -1; 2061 2062 for (i = 0, pipe_idx = -1; i < dc->res_pool->pipe_count; i++) { 2063 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; 2064 struct pipe_ctx *hsplit_pipe = pipe->bottom_pipe; 2065 2066 if (!pipe->stream || pipe_split_from[i] >= 0) 2067 continue; 2068 2069 pipe_idx++; 2070 2071 if (!pipe->top_pipe && !pipe->plane_state && context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx]) { 2072 hsplit_pipe = dcn20_find_secondary_pipe(dc, &context->res_ctx, dc->res_pool, pipe); 2073 ASSERT(hsplit_pipe); 2074 if (!dcn20_split_stream_for_odm( 2075 dc, &context->res_ctx, 2076 pipe, hsplit_pipe)) 2077 goto validate_fail; 2078 pipe_split_from[hsplit_pipe->pipe_idx] = pipe_idx; 2079 dcn20_build_mapped_resource(dc, context, pipe->stream); 2080 } 2081 2082 if (!pipe->plane_state) 2083 continue; 2084 /* Skip 2nd half of already split pipe */ 2085 if (pipe->top_pipe && pipe->plane_state == pipe->top_pipe->plane_state) 2086 continue; 2087 2088 /* We do not support mpo + odm at the moment */ 2089 if (hsplit_pipe && hsplit_pipe->plane_state != pipe->plane_state 2090 && context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx]) 2091 goto validate_fail; 2092 2093 if (split[i] == 2) { 2094 if (!hsplit_pipe || hsplit_pipe->plane_state != pipe->plane_state) { 2095 /* pipe not split previously needs split */ 2096 hsplit_pipe = dcn20_find_secondary_pipe(dc, &context->res_ctx, dc->res_pool, pipe); 2097 ASSERT(hsplit_pipe); 2098 if (!hsplit_pipe) { 2099 DC_FP_START(); 2100 dcn20_fpu_adjust_dppclk(&context->bw_ctx.dml.vba, vlevel, context->bw_ctx.dml.vba.maxMpcComb, pipe_idx, true); 2101 DC_FP_END(); 2102 continue; 2103 } 2104 if (context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx]) { 2105 if (!dcn20_split_stream_for_odm( 2106 dc, &context->res_ctx, 2107 pipe, hsplit_pipe)) 2108 goto validate_fail; 2109 dcn20_build_mapped_resource(dc, context, pipe->stream); 2110 } else { 2111 dcn20_split_stream_for_mpc( 2112 &context->res_ctx, dc->res_pool, 2113 pipe, hsplit_pipe); 2114 resource_build_scaling_params(pipe); 2115 resource_build_scaling_params(hsplit_pipe); 2116 } 2117 pipe_split_from[hsplit_pipe->pipe_idx] = pipe_idx; 2118 } 2119 } else if (hsplit_pipe && hsplit_pipe->plane_state == pipe->plane_state) { 2120 /* merge should already have been done */ 2121 ASSERT(0); 2122 } 2123 } 2124 /* Actual dsc count per stream dsc validation*/ 2125 if (!dcn20_validate_dsc(dc, context)) { 2126 context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states] = 2127 DML_FAIL_DSC_VALIDATION_FAILURE; 2128 goto validate_fail; 2129 } 2130 2131 *vlevel_out = vlevel; 2132 2133 out = true; 2134 goto validate_out; 2135 2136validate_fail: 2137 out = false; 2138 2139validate_out: 2140 return out; 2141} 2142 2143bool dcn20_validate_bandwidth(struct dc *dc, struct dc_state *context, 2144 bool fast_validate) 2145{ 2146 bool voltage_supported; 2147 display_e2e_pipe_params_st *pipes; 2148 2149 pipes = kcalloc(dc->res_pool->pipe_count, sizeof(display_e2e_pipe_params_st), GFP_KERNEL); 2150 if (!pipes) 2151 return false; 2152 2153 DC_FP_START(); 2154 voltage_supported = dcn20_validate_bandwidth_fp(dc, context, fast_validate, pipes); 2155 DC_FP_END(); 2156 2157 kfree(pipes); 2158 return voltage_supported; 2159} 2160 2161struct pipe_ctx *dcn20_acquire_free_pipe_for_layer( 2162 const struct dc_state *cur_ctx, 2163 struct dc_state *new_ctx, 2164 const struct resource_pool *pool, 2165 const struct pipe_ctx *opp_head) 2166{ 2167 struct resource_context *res_ctx = &new_ctx->res_ctx; 2168 struct pipe_ctx *otg_master = resource_get_otg_master_for_stream(res_ctx, opp_head->stream); 2169 struct pipe_ctx *sec_dpp_pipe = resource_find_free_secondary_pipe_legacy(res_ctx, pool, otg_master); 2170 2171 ASSERT(otg_master); 2172 2173 if (!sec_dpp_pipe) 2174 return NULL; 2175 2176 sec_dpp_pipe->stream = opp_head->stream; 2177 sec_dpp_pipe->stream_res.tg = opp_head->stream_res.tg; 2178 sec_dpp_pipe->stream_res.opp = opp_head->stream_res.opp; 2179 2180 sec_dpp_pipe->plane_res.hubp = pool->hubps[sec_dpp_pipe->pipe_idx]; 2181 sec_dpp_pipe->plane_res.ipp = pool->ipps[sec_dpp_pipe->pipe_idx]; 2182 sec_dpp_pipe->plane_res.dpp = pool->dpps[sec_dpp_pipe->pipe_idx]; 2183 sec_dpp_pipe->plane_res.mpcc_inst = pool->dpps[sec_dpp_pipe->pipe_idx]->inst; 2184 2185 return sec_dpp_pipe; 2186} 2187 2188bool dcn20_get_dcc_compression_cap(const struct dc *dc, 2189 const struct dc_dcc_surface_param *input, 2190 struct dc_surface_dcc_cap *output) 2191{ 2192 return dc->res_pool->hubbub->funcs->get_dcc_compression_cap( 2193 dc->res_pool->hubbub, 2194 input, 2195 output); 2196} 2197 2198static void dcn20_destroy_resource_pool(struct resource_pool **pool) 2199{ 2200 struct dcn20_resource_pool *dcn20_pool = TO_DCN20_RES_POOL(*pool); 2201 2202 dcn20_resource_destruct(dcn20_pool); 2203 kfree(dcn20_pool); 2204 *pool = NULL; 2205} 2206 2207 2208static struct dc_cap_funcs cap_funcs = { 2209 .get_dcc_compression_cap = dcn20_get_dcc_compression_cap 2210}; 2211 2212 2213enum dc_status dcn20_patch_unknown_plane_state(struct dc_plane_state *plane_state) 2214{ 2215 enum surface_pixel_format surf_pix_format = plane_state->format; 2216 unsigned int bpp = resource_pixel_format_to_bpp(surf_pix_format); 2217 2218 plane_state->tiling_info.gfx9.swizzle = DC_SW_64KB_S; 2219 if (bpp == 64) 2220 plane_state->tiling_info.gfx9.swizzle = DC_SW_64KB_D; 2221 2222 return DC_OK; 2223} 2224 2225void dcn20_release_pipe(struct dc_state *context, 2226 struct pipe_ctx *pipe, 2227 const struct resource_pool *pool) 2228{ 2229 if (resource_is_pipe_type(pipe, OPP_HEAD) && pipe->stream_res.dsc) 2230 dcn20_release_dsc(&context->res_ctx, pool, &pipe->stream_res.dsc); 2231 memset(pipe, 0, sizeof(*pipe)); 2232} 2233 2234static const struct resource_funcs dcn20_res_pool_funcs = { 2235 .destroy = dcn20_destroy_resource_pool, 2236 .link_enc_create = dcn20_link_encoder_create, 2237 .panel_cntl_create = dcn20_panel_cntl_create, 2238 .validate_bandwidth = dcn20_validate_bandwidth, 2239 .acquire_free_pipe_as_secondary_dpp_pipe = dcn20_acquire_free_pipe_for_layer, 2240 .release_pipe = dcn20_release_pipe, 2241 .add_stream_to_ctx = dcn20_add_stream_to_ctx, 2242 .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource, 2243 .remove_stream_from_ctx = dcn20_remove_stream_from_ctx, 2244 .populate_dml_writeback_from_context = dcn20_populate_dml_writeback_from_context, 2245 .patch_unknown_plane_state = dcn20_patch_unknown_plane_state, 2246 .set_mcif_arb_params = dcn20_set_mcif_arb_params, 2247 .populate_dml_pipes = dcn20_populate_dml_pipes_from_context, 2248 .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link 2249}; 2250 2251bool dcn20_dwbc_create(struct dc_context *ctx, struct resource_pool *pool) 2252{ 2253 int i; 2254 uint32_t pipe_count = pool->res_cap->num_dwb; 2255 2256 for (i = 0; i < pipe_count; i++) { 2257 struct dcn20_dwbc *dwbc20 = kzalloc(sizeof(struct dcn20_dwbc), 2258 GFP_KERNEL); 2259 2260 if (!dwbc20) { 2261 dm_error("DC: failed to create dwbc20!\n"); 2262 return false; 2263 } 2264 dcn20_dwbc_construct(dwbc20, ctx, 2265 &dwbc20_regs[i], 2266 &dwbc20_shift, 2267 &dwbc20_mask, 2268 i); 2269 pool->dwbc[i] = &dwbc20->base; 2270 } 2271 return true; 2272} 2273 2274bool dcn20_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool) 2275{ 2276 int i; 2277 uint32_t pipe_count = pool->res_cap->num_dwb; 2278 2279 ASSERT(pipe_count > 0); 2280 2281 for (i = 0; i < pipe_count; i++) { 2282 struct dcn20_mmhubbub *mcif_wb20 = kzalloc(sizeof(struct dcn20_mmhubbub), 2283 GFP_KERNEL); 2284 2285 if (!mcif_wb20) { 2286 dm_error("DC: failed to create mcif_wb20!\n"); 2287 return false; 2288 } 2289 2290 dcn20_mmhubbub_construct(mcif_wb20, ctx, 2291 &mcif_wb20_regs[i], 2292 &mcif_wb20_shift, 2293 &mcif_wb20_mask, 2294 i); 2295 2296 pool->mcif_wb[i] = &mcif_wb20->base; 2297 } 2298 return true; 2299} 2300 2301static struct pp_smu_funcs *dcn20_pp_smu_create(struct dc_context *ctx) 2302{ 2303 struct pp_smu_funcs *pp_smu = kzalloc(sizeof(*pp_smu), GFP_ATOMIC); 2304 2305 if (!pp_smu) 2306 return pp_smu; 2307 2308 dm_pp_get_funcs(ctx, pp_smu); 2309 2310 if (pp_smu->ctx.ver != PP_SMU_VER_NV) 2311 pp_smu = memset(pp_smu, 0, sizeof(struct pp_smu_funcs)); 2312 2313 return pp_smu; 2314} 2315 2316static void dcn20_pp_smu_destroy(struct pp_smu_funcs **pp_smu) 2317{ 2318 if (pp_smu && *pp_smu) { 2319 kfree(*pp_smu); 2320 *pp_smu = NULL; 2321 } 2322} 2323 2324static struct _vcs_dpi_soc_bounding_box_st *get_asic_rev_soc_bb( 2325 uint32_t hw_internal_rev) 2326{ 2327 if (ASICREV_IS_NAVI14_M(hw_internal_rev)) 2328 return &dcn2_0_nv14_soc; 2329 2330 if (ASICREV_IS_NAVI12_P(hw_internal_rev)) 2331 return &dcn2_0_nv12_soc; 2332 2333 return &dcn2_0_soc; 2334} 2335 2336static struct _vcs_dpi_ip_params_st *get_asic_rev_ip_params( 2337 uint32_t hw_internal_rev) 2338{ 2339 /* NV14 */ 2340 if (ASICREV_IS_NAVI14_M(hw_internal_rev)) 2341 return &dcn2_0_nv14_ip; 2342 2343 /* NV12 and NV10 */ 2344 return &dcn2_0_ip; 2345} 2346 2347static enum dml_project get_dml_project_version(uint32_t hw_internal_rev) 2348{ 2349 return DML_PROJECT_NAVI10v2; 2350} 2351 2352static bool init_soc_bounding_box(struct dc *dc, 2353 struct dcn20_resource_pool *pool) 2354{ 2355 struct _vcs_dpi_soc_bounding_box_st *loaded_bb = 2356 get_asic_rev_soc_bb(dc->ctx->asic_id.hw_internal_rev); 2357 struct _vcs_dpi_ip_params_st *loaded_ip = 2358 get_asic_rev_ip_params(dc->ctx->asic_id.hw_internal_rev); 2359 2360 DC_LOGGER_INIT(dc->ctx->logger); 2361 2362 if (pool->base.pp_smu) { 2363 struct pp_smu_nv_clock_table max_clocks = {0}; 2364 unsigned int uclk_states[8] = {0}; 2365 unsigned int num_states = 0; 2366 enum pp_smu_status status; 2367 bool clock_limits_available = false; 2368 bool uclk_states_available = false; 2369 2370 if (pool->base.pp_smu->nv_funcs.get_uclk_dpm_states) { 2371 status = (pool->base.pp_smu->nv_funcs.get_uclk_dpm_states) 2372 (&pool->base.pp_smu->nv_funcs.pp_smu, uclk_states, &num_states); 2373 2374 uclk_states_available = (status == PP_SMU_RESULT_OK); 2375 } 2376 2377 if (pool->base.pp_smu->nv_funcs.get_maximum_sustainable_clocks) { 2378 status = (*pool->base.pp_smu->nv_funcs.get_maximum_sustainable_clocks) 2379 (&pool->base.pp_smu->nv_funcs.pp_smu, &max_clocks); 2380 /* SMU cannot set DCF clock to anything equal to or higher than SOC clock 2381 */ 2382 if (max_clocks.dcfClockInKhz >= max_clocks.socClockInKhz) 2383 max_clocks.dcfClockInKhz = max_clocks.socClockInKhz - 1000; 2384 clock_limits_available = (status == PP_SMU_RESULT_OK); 2385 } 2386 2387 if (clock_limits_available && uclk_states_available && num_states) { 2388 DC_FP_START(); 2389 dcn20_update_bounding_box(dc, loaded_bb, &max_clocks, uclk_states, num_states); 2390 DC_FP_END(); 2391 } else if (clock_limits_available) { 2392 DC_FP_START(); 2393 dcn20_cap_soc_clocks(loaded_bb, max_clocks); 2394 DC_FP_END(); 2395 } 2396 } 2397 2398 loaded_ip->max_num_otg = pool->base.res_cap->num_timing_generator; 2399 loaded_ip->max_num_dpp = pool->base.pipe_count; 2400 DC_FP_START(); 2401 dcn20_patch_bounding_box(dc, loaded_bb); 2402 DC_FP_END(); 2403 return true; 2404} 2405 2406static bool dcn20_resource_construct( 2407 uint8_t num_virtual_links, 2408 struct dc *dc, 2409 struct dcn20_resource_pool *pool) 2410{ 2411 int i; 2412 struct dc_context *ctx = dc->ctx; 2413 struct irq_service_init_data init_data; 2414 struct ddc_service_init_data ddc_init_data = {0}; 2415 struct _vcs_dpi_soc_bounding_box_st *loaded_bb = 2416 get_asic_rev_soc_bb(ctx->asic_id.hw_internal_rev); 2417 struct _vcs_dpi_ip_params_st *loaded_ip = 2418 get_asic_rev_ip_params(ctx->asic_id.hw_internal_rev); 2419 enum dml_project dml_project_version = 2420 get_dml_project_version(ctx->asic_id.hw_internal_rev); 2421 2422 ctx->dc_bios->regs = &bios_regs; 2423 pool->base.funcs = &dcn20_res_pool_funcs; 2424 2425 if (ASICREV_IS_NAVI14_M(ctx->asic_id.hw_internal_rev)) { 2426 pool->base.res_cap = &res_cap_nv14; 2427 pool->base.pipe_count = 5; 2428 pool->base.mpcc_count = 5; 2429 } else { 2430 pool->base.res_cap = &res_cap_nv10; 2431 pool->base.pipe_count = 6; 2432 pool->base.mpcc_count = 6; 2433 } 2434 /************************************************* 2435 * Resource + asic cap harcoding * 2436 *************************************************/ 2437 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; 2438 2439 dc->caps.max_downscale_ratio = 200; 2440 dc->caps.i2c_speed_in_khz = 100; 2441 dc->caps.i2c_speed_in_khz_hdcp = 100; /*1.4 w/a not applied by default*/ 2442 dc->caps.max_cursor_size = 256; 2443 dc->caps.min_horizontal_blanking_period = 80; 2444 dc->caps.dmdata_alloc_size = 2048; 2445 2446 dc->caps.max_slave_planes = 1; 2447 dc->caps.max_slave_yuv_planes = 1; 2448 dc->caps.max_slave_rgb_planes = 1; 2449 dc->caps.post_blend_color_processing = true; 2450 dc->caps.force_dp_tps4_for_cp2520 = true; 2451 dc->caps.extended_aux_timeout_support = true; 2452 2453 /* Color pipeline capabilities */ 2454 dc->caps.color.dpp.dcn_arch = 1; 2455 dc->caps.color.dpp.input_lut_shared = 0; 2456 dc->caps.color.dpp.icsc = 1; 2457 dc->caps.color.dpp.dgam_ram = 1; 2458 dc->caps.color.dpp.dgam_rom_caps.srgb = 1; 2459 dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1; 2460 dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 0; 2461 dc->caps.color.dpp.dgam_rom_caps.pq = 0; 2462 dc->caps.color.dpp.dgam_rom_caps.hlg = 0; 2463 dc->caps.color.dpp.post_csc = 0; 2464 dc->caps.color.dpp.gamma_corr = 0; 2465 dc->caps.color.dpp.dgam_rom_for_yuv = 1; 2466 2467 dc->caps.color.dpp.hw_3d_lut = 1; 2468 dc->caps.color.dpp.ogam_ram = 1; 2469 // no OGAM ROM on DCN2, only MPC ROM 2470 dc->caps.color.dpp.ogam_rom_caps.srgb = 0; 2471 dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0; 2472 dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0; 2473 dc->caps.color.dpp.ogam_rom_caps.pq = 0; 2474 dc->caps.color.dpp.ogam_rom_caps.hlg = 0; 2475 dc->caps.color.dpp.ocsc = 0; 2476 2477 dc->caps.color.mpc.gamut_remap = 0; 2478 dc->caps.color.mpc.num_3dluts = 0; 2479 dc->caps.color.mpc.shared_3d_lut = 0; 2480 dc->caps.color.mpc.ogam_ram = 1; 2481 dc->caps.color.mpc.ogam_rom_caps.srgb = 0; 2482 dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0; 2483 dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0; 2484 dc->caps.color.mpc.ogam_rom_caps.pq = 0; 2485 dc->caps.color.mpc.ogam_rom_caps.hlg = 0; 2486 dc->caps.color.mpc.ocsc = 1; 2487 2488 dc->caps.dp_hdmi21_pcon_support = true; 2489 2490 if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV) 2491 dc->debug = debug_defaults_drv; 2492 2493 //dcn2.0x 2494 dc->work_arounds.dedcn20_305_wa = true; 2495 2496 // Init the vm_helper 2497 if (dc->vm_helper) 2498 vm_helper_init(dc->vm_helper, 16); 2499 2500 /************************************************* 2501 * Create resources * 2502 *************************************************/ 2503 2504 pool->base.clock_sources[DCN20_CLK_SRC_PLL0] = 2505 dcn20_clock_source_create(ctx, ctx->dc_bios, 2506 CLOCK_SOURCE_COMBO_PHY_PLL0, 2507 &clk_src_regs[0], false); 2508 pool->base.clock_sources[DCN20_CLK_SRC_PLL1] = 2509 dcn20_clock_source_create(ctx, ctx->dc_bios, 2510 CLOCK_SOURCE_COMBO_PHY_PLL1, 2511 &clk_src_regs[1], false); 2512 pool->base.clock_sources[DCN20_CLK_SRC_PLL2] = 2513 dcn20_clock_source_create(ctx, ctx->dc_bios, 2514 CLOCK_SOURCE_COMBO_PHY_PLL2, 2515 &clk_src_regs[2], false); 2516 pool->base.clock_sources[DCN20_CLK_SRC_PLL3] = 2517 dcn20_clock_source_create(ctx, ctx->dc_bios, 2518 CLOCK_SOURCE_COMBO_PHY_PLL3, 2519 &clk_src_regs[3], false); 2520 pool->base.clock_sources[DCN20_CLK_SRC_PLL4] = 2521 dcn20_clock_source_create(ctx, ctx->dc_bios, 2522 CLOCK_SOURCE_COMBO_PHY_PLL4, 2523 &clk_src_regs[4], false); 2524 pool->base.clock_sources[DCN20_CLK_SRC_PLL5] = 2525 dcn20_clock_source_create(ctx, ctx->dc_bios, 2526 CLOCK_SOURCE_COMBO_PHY_PLL5, 2527 &clk_src_regs[5], false); 2528 pool->base.clk_src_count = DCN20_CLK_SRC_TOTAL; 2529 /* todo: not reuse phy_pll registers */ 2530 pool->base.dp_clock_source = 2531 dcn20_clock_source_create(ctx, ctx->dc_bios, 2532 CLOCK_SOURCE_ID_DP_DTO, 2533 &clk_src_regs[0], true); 2534 2535 for (i = 0; i < pool->base.clk_src_count; i++) { 2536 if (pool->base.clock_sources[i] == NULL) { 2537 dm_error("DC: failed to create clock sources!\n"); 2538 BREAK_TO_DEBUGGER(); 2539 goto create_fail; 2540 } 2541 } 2542 2543 pool->base.dccg = dccg2_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask); 2544 if (pool->base.dccg == NULL) { 2545 dm_error("DC: failed to create dccg!\n"); 2546 BREAK_TO_DEBUGGER(); 2547 goto create_fail; 2548 } 2549 2550 pool->base.dmcu = dcn20_dmcu_create(ctx, 2551 &dmcu_regs, 2552 &dmcu_shift, 2553 &dmcu_mask); 2554 if (pool->base.dmcu == NULL) { 2555 dm_error("DC: failed to create dmcu!\n"); 2556 BREAK_TO_DEBUGGER(); 2557 goto create_fail; 2558 } 2559 2560 pool->base.abm = dce_abm_create(ctx, 2561 &abm_regs, 2562 &abm_shift, 2563 &abm_mask); 2564 if (pool->base.abm == NULL) { 2565 dm_error("DC: failed to create abm!\n"); 2566 BREAK_TO_DEBUGGER(); 2567 goto create_fail; 2568 } 2569 2570 pool->base.pp_smu = dcn20_pp_smu_create(ctx); 2571 2572 2573 if (!init_soc_bounding_box(dc, pool)) { 2574 dm_error("DC: failed to initialize soc bounding box!\n"); 2575 BREAK_TO_DEBUGGER(); 2576 goto create_fail; 2577 } 2578 2579 dml_init_instance(&dc->dml, loaded_bb, loaded_ip, dml_project_version); 2580 2581 if (!dc->debug.disable_pplib_wm_range) { 2582 struct pp_smu_wm_range_sets ranges = {0}; 2583 int i = 0; 2584 2585 ranges.num_reader_wm_sets = 0; 2586 2587 if (loaded_bb->num_states == 1) { 2588 ranges.reader_wm_sets[0].wm_inst = i; 2589 ranges.reader_wm_sets[0].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN; 2590 ranges.reader_wm_sets[0].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX; 2591 ranges.reader_wm_sets[0].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN; 2592 ranges.reader_wm_sets[0].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX; 2593 2594 ranges.num_reader_wm_sets = 1; 2595 } else if (loaded_bb->num_states > 1) { 2596 for (i = 0; i < 4 && i < loaded_bb->num_states; i++) { 2597 ranges.reader_wm_sets[i].wm_inst = i; 2598 ranges.reader_wm_sets[i].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN; 2599 ranges.reader_wm_sets[i].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX; 2600 DC_FP_START(); 2601 dcn20_fpu_set_wm_ranges(i, &ranges, loaded_bb); 2602 DC_FP_END(); 2603 2604 ranges.num_reader_wm_sets = i + 1; 2605 } 2606 2607 ranges.reader_wm_sets[0].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN; 2608 ranges.reader_wm_sets[ranges.num_reader_wm_sets - 1].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX; 2609 } 2610 2611 ranges.num_writer_wm_sets = 1; 2612 2613 ranges.writer_wm_sets[0].wm_inst = 0; 2614 ranges.writer_wm_sets[0].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN; 2615 ranges.writer_wm_sets[0].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX; 2616 ranges.writer_wm_sets[0].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN; 2617 ranges.writer_wm_sets[0].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX; 2618 2619 /* Notify PP Lib/SMU which Watermarks to use for which clock ranges */ 2620 if (pool->base.pp_smu->nv_funcs.set_wm_ranges) 2621 pool->base.pp_smu->nv_funcs.set_wm_ranges(&pool->base.pp_smu->nv_funcs.pp_smu, &ranges); 2622 } 2623 2624 init_data.ctx = dc->ctx; 2625 pool->base.irqs = dal_irq_service_dcn20_create(&init_data); 2626 if (!pool->base.irqs) 2627 goto create_fail; 2628 2629 /* mem input -> ipp -> dpp -> opp -> TG */ 2630 for (i = 0; i < pool->base.pipe_count; i++) { 2631 pool->base.hubps[i] = dcn20_hubp_create(ctx, i); 2632 if (pool->base.hubps[i] == NULL) { 2633 BREAK_TO_DEBUGGER(); 2634 dm_error( 2635 "DC: failed to create memory input!\n"); 2636 goto create_fail; 2637 } 2638 2639 pool->base.ipps[i] = dcn20_ipp_create(ctx, i); 2640 if (pool->base.ipps[i] == NULL) { 2641 BREAK_TO_DEBUGGER(); 2642 dm_error( 2643 "DC: failed to create input pixel processor!\n"); 2644 goto create_fail; 2645 } 2646 2647 pool->base.dpps[i] = dcn20_dpp_create(ctx, i); 2648 if (pool->base.dpps[i] == NULL) { 2649 BREAK_TO_DEBUGGER(); 2650 dm_error( 2651 "DC: failed to create dpps!\n"); 2652 goto create_fail; 2653 } 2654 } 2655 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 2656 pool->base.engines[i] = dcn20_aux_engine_create(ctx, i); 2657 if (pool->base.engines[i] == NULL) { 2658 BREAK_TO_DEBUGGER(); 2659 dm_error( 2660 "DC:failed to create aux engine!!\n"); 2661 goto create_fail; 2662 } 2663 pool->base.hw_i2cs[i] = dcn20_i2c_hw_create(ctx, i); 2664 if (pool->base.hw_i2cs[i] == NULL) { 2665 BREAK_TO_DEBUGGER(); 2666 dm_error( 2667 "DC:failed to create hw i2c!!\n"); 2668 goto create_fail; 2669 } 2670 pool->base.sw_i2cs[i] = NULL; 2671 } 2672 2673 for (i = 0; i < pool->base.res_cap->num_opp; i++) { 2674 pool->base.opps[i] = dcn20_opp_create(ctx, i); 2675 if (pool->base.opps[i] == NULL) { 2676 BREAK_TO_DEBUGGER(); 2677 dm_error( 2678 "DC: failed to create output pixel processor!\n"); 2679 goto create_fail; 2680 } 2681 } 2682 2683 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { 2684 pool->base.timing_generators[i] = dcn20_timing_generator_create( 2685 ctx, i); 2686 if (pool->base.timing_generators[i] == NULL) { 2687 BREAK_TO_DEBUGGER(); 2688 dm_error("DC: failed to create tg!\n"); 2689 goto create_fail; 2690 } 2691 } 2692 2693 pool->base.timing_generator_count = i; 2694 2695 pool->base.mpc = dcn20_mpc_create(ctx); 2696 if (pool->base.mpc == NULL) { 2697 BREAK_TO_DEBUGGER(); 2698 dm_error("DC: failed to create mpc!\n"); 2699 goto create_fail; 2700 } 2701 2702 pool->base.hubbub = dcn20_hubbub_create(ctx); 2703 if (pool->base.hubbub == NULL) { 2704 BREAK_TO_DEBUGGER(); 2705 dm_error("DC: failed to create hubbub!\n"); 2706 goto create_fail; 2707 } 2708 2709 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { 2710 pool->base.dscs[i] = dcn20_dsc_create(ctx, i); 2711 if (pool->base.dscs[i] == NULL) { 2712 BREAK_TO_DEBUGGER(); 2713 dm_error("DC: failed to create display stream compressor %d!\n", i); 2714 goto create_fail; 2715 } 2716 } 2717 2718 if (!dcn20_dwbc_create(ctx, &pool->base)) { 2719 BREAK_TO_DEBUGGER(); 2720 dm_error("DC: failed to create dwbc!\n"); 2721 goto create_fail; 2722 } 2723 if (!dcn20_mmhubbub_create(ctx, &pool->base)) { 2724 BREAK_TO_DEBUGGER(); 2725 dm_error("DC: failed to create mcif_wb!\n"); 2726 goto create_fail; 2727 } 2728 2729 if (!resource_construct(num_virtual_links, dc, &pool->base, 2730 &res_create_funcs)) 2731 goto create_fail; 2732 2733 dcn20_hw_sequencer_construct(dc); 2734 2735 // IF NV12, set PG function pointer to NULL. It's not that 2736 // PG isn't supported for NV12, it's that we don't want to 2737 // program the registers because that will cause more power 2738 // to be consumed. We could have created dcn20_init_hw to get 2739 // the same effect by checking ASIC rev, but there was a 2740 // request at some point to not check ASIC rev on hw sequencer. 2741 if (ASICREV_IS_NAVI12_P(dc->ctx->asic_id.hw_internal_rev)) { 2742 dc->hwseq->funcs.enable_power_gating_plane = NULL; 2743 dc->debug.disable_dpp_power_gate = true; 2744 dc->debug.disable_hubp_power_gate = true; 2745 } 2746 2747 2748 dc->caps.max_planes = pool->base.pipe_count; 2749 2750 for (i = 0; i < dc->caps.max_planes; ++i) 2751 dc->caps.planes[i] = plane_cap; 2752 2753 dc->cap_funcs = cap_funcs; 2754 2755 if (dc->ctx->dc_bios->fw_info.oem_i2c_present) { 2756 ddc_init_data.ctx = dc->ctx; 2757 ddc_init_data.link = NULL; 2758 ddc_init_data.id.id = dc->ctx->dc_bios->fw_info.oem_i2c_obj_id; 2759 ddc_init_data.id.enum_id = 0; 2760 ddc_init_data.id.type = OBJECT_TYPE_GENERIC; 2761 pool->base.oem_device = dc->link_srv->create_ddc_service(&ddc_init_data); 2762 } else { 2763 pool->base.oem_device = NULL; 2764 } 2765 2766 return true; 2767 2768create_fail: 2769 2770 dcn20_resource_destruct(pool); 2771 2772 return false; 2773} 2774 2775struct resource_pool *dcn20_create_resource_pool( 2776 const struct dc_init_data *init_data, 2777 struct dc *dc) 2778{ 2779 struct dcn20_resource_pool *pool = 2780 kzalloc(sizeof(struct dcn20_resource_pool), GFP_ATOMIC); 2781 2782 if (!pool) 2783 return NULL; 2784 2785 if (dcn20_resource_construct(init_data->num_virtual_links, dc, pool)) 2786 return &pool->base; 2787 2788 BREAK_TO_DEBUGGER(); 2789 kfree(pool); 2790 return NULL; 2791} 2792