/freebsd-11-stable/sys/arm/arm/ |
H A D | cpufunc_asm_arm11.S | 44 mcr p15, 0, r0, c8, c6, 1 /* flush D tlb single entry */ 45 mcr p15, 0, r0, c8, c5, 1 /* flush I tlb single entry */ 46 mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */ 64 mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */ 65 mcr p15, 0, r0, c2, c0, 0 /* set the new TTB */ 66 mcr p15, 0, r0, c8, c7, 0 /* and flush the I+D tlbs */ 79 mcr p15, 0, r0, c8, c7, 0 /* flush I+D tlb */ 80 mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */ 85 mcr p15, 0, r0, c8, c6, 0 /* flush D tlb */ 86 mcr p1 [all...] |
H A D | cpufunc_asm_armv4.S | 47 mcr p15, 0, r0, c8, c7, 0 /* flush I+D tlb */ 52 mcr p15, 0, r0, c8, c6, 0 /* flush D tlb */ 57 mcr p15, 0, r0, c8, c6, 1 /* flush D tlb single entry */ 65 mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */ 71 mcr p15, 0, r0, c7, c7, 0 /* invalidate all I+D cache */
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H A D | cpufunc_asm_arm11x6.S | 69 mcr p15, 0, Rtmp1, c7, c5, 0 /* Invalidate Entire I cache */ 83 mcr p15, 0, Rtmp1, c7, c5, 0; /* Nuke Whole Icache */ \ 84 mcr p15, 0, Rtmp1, c7, c5, 0; /* Nuke Whole Icache */ \ 85 mcr p15, 0, Rtmp1, c7, c5, 0; /* Nuke Whole Icache */ \ 86 mcr p15, 0, Rtmp1, c7, c5, 0; /* Nuke Whole Icache */ \ 104 mcr p15, 0, reg, c7, c14, 0;/* Clean and Invalidate Entire Data Cache */ \ 105 mcr p15, 0, reg, c7, c10, 4;/* Data Synchronization Barrier */ 109 mcr p15, 0, reg, c7, c14, 0;/* Clean and Invalidate Entire Data Cache */ \ 113 mcr p15, 0, reg, c7, c10, 4;/* Data Synchronization Barrier */ 118 mcr p1 [all...] |
H A D | cpufunc_asm_armv6.S | 52 mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */ 54 mcr p15, 0, r0, c2, c0, 0 /* load new TTB */ 56 mcr p15, 0, r0, c8, c7, 0 /* invalidate I+D TLBs */ 69 mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */ 78 mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */ 92 mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */ 103 mcr p15, 0, r0, c7, c5, 0 /* Flush I cache */ 106 mcr p15, 0, r0, c7, c14, 0 /* clean & invalidate D cache */ 107 mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */ 113 mcr p1 [all...] |
H A D | cpufunc_asm_fa526.S | 43 mcr p15, 0, r1, c7, c14, 0 /* clean and invalidate D$ */ 44 mcr p15, 0, r1, c7, c5, 0 /* invalidate I$ */ 45 mcr p15, 0, r1, c7, c5, 6 /* invalidate BTB */ 46 mcr p15, 0, r1, c7, c10, 4 /* drain write and fill buffer */ 48 mcr p15, 0, r0, c2, c0, 0 /* Write the TTB */ 51 mcr p15, 0, r1, c8, c7, 0 /* invalidate I+D TLB */ 63 mcr p15, 0, r0, c8, c7, 1 /* flush Utlb single entry */ 71 mcr p15, 0, r0, c7, c0, 4 /* Wait for interrupt*/ 80 mcr p15, 0, r0, c7, c14, 0 /* clean and invalidate D$ */ 81 mcr p1 [all...] |
H A D | cpufunc_asm_xscale_c3.S | 137 mcr p15, 0, r0, c7, c5, 0 /* flush I cache (D cleaned below) */ 149 mcr p15, 0, r3, c7, c14, 2 /* clean and invalidate */ 158 mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */ 175 1: mcr p15, 0, r0, c7, c14, 1 /* clean/invalidate L1 D cache entry */ 177 mcr p15, 0, r0, c7, c5, 1 /* flush I cache single entry */ 184 mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */ 197 1: mcr p15, 0, r0, c7, c10, 1 /* clean D cache entry */ 198 mcr p15, 0, r0, c7, c5, 1 /* flush I cache single entry */ 205 mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */ 218 1: mcr p1 [all...] |
H A D | cpufunc_asm_xscale.S | 140 mcr p15, 0, r0, c7, c5, 0 /* invalidate I$ and BTB */ 141 mcr p15, 0, r0, c7, c10, 4 /* drain write and fill buffer */ 148 mcr p15, 0, r0, c2, c0, 0 151 mcr p15, 0, r0, c8, c7, 0 /* invalidate I+D TLB */ 154 mcr p15, 0, r0, c7, c5, 0 /* invalidate I$ and BTB */ 169 mcr p15, 0, r0, c8, c6, 1 /* flush D tlb single entry */ 170 mcr p15, 0, r0, c8, c5, 1 /* flush I tlb single entry */ 178 mcr p15, 0, r0, c7, c7, 0 /* flush I+D cache */ 183 mcr p15, 0, r0, c7, c5, 0 /* flush I cache */ 188 mcr p1 [all...] |
H A D | cpufunc_asm_armv5_ec.S | 60 mcr p15, 0, r0, c7, c5, 0 /* Invalidate ICache */ 63 mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */ 65 mcr p15, 0, r0, c2, c0, 0 /* load new TTB */ 67 mcr p15, 0, r0, c8, c7, 0 /* invalidate I+D TLBs */ 87 mcr p15, 0, r0, c7, c5, 1 /* Invalidate I cache SE with VA */ 88 mcr p15, 0, r0, c7, c10, 1 /* Clean D cache SE with VA */ 92 mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */ 101 mcr p15, 0, r0, c7, c5, 0 /* Flush I cache */ 108 mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */ 126 mcr p1 [all...] |
H A D | cpufunc_asm_arm9.S | 48 mcr p15, 0, r0, c2, c0, 0 /* load new TTB */ 50 mcr p15, 0, r0, c8, c7, 0 /* invalidate I+D TLBs */ 58 mcr p15, 0, r0, c8, c6, 1 /* flush D tlb single entry */ 59 mcr p15, 0, r0, c8, c5, 1 /* flush I tlb single entry */ 82 mcr p15, 0, r0, c7, c5, 1 /* Invalidate I cache SE with VA */ 83 mcr p15, 0, r0, c7, c10, 1 /* Clean D cache SE with VA */ 95 mcr p15, 0, r0, c7, c5, 0 /* Flush I cache */ 104 mcr p15, 0, ip, c7, c10, 2 /* Clean D cache SE with Set/Index */ 125 mcr p15, 0, r0, c7, c10, 1 /* Clean D cache SE with VA */ 142 mcr p1 [all...] |
H A D | cpufunc_asm_sheeva.S | 50 mcr p15, 0, r1, c7, c5, 0 /* Invalidate ICache */ 54 mcr p15, 1, r1, c15, c9, 0 /* Clean L2 */ 55 mcr p15, 1, r1, c15, c11, 0 /* Invalidate L2 */ 60 mcr p15, 0, r1, c7, c10, 4 /* drain the write buffer */ 62 mcr p15, 0, r0, c2, c0, 0 /* load new TTB */ 64 mcr p15, 0, r0, c8, c7, 0 /* invalidate I+D TLBs */ 93 mcr p15, 5, r0, c15, c15, 0 /* Clean and inv zone start address */ 94 mcr p15, 5, r2, c15, c15, 1 /* Clean and inv zone end address */ 106 mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */ 136 mcr p1 [all...] |
H A D | cpufunc_asm.S | 102 mcr p15, 0, r0, c3, c0, 0 170 mcr p15, 0, r0, c7, c10, 4 /* Drain write buffer */ 172 mcr p15, 0, r1, c9, c2, 0 /* Enable data cache lock mode */ 174 mcr p15, 0, r0, c7, c2, 5 /* Allocate the cache line */ 175 mcr p15, 0, r0, c7, c10, 4 /* Drain write buffer */ 178 mcr p15, 0, r0, c7, c10, 4 /* Drain write buffer */ 179 mcr p15, 0, r1, c9, c2, 0 /* Disable data cache lock mode */
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H A D | cpufunc_asm_pj4b.S | 48 mcr p15, 1, r0, c15, c1, 0 58 mcr p15, 1, r0, c15, c1, 1 67 mcr p15, 1, r0, c15, c2, 0 77 mcr p15, 1, r0, c15, c1, 2 82 mcr p15, 0, r0, c1, c0, 1
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H A D | cpufunc_asm_armv7.S | 77 mcr CP15_TTBR0(r0) 80 mcr CP15_TLBIALLIS 82 mcr CP15_TLBIALL 92 mcr CP15_TLBIALLIS 93 mcr CP15_BPIALLIS 95 mcr CP15_TLBIALL 96 mcr CP15_BPIALL 107 mcr CP15_TLBIMVAAIS(r0) 108 mcr CP15_BPIALLIS 110 mcr CP15_TLBIMV [all...] |
H A D | cpu_asm-v6.S | 53 mcr CP15_DCIALL 63 mcr CP15_CSSELR(r0) /* set cache level */ 84 2: mcr CP15_DCISW(r3) /* invalidate line */ 99 mcr CP15_CSSELR(r0) 108 mcr CP15_DCIALL 118 mcr CP15_CSSELR(r0) /* set cache level */ 139 2: mcr CP15_DCISW(r3) /* invalidate line */ 154 mcr CP15_CSSELR(r0) 162 mcr CP15_DCCIALL 171 1: mcr CP15_CSSEL [all...] |
H A D | locore-v6.S | 142 mcr CP15_SCTLR(r7) 146 mcr CP15_ICIALLU 281 mcr CP15_TTBR0(r0) /* Set TTB */ 283 mcr CP15_CONTEXTIDR(r0) /* Set ASID to 0 */ 287 mcr CP15_DACR(r0) 294 mcr CP15_PRRR(r0) 296 mcr CP15_NMRR(r0) 297 mcr CP15_TLBIALL /* Flush TLB */ 307 mcr CP15_SCTLR(r0) 310 mcr CP15_TLBIAL [all...] |
H A D | swtch-v6.S | 130 mcr CP15_TTBR0(r1) /* switch to kernel TTB */ 132 mcr CP15_TLBIASID(r2) /* flush not global TLBs */ 134 mcr CP15_TTBR0(r0) /* switch to new TTB */ 140 mcr CP15_TLBIASID(r2) /* flush not global TLBs */ 454 mcr CP15_TPIDRPRW(r11) 469 mcr CP15_TPIDRURW(r3) /* write tls thread reg 2 */ 470 mcr CP15_TPIDRURO(r3) /* write tls thread reg 3 */
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H A D | locore-v4.S | 153 mcr CP15_SCTLR(r2) 216 mcr p15, 0, r0, c2, c0, 0 /* Set TTB */ 217 mcr p15, 0, r0, c8, c7, 0 /* Flush TLB */ 221 mcr p15, 0, r0, c3, c0, 0 227 mcr CP15_SCTLR(r0) 410 mcr CP15_SCTLR(r0)
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/freebsd-11-stable/sys/dev/uart/ |
H A D | uart_dev_ns8250.h | 39 uint8_t mcr; member in struct:ns8250_softc
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H A D | uart_dev_lpc.c | 384 uint8_t mcr; member in struct:lpc_ns8250_softc 453 lpc_ns8250->mcr = uart_getreg(bas, REG_MCR); 484 if (lpc_ns8250->mcr & MCR_DTR) 486 if (lpc_ns8250->mcr & MCR_RTS) 688 uint8_t lsr, mcr, ier; local 697 mcr = MCR_IE; 702 mcr |= MCR_DTR | MCR_RTS; 729 uart_setreg(bas, REG_MCR, mcr); 745 uart_setreg(bas, REG_MCR, mcr); 775 uart_setreg(bas, REG_MCR, mcr); [all...] |
/freebsd-11-stable/usr.sbin/bhyve/ |
H A D | uart_emul.c | 111 uint8_t mcr; /* Modem control register (R/W) */ member in struct:uart_softc 284 modem_status(uint8_t mcr) argument 288 if (mcr & MCR_LOOPBACK) { 294 if (mcr & MCR_RTS) 296 if (mcr & MCR_DTR) 298 if (mcr & MCR_OUT1) 300 if (mcr & MCR_OUT2) 346 sc->msr = modem_status(sc->mcr); 386 if ((sc->mcr & MCR_LOOPBACK) != 0) { 424 if (sc->mcr [all...] |
/freebsd-11-stable/sys/arm/include/ |
H A D | asm.h | 239 #define ISB mcr CP15_CP15ISB 240 #define DSB mcr CP15_CP15DSB 241 #define DMB mcr CP15_CP15DMB 242 #define WFI mcr CP15_CP15WFI 244 #define ISB mcr CP15_CP15ISB 245 #define DSB mcr CP15_CP15DSB /* DSB and DMB are the */ 246 #define DMB mcr CP15_CP15DSB /* same prior to v6.*/
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/freebsd-11-stable/sys/arm/mv/armadaxp/ |
H A D | mptramp.S | 36 mcr p15, 0, r0, c7, c7, 0
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/freebsd-11-stable/sys/contrib/ncsw/Peripherals/BM/ |
H A D | bm_portal.c | 411 struct bm_mc_result *mcr; local 421 while (!(mcr = bm_mc_result(p_BmPortal->p_BmPortalLow))) ; 422 ret = num = (uint8_t)(mcr->verb & BM_MCR_VERB_ACQUIRE_BUFCOUNT); 426 bufs[num].hi = mcr->acquire.bufs[num].hi; 427 bufs[num].lo = mcr->acquire.bufs[num].lo; 436 struct bm_mc_result *mcr; local 443 while (!(mcr = bm_mc_result(p_BmPortal->p_BmPortalLow))) ; 445 *p_Pools = mcr->query.ds.state; 447 *p_Pools = mcr->query.as.state;
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/freebsd-11-stable/sys/dev/vte/ |
H A D | if_vte.c | 1233 uint16_t mcr; local 1238 mcr = CSR_READ_2(sc, VTE_MCR0); 1239 mcr &= ~(MCR0_FC_ENB | MCR0_FULL_DUPLEX); 1241 mcr |= MCR0_FULL_DUPLEX; 1244 mcr |= MCR0_FC_ENB; 1252 mcr |= MCR0_FC_ENB; 1255 CSR_WRITE_2(sc, VTE_MCR0, mcr); 1604 uint16_t mcr; local 1607 mcr = CSR_READ_2(sc, VTE_MCR1); 1608 CSR_WRITE_2(sc, VTE_MCR1, mcr | MCR1_MAC_RESE 1824 uint16_t mcr; local 1851 uint16_t mcr; local 1964 uint16_t mchash[4], mcr; local [all...] |
/freebsd-11-stable/sys/dev/ubsec/ |
H A D | ubsec.c | 648 struct ubsec_mcr *mcr; local 657 mcr = (struct ubsec_mcr *)q2->q_mcr.dma_vaddr; 658 if ((mcr->mcr_flags & htole16(UBS_MCR_DONE)) == 0) { 1779 struct ubsec_mcr *mcr; local 1791 mcr = (struct ubsec_mcr *)rng->rng_q.q_mcr.dma_vaddr; 1794 mcr->mcr_pkts = htole16(1); 1795 mcr->mcr_flags = 0; 1796 mcr->mcr_cmdctxp = htole32(rng->rng_q.q_ctx.dma_paddr); 1797 mcr->mcr_ipktbuf.pb_addr = mcr 2138 struct ubsec_mcr *mcr; local 2340 struct ubsec_mcr *mcr; local 2538 struct ubsec_mcr *mcr; local 2754 ubsec_dump_mcr(struct ubsec_mcr *mcr) argument [all...] |