1/* $NetBSD: cpufunc_asm_armv4.S,v 1.1 2001/11/10 23:14:09 thorpej Exp $ */ 2 3/*- 4 * Copyright (c) 2001 ARM Limited 5 * Copyright (c) 1997,1998 Mark Brinicombe. 6 * Copyright (c) 1997 Causality Limited 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by Causality Limited. 20 * 4. The name of Causality Limited may not be used to endorse or promote 21 * products derived from this software without specific prior written 22 * permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY CAUSALITY LIMITED ``AS IS'' AND ANY EXPRESS 25 * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 26 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 27 * DISCLAIMED. IN NO EVENT SHALL CAUSALITY LIMITED BE LIABLE FOR ANY DIRECT, 28 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 29 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 34 * SUCH DAMAGE. 35 * 36 * ARM9 assembly functions for CPU / MMU / TLB specific operations 37 * 38 */ 39 40#include <machine/asm.h> 41__FBSDID("$FreeBSD$"); 42 43/* 44 * TLB functions 45 */ 46ENTRY(armv4_tlb_flushID) 47 mcr p15, 0, r0, c8, c7, 0 /* flush I+D tlb */ 48 RET 49END(armv4_tlb_flushID) 50 51ENTRY(armv4_tlb_flushD) 52 mcr p15, 0, r0, c8, c6, 0 /* flush D tlb */ 53 RET 54END(armv4_tlb_flushD) 55 56ENTRY(armv4_tlb_flushD_SE) 57 mcr p15, 0, r0, c8, c6, 1 /* flush D tlb single entry */ 58 RET 59END(armv4_tlb_flushD_SE) 60 61/* 62 * Other functions 63 */ 64ENTRY(armv4_drain_writebuf) 65 mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */ 66 RET 67END(armv4_drain_writebuf) 68 69ENTRY(armv4_idcache_inv_all) 70 mov r0, #0 71 mcr p15, 0, r0, c7, c7, 0 /* invalidate all I+D cache */ 72 RET 73END(armv4_drain_writebuf) 74 75