arm/arm/cpufunc_asm_xscale.S

140 	mcr	p15, 0, r0, c7, c5, 0	/* invalidate I$ and BTB */
141 	mcr	p15, 0, r0, c7, c10, 4	/* drain write and fill buffer */
148 	mcr	p15, 0, r0, c2, c0, 0
151 	mcr	p15, 0, r0, c8, c7, 0	/* invalidate I+D TLB */
154 	mcr	p15, 0, r0, c7, c5, 0	/* invalidate I$ and BTB */
169 	mcr	p15, 0, r0, c8, c6, 1	/* flush D tlb single entry */
170 	mcr	p15, 0, r0, c8, c5, 1	/* flush I tlb single entry */
178 	mcr	p15, 0, r0, c7, c7, 0	/* flush I+D cache */
183 	mcr	p15, 0, r0, c7, c5, 0	/* flush I cache */
188 	mcr	p15, 0, r0, c7, c6, 0	/* flush D cache */
193 	mcr	p15, 0, r0, c7, c5, 1	/* flush I cache single entry */
203 	mcr	p15, 0, r0, c7, c10, 1
204 	mcr	p15, 0, r0, c7, c6, 1	/* flush D cache single entry */
209 	mcr	p15, 0, r0, c7, c10, 1	/* clean D cache entry */
296 	mcr	p15, 0, r0, c7, c5, 0	/* flush I cache (D cleaned below) */
303 	mcr	p15, 0, r0, c7, c2, 5	/* allocate cache line */
309 	mcr	p15, 0, r0, c7, c10, 4	/* drain write buffer */
336 	mcr	p15, 0, r0, c7, c10, 4	/* drain write buffer */
342 	mcr	p15, 0, r0, c7, c10, 1	/* clean D cache entry */
344 	mcr	p15, 0, r0, c7, c10, 4	/* drain write buffer */
345 	mcr	p15, 0, r0, c7, c5, 1	/* flush I cache single entry */
346 	mcr	p15, 0, r0, c7, c6, 1	/* flush D cache single entry */
351 	mcr	p15, 0, r0, c7, c10, 1	/* clean D cache entry */
353 	mcr	p15, 0, r0, c7, c10, 4	/* drain write buffer */
354 	mcr	p15, 0, r0, c7, c6, 1	/* flush D cache single entry */
372 1:	mcr	p15, 0, r0, c7, c10, 1	/* clean D cache entry */
379 	mcr	p15, 0, r0, c7, c10, 4	/* drain write buffer */
393 1:	mcr	p15, 0, r0, c7, c10, 1	/* clean D cache entry */
394 	mcr	p15, 0, r0, c7, c6, 1	/* flush D cache single entry */
395 	mcr	p15, 0, r0, c7, c5, 1	/* flush I cache single entry */
402 	mcr	p15, 0, r0, c7, c10, 4	/* drain write buffer */
415 1:	mcr	p15, 0, r0, c7, c10, 1	/* clean D cache entry */
416 	mcr	p15, 0, r0, c7, c6, 1	/* flush D cache single entry */
423 	mcr	p15, 0, r0, c7, c10, 4	/* drain write buffer */
436 1:	mcr	p15, 0, r0, c7, c10, 1	/* clean D cache entry */
437 	mcr	p15, 0, r0, c7, c5, 1	/* flush I cache single entry */
444 	mcr	p15, 0, r0, c7, c10, 4	/* drain write buffer */
454 1:	mcr	p15, 0, r0, c7, c6, 1	/* flush D cache single entry */
459 	mcr	p15, 0, r0, c7, c10, 4	/* drain write buffer */
482 	mcr	p15, 0, r0, c2, c0, 0
485 	mcr	p15, 0, r0, c8, c7, 0	/* flush the I+D tlb */
503 	mcr	p14, 0, r0, c7, c0, 0