1239268Sgonzo/*- 2239268Sgonzo * Copyright (C) 2011 MARVELL INTERNATIONAL LTD. 3239268Sgonzo * All rights reserved. 4239268Sgonzo * 5239268Sgonzo * Developed by Semihalf. 6239268Sgonzo * 7239268Sgonzo * Redistribution and use in source and binary forms, with or without 8239268Sgonzo * modification, are permitted provided that the following conditions 9239268Sgonzo * are met: 10239268Sgonzo * 1. Redistributions of source code must retain the above copyright 11239268Sgonzo * notice, this list of conditions and the following disclaimer. 12239268Sgonzo * 2. Redistributions in binary form must reproduce the above copyright 13239268Sgonzo * notice, this list of conditions and the following disclaimer in the 14239268Sgonzo * documentation and/or other materials provided with the distribution. 15239268Sgonzo * 3. Neither the name of MARVELL nor the names of contributors 16239268Sgonzo * may be used to endorse or promote products derived from this software 17239268Sgonzo * without specific prior written permission. 18239268Sgonzo * 19239268Sgonzo * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND 20239268Sgonzo * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21239268Sgonzo * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22239268Sgonzo * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 23239268Sgonzo * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24239268Sgonzo * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 25239268Sgonzo * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26239268Sgonzo * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27239268Sgonzo * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28239268Sgonzo * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29239268Sgonzo * SUCH DAMAGE. 30239268Sgonzo */ 31239268Sgonzo 32239268Sgonzo#include <machine/asm.h> 33239268Sgonzo__FBSDID("$FreeBSD$"); 34239268Sgonzo 35239268Sgonzo#include <machine/param.h> 36239268Sgonzo 37250293Sgber.Lpj4b_sf_ctrl_reg: 38250293Sgber .word 0xf1021820 39250293Sgber 40239268SgonzoENTRY(pj4b_config) 41250293Sgber 42250293Sgber /* Set Auxiliary Debug Modes Control 0 register */ 43250293Sgber mrc p15, 1, r0, c15, c1, 0 44250293Sgber /* ARMADAXP errata fix: ARM-CPU-6136 */ 45250293Sgber bic r0, r0, #(1 << 12) /* LDSTM first issue is single word */ 46250293Sgber 47250293Sgber orr r0, r0, #(1 << 22) /* DVM_WAKEUP disable */ 48250293Sgber mcr p15, 1, r0, c15, c1, 0 49250293Sgber 50250293Sgber /* Set Auxiliary Debug Modes Control 1 register */ 51250293Sgber mrc p15, 1, r0, c15, c1, 1 52250293Sgber /* ARMADAXP errata fix: ARM-CPU-6409 */ 53250293Sgber bic r0, r0, #(1 << 2) /* Disable static branch prediction */ 54250293Sgber 55250293Sgber orr r0, r0, #(1 << 5) /* STREX backoff disable */ 56250293Sgber orr r0, r0, #(1 << 8) /* Internal parity handling disable */ 57250293Sgber orr r0, r0, #(1 << 16) /* Disable data transfer for clean line */ 58250293Sgber mcr p15, 1, r0, c15, c1, 1 59250293Sgber 60250293Sgber /* Set Auxiliary Function Modes Control 0 register */ 61250293Sgber mrc p15, 1, r0, c15, c2, 0 62250293Sgber#if defined(SMP) 63250293Sgber orr r0, r0, #(1 << 1) /* SMP/nAMP enabled (coherency) */ 64250293Sgber#endif 65250293Sgber orr r0, r0, #(1 << 2) /* L1 parite enable */ 66250293Sgber orr r0, r0, #(1 << 8) /* Cache and TLB maintenance broadcast enable */ 67250293Sgber mcr p15, 1, r0, c15, c2, 0 68250293Sgber 69239268Sgonzo /* Set Auxiliary Debug Modes Control 2 register */ 70239268Sgonzo mrc p15, 1, r0, c15, c1, 2 71250293Sgber bic r0, r0, #(1 << 23) /* Enable fast LDR */ 72250293Sgber orr r0, r0, #(1 << 25) /* Intervention Interleave disable */ 73250293Sgber orr r0, r0, #(1 << 27) /* Critical word first sequencing disable */ 74250293Sgber orr r0, r0, #(1 << 29) /* Disable MO device read / write */ 75250293Sgber orr r0, r0, #(1 << 30) /* L1 cache strict round-robin replacement policy*/ 76258787Seadler orr r0, r0, #(1 << 31) /* Enable write evict */ 77239268Sgonzo mcr p15, 1, r0, c15, c1, 2 78239268Sgonzo#if defined(SMP) 79239268Sgonzo /* Set SMP mode in Auxiliary Control Register */ 80239268Sgonzo mrc p15, 0, r0, c1, c0, 1 81239268Sgonzo orr r0, r0, #(1 << 5) 82239268Sgonzo mcr p15, 0, r0, c1, c0, 1 83239268Sgonzo#endif 84250293Sgber 85250293Sgber /* Load CPU number */ 86250293Sgber mrc p15, 0, r0, c0, c0, 5 87250293Sgber and r0, r0, #0xf 88250293Sgber 89250293Sgber /* SF Enable and invalidate */ 90250293Sgber ldr r1, .Lpj4b_sf_ctrl_reg 91250293Sgber ldr r2, [r1, r0, lsl #8] 92250293Sgber orr r2, r2, #(1 << 0) 93250293Sgber bic r2, r2, #(1 << 8) 94250293Sgber str r2, [r1, r0, lsl #8] 95250293Sgber 96239268Sgonzo RET 97248361SandrewEND(pj4b_config) 98248361Sandrew 99