1172738Simp/*	$NetBSD: cpufunc_asm_arm11.S,v 1.2 2005/12/11 12:16:41 christos Exp $	*/
2172738Simp
3172738Simp/*
4172738Simp * Copyright (c) 2002, 2005 ARM Limited
5172738Simp * All rights reserved.
6172738Simp *
7172738Simp * Redistribution and use in source and binary forms, with or without
8172738Simp * modification, are permitted provided that the following conditions
9172738Simp * are met:
10172738Simp * 1. Redistributions of source code must retain the above copyright
11172738Simp *    notice, this list of conditions and the following disclaimer.
12172738Simp * 2. Redistributions in binary form must reproduce the above copyright
13172738Simp *    notice, this list of conditions and the following disclaimer in the
14172738Simp *    documentation and/or other materials provided with the distribution.
15172738Simp * 3. The name of the company may not be used to endorse or promote
16172738Simp *    products derived from this software without specific prior written
17172738Simp *    permission.
18172738Simp *
19172738Simp * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
20172738Simp * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
21172738Simp * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
22172738Simp * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
23172738Simp * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
24172738Simp * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
25172738Simp * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
26172738Simp * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
27172738Simp * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
28172738Simp * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29172738Simp * SUCH DAMAGE.
30172738Simp *
31172738Simp * ARM11 assembly functions for CPU / MMU / TLB specific operations
32172738Simp *
33299069Spfg * XXX We make no attempt at present to take advantage of the v6 memory
34172738Simp * architecture or physically tagged cache.
35172738Simp */
36236991Simp
37172738Simp#include <machine/asm.h>
38172738Simp__FBSDID("$FreeBSD$");
39172738Simp
40172738Simp/*
41172738Simp * TLB functions
42172738Simp */
43172738SimpENTRY(arm11_tlb_flushID_SE)
44172738Simp	mcr	p15, 0, r0, c8, c6, 1	/* flush D tlb single entry */
45172738Simp	mcr	p15, 0, r0, c8, c5, 1	/* flush I tlb single entry */
46172738Simp	mcr	p15, 0, r0, c7, c10, 4	/* drain write buffer */
47172738Simp	RET
48248361SandrewEND(arm11_tlb_flushID_SE)
49172738Simp
50172738Simp/*
51172738Simp * Context switch.
52172738Simp *
53172738Simp * These is the CPU-specific parts of the context switcher cpu_switch()
54172738Simp * These functions actually perform the TTB reload.
55172738Simp *
56172738Simp * NOTE: Special calling convention
57172738Simp *	r1, r4-r13 must be preserved
58172738Simp */
59172738SimpENTRY(arm11_context_switch)
60172738Simp	/*
61172738Simp	 * We can assume that the caches will only contain kernel addresses
62172738Simp	 * at this point.  So no need to flush them again.
63172738Simp	 */
64172738Simp	mcr	p15, 0, r0, c7, c10, 4	/* drain the write buffer */
65172738Simp	mcr	p15, 0, r0, c2, c0, 0	/* set the new TTB */
66172738Simp	mcr	p15, 0, r0, c8, c7, 0	/* and flush the I+D tlbs */
67172738Simp
68172738Simp	/* Paranoia -- make sure the pipeline is empty. */
69172738Simp	nop
70172738Simp	nop
71172738Simp	nop
72172738Simp	RET
73248361SandrewEND(arm11_context_switch)
74172738Simp
75172738Simp/*
76172738Simp * TLB functions
77172738Simp */
78172738SimpENTRY(arm11_tlb_flushID)
79172738Simp	mcr	p15, 0, r0, c8, c7, 0	/* flush I+D tlb */
80172738Simp	mcr	p15, 0, r0, c7, c10, 4	/* drain write buffer */
81172738Simp	mov	pc, lr
82248361SandrewEND(arm11_tlb_flushID)
83172738Simp
84172738SimpENTRY(arm11_tlb_flushD)
85172738Simp	mcr	p15, 0, r0, c8, c6, 0	/* flush D tlb */
86172738Simp	mcr	p15, 0, r0, c7, c10, 4	/* drain write buffer */
87172738Simp	mov	pc, lr
88248361SandrewEND(arm11_tlb_flushD)
89172738Simp
90172738SimpENTRY(arm11_tlb_flushD_SE)
91172738Simp	mcr	p15, 0, r0, c8, c6, 1	/* flush D tlb single entry */
92172738Simp	mcr	p15, 0, r0, c7, c10, 4	/* drain write buffer */
93172738Simp	mov	pc, lr
94248361SandrewEND(arm11_tlb_flushD_SE)
95172738Simp
96172738Simp/*
97172738Simp * Other functions
98172738Simp */
99172738SimpENTRY(arm11_drain_writebuf)
100172738Simp	mcr	p15, 0, r0, c7, c10, 4	/* drain write buffer */
101172738Simp	mov	pc, lr
102248361SandrewEND(arm11_drain_writebuf)
103