arm/arm/cpufunc_asm_xscale_c3.S

137 	mcr	p15, 0, r0, c7, c5, 0	/* flush I cache (D cleaned below) */
149 	mcr	p15, 0, r3, c7, c14, 2	/* clean and invalidate */
158 	mcr	p15, 0, r0, c7, c10, 4	/* drain write buffer */
175 1:	mcr	p15, 0, r0, c7, c14, 1	/* clean/invalidate L1 D cache entry */
177 	mcr	p15, 0, r0, c7, c5, 1	/* flush I cache single entry */
184 	mcr	p15, 0, r0, c7, c10, 4	/* drain write buffer */
197 1:	mcr	p15, 0, r0, c7, c10, 1	/* clean D cache entry */
198 	mcr	p15, 0, r0, c7, c5, 1	/* flush I cache single entry */
205 	mcr	p15, 0, r0, c7, c10, 4	/* drain write buffer */
218 1:	mcr	p15, 0, r0, c7, c14, 1	/* Clean and invalidate D cache entry */
225 	mcr	p15, 0, r0, c7, c10, 4	/* drain write buffer */
239 1:	mcr	p15, 0, r0, c7, c10, 1	/* clean L1 D cache entry */
247 	mcr	p15, 0, r0, c7, c10, 4	/* drain write buffer */
255 	mcr	p15, 0, r0, c7, c10, 5	/* Data memory barrier */
262 	mcr	p15, 1, r3, c7, c15, 2
269 	mcr	p15, 0, r0, c7, c10, 4		@ data write barrier
272 	mcr	p15, 0, r0, c7, c10, 5	/* Data memory barrier */
277 	mcr	p15, 0, r0, c7, c10, 5	/* Data memory barrier */
283 1:	mcr	p15, 1, r0, c7, c11, 1	/* Clean L2 D cache entry */
291 	mcr	p15, 0, r0, c7, c10, 4		@ data write barrier
292 	mcr	p15, 0, r0, c7, c10, 5
299 	mcr	p15, 0, r0, c7, c10, 5	/* Data memory barrier */
305 1:	mcr	p15, 1, r0, c7, c11, 1	/* Clean L2 D cache entry */
306 	mcr	p15, 1, r0, c7, c7, 1   /* Invalidate L2 D cache entry */
311 	mcr	p15, 0, r0, c7, c10, 4		@ data write barrier
312 	mcr	p15, 0, r0, c7, c10, 5
318 	mcr	p15, 0, r0, c7, c10, 5	/* Data memory barrier */
324 1:	mcr	p15, 1, r0, c7, c7, 1   /* Invalidate L2 cache line */
328 	mcr	p15, 0, r0, c7, c10, 4		@ data write barrier
329 	mcr	p15, 0, r0, c7, c10, 5
347 	mcr	p15, 0, r0, c7, c5, 0	/* invalidate I$ and BTB */
348 	mcr	p15, 0, r0, c7, c10, 4	/* drain write and fill buffer */
358 	mcr	p15, 0, r0, c2, c0, 0
361 	mcr	p15, 0, r0, c8, c7, 0	/* invalidate I+D TLB */
391 	mcr	p15, 0, r0, c2, c0, 0
394 	mcr	p15, 0, r0, c8, c7, 0	/* flush the I+D tlb */