arm/arm/cpufunc_asm_sheeva.S

50 	mcr	p15, 0, r1, c7, c5, 0	/* Invalidate ICache */
54 	mcr	p15, 1, r1, c15, c9, 0	/* Clean L2 */
55 	mcr	p15, 1, r1, c15, c11, 0	/* Invalidate L2 */
60 	mcr	p15, 0, r1, c7, c10, 4	/* drain the write buffer */
62 	mcr	p15, 0, r0, c2, c0, 0	/* load new TTB */
64 	mcr	p15, 0, r0, c8, c7, 0	/* invalidate I+D TLBs */
93 	mcr	p15, 5, r0, c15, c15, 0	/* Clean and inv zone start address */
94 	mcr	p15, 5, r2, c15, c15, 1	/* Clean and inv zone end address */
106 	mcr	p15, 0, r0, c7, c10, 4	/* drain the write buffer */
136 	mcr	p15, 5, r0, c15, c15, 0	/* Clean and inv zone start address */
137 	mcr	p15, 5, r2, c15, c15, 1	/* Clean and inv zone end address */
145 	mcr	p15, 0, r0, c7, c5, 1
158 	mcr	p15, 0, r0, c7, c10, 4	/* drain the write buffer */
188 	mcr	p15, 5, r0, c15, c14, 0	/* Inv zone start address */
189 	mcr	p15, 5, r2, c15, c14, 1	/* Inv zone end address */
201 	mcr	p15, 0, r0, c7, c10, 4	/* drain the write buffer */
231 	mcr	p15, 5, r0, c15, c13, 0	/* Clean zone start address */
232 	mcr	p15, 5, r2, c15, c13, 1	/* Clean zone end address */
244 	mcr	p15, 0, r0, c7, c10, 4	/* drain the write buffer */
274 	mcr	p15, 1, r0, c15, c9, 4	/* Clean L2 zone start address */
275 	mcr	p15, 1, r2, c15, c9, 5	/* Clean L2 zone end address */
276 	mcr	p15, 1, r0, c15, c11, 4	/* Inv L2 zone start address */
277 	mcr	p15, 1, r2, c15, c11, 5	/* Inv L2 zone end address */
289 	mcr	p15, 0, r0, c7, c10, 4	/* drain the write buffer */
319 	mcr	p15, 1, r0, c15, c11, 4	/* Inv L2 zone start address */
320 	mcr	p15, 1, r2, c15, c11, 5	/* Inv L2 zone end address */
332 	mcr	p15, 0, r0, c7, c10, 4	/* drain the write buffer */
362 	mcr	p15, 1, r0, c15, c9, 4	/* Clean L2 zone start address */
363 	mcr	p15, 1, r2, c15, c9, 5	/* Clean L2 zone end address */
375 	mcr	p15, 0, r0, c7, c10, 4	/* drain the write buffer */
387 	mcr	p15, 1, r0, c15, c9, 0	/* Clean L2 */
388 	mcr	p15, 1, r0, c15, c11, 0	/* Invalidate L2 */
392 	mcr	p15, 0, r0, c7, c10, 4	/* drain the write buffer */
417 	mcr	p15, 0, r0, c7, c10, 4	/* Drain write buffer */
418 	mcr	p15, 0, r0, c7, c0, 4	/* Wait for interrupt */