Lines Matching refs:mcr
77 mcr CP15_TTBR0(r0)
80 mcr CP15_TLBIALLIS
82 mcr CP15_TLBIALL
92 mcr CP15_TLBIALLIS
93 mcr CP15_BPIALLIS
95 mcr CP15_TLBIALL
96 mcr CP15_BPIALL
107 mcr CP15_TLBIMVAAIS(r0)
108 mcr CP15_BPIALLIS
110 mcr CP15_TLBIMVA(r0)
111 mcr CP15_BPIALL
156 mcr CP15_DCCISW(r6)
175 mcr CP15_ICIALLUIS
177 mcr CP15_ICIALLU
193 mcr CP15_DCCMVAC(r0)
209 mcr CP15_DCCIMVAC(r0)
229 mcr CP15_DCIMVAC(r0)
245 mcr CP15_ICIMVAU(r0)
246 mcr CP15_DCCIMVAC(r0)
263 mcr CP15_DCCMVAC(r0)
264 mcr CP15_ICIMVAU(r0)
283 mcr CP15_TTBR0(r0)
286 mcr CP15_TLBIALLIS
288 mcr CP15_TLBIALL
317 mcr CP15_CSSELR(r0) @ set cache level to L1
337 1: mcr CP15_DCISW(r3) @ invalidate line
347 mcr CP15_ICIALLU @ invalidate instruction+branch cache