Lines Matching refs:mcr
1233 uint16_t mcr;
1238 mcr = CSR_READ_2(sc, VTE_MCR0);
1239 mcr &= ~(MCR0_FC_ENB | MCR0_FULL_DUPLEX);
1241 mcr |= MCR0_FULL_DUPLEX;
1244 mcr |= MCR0_FC_ENB;
1252 mcr |= MCR0_FC_ENB;
1255 CSR_WRITE_2(sc, VTE_MCR0, mcr);
1604 uint16_t mcr;
1607 mcr = CSR_READ_2(sc, VTE_MCR1);
1608 CSR_WRITE_2(sc, VTE_MCR1, mcr | MCR1_MAC_RESET);
1615 device_printf(sc->vte_dev, "reset timeout(0x%04x)!\n", mcr);
1824 uint16_t mcr;
1830 mcr = CSR_READ_2(sc, VTE_MCR0);
1831 if ((mcr & (MCR0_RX_ENB | MCR0_TX_ENB)) !=
1833 mcr |= MCR0_RX_ENB | MCR0_TX_ENB;
1834 CSR_WRITE_2(sc, VTE_MCR0, mcr);
1836 mcr = CSR_READ_2(sc, VTE_MCR0);
1837 if ((mcr & (MCR0_RX_ENB | MCR0_TX_ENB)) ==
1844 "could not enable RX/TX MAC(0x%04x)!\n", mcr);
1851 uint16_t mcr;
1857 mcr = CSR_READ_2(sc, VTE_MCR0);
1858 if ((mcr & (MCR0_RX_ENB | MCR0_TX_ENB)) != 0) {
1859 mcr &= ~(MCR0_RX_ENB | MCR0_TX_ENB);
1860 CSR_WRITE_2(sc, VTE_MCR0, mcr);
1862 mcr = CSR_READ_2(sc, VTE_MCR0);
1863 if ((mcr & (MCR0_RX_ENB | MCR0_TX_ENB)) == 0)
1869 "could not disable RX/TX MAC(0x%04x)!\n", mcr);
1964 uint16_t mchash[4], mcr;
1978 mcr = CSR_READ_2(sc, VTE_MCR0);
1979 mcr &= ~(MCR0_PROMISC | MCR0_MULTICAST);
1980 mcr |= MCR0_BROADCAST_DIS;
1982 mcr &= ~MCR0_BROADCAST_DIS;
1985 mcr |= MCR0_PROMISC;
1987 mcr |= MCR0_MULTICAST;
2020 mcr |= MCR0_MULTICAST;
2037 CSR_WRITE_2(sc, VTE_MCR0, mcr);