MFC r327222:

Add a new ARM kernel option, LOCORE_MAP_MB, to control the size of the
kernel VA mapping in the temporary page tables set up by locore-v6.S.

The number used to be hard-coded to 64MB, which is still the default if
the kernel option is not specified. However, 64MB is insufficient for
using a large mdroot filesystem. The hard-coded number can't be safely
increased because too large a number may run into memory-mapped IO space
on some SoCs that must not be mapped as ordinary memory.

MFC r320056: arm: set appropriate section flags for .init_pagetable

The arm kernel linker scripts place the .init_pagetable section in .bss,
but .init_pagetable had no section flags set, and so did not match the
expected flags for .bss.

GNU ld silently ignores this case, but lld reports an error:

ld: error: incompatible section flags for .bss
>>> locore.o:(.init_pagetable): 0x0
>>> output section .bss: 0x3

PR: 220055
Sponsored by: The FreeBSD Foundation

MFC r312292, r313573:

Stop including sys/types.h from arm's machine/atomic.h, fix the places
where atomic.h was being included without ensuring that types.h (via
param.h) was included first, as required by atomic(9).

Remove arm's cpuconf.h, and references to it, after moving a few lines from
it into pmap-v4.h where they are used. Other than those few lines of
support for different MMU types, nothing in cpuconf.h has been used in our
code for quite a while.
The file existed to set up a variety of symbols to describe the
architecture. Over the past few years we have converted all of our source
to use the new architecture symbols standardized by ARM Inc, and predefined
by both clang and gcc.

MFC r306754:

ARM: Remove unused variable. Not a functional change.

Copy head@r302406 to stable/11 as part of the 11.0-RELEASE cycle.
Prune svn:mergeinfo from the new branch, as nothing has been merged
here.

Additional commits post-branch will follow.

Approved by: re (implicit)
Sponsored by: The FreeBSD Foundation

Disable alignment faults on armv6, adjust various alignment-related macros
to match the new state of affairs. The hardware we support has always been
able to do unaligned accesses, we've just never enabled it until now.

This brings FreeBSD into line with all the other major OSes, and should help
with the growing volume of 3rd-party software that assumes unaligned access
will just work on armv6 and armv7.

Include machine/acle-compat.h in cdefs.h on arm if the compiler doesn't
have ACLE support built in. The ACLE (ARM C Language Extensions) defines
a set of standardized symbols which indicate the architecture version and
features available. ACLE support is built in to modern compilers (both
clang and gcc), but absent from gcc prior to 4.4.

ARM (the company) provides the acle-compat.h header file to define the
right symbols for older versions of gcc. Basically, acle-compat.h does
for arm about the same thing cdefs.h does for freebsd: defines
standardized macros that work no matter which compiler you use. If ARM
hadn't provided this file we would have ended up with a big #ifdef __arm__
section in cdefs.h with our own compatibility shims.

Remove #include <machine/acle-compat.h> from the zillion other places (an
ever-growing list) that it appears. Since style(9) requires sys/types.h
or sys/param.h early in the include list, and both of those lead to
including cdefs.h, only a couple special cases still need to include
acle-compat.h directly.

Loves it: imp

Rename pte.h to pte-v4.h and start including directly either pte-v4.h
or pte-v6.h in files which needs it.

There are quite internal definitions in pte-v4.h and pte-v6.h headers
specific for corresponding pmap implementation. These headers should be
included only in very few files and an intention is to not hide for
which implementation such files are.

Further, sys/arm/arm/elf_trampoline.c is an example of file which
uses armv4 like pmap implementation for both armv4 and armv6 platforms.
This is another reason why pte.h which includes specific header
according to __ARM_ARCH is not created.

Do not use PMAP_DOMAIN_KERNEL definition for __ARM_ARCH >= 6 as domains
are not utilized there. Only domain #0 is used and there is no reference
to it in the whole pmap-v6.c. Thus initialize domain access register in
locore-v6.c without reference too.

ARM: Set UNAL_ENABLE bit in SCTLR CP15 register. This bit is RAO/SBOP
for ARMv7. For ARMv6, it controls ARMv5 compatible alignment support.
This bit have no effect until unaligned access is enabled.

ARM: remove old pmap-v6 code. The new pmap-v6 is mature enough, and
dual implementation is showstopper for major cleanup.

This patch only removes old code from tree. Cleanups will follow asap.

Bring some of the recent locore-v4.S improvements into locore-V6...

- Map all 4GB as VA=PA so that args passed in from a bootloader can
be accessed regardless of where they are.
- Figure out the kernel load address by directly masking the PC rather
then by doing pc-relative math on the _start symbol.
- For EARLY_PRINTF support, map device memory as uncacheable (no-op for
ARM_NEW_PMAP because all TEX types resolve to uncacheable).

ARM: Improve robustness of locore_v6.S and fix errors.
- boot page table is not allocated in data section, so must be
cleared before use
- map only one section (1 MB) for SOCDEV mapping (*)
- DSB must be used for ensuring of finishing TLB operations
- Invalidate BTB when appropriate

PR: 198360
Reported by: Daisuke Aoyama <aoyama at peach.ne.jp> (*)
Approved by: kib (mentor)

Fix LEAVE_HYP macro: spsr is not guaranteed to contain valid value at this
point, e.g. on RaspberryPi 2 when control is passed from loader to kernel
it contains garbage. So we use cpsr as a base for new cpsr value: if we
have reached this point it means current value is OK

Reviewed by: andrew

Clean up the style of the LEAVE_HYP macro.

Leave hypervisor mode upon startup on ARMv7

If ARMv7 boots in HYP mode, switch to SVC32.

Reviewed by: ian
Submitted by: Wojciech Macek <wma@semihalf.com>
Jakub Palider <jpa@semihalf.com>
Obtained from: Semihalf
Sponsored by: Annapurna Labs
Differential Revision: https://reviews.freebsd.org/D1810

Write to the PRRR (Primary Region Remap Register) rather than reading from
it during the early boot.

Found By: Patrick Wildt <patrick@bitrig.org>
Sponsored by: ABT Systems Ltd

Cleanup a little more:
- Remove whitespace at the end of lines
- Use a tab after instructions, not spaces

Fix the style of locore-v4.S and locore-v6.S to help find any common code.

Minor cleanups, comment changes. No need to load 3 values when setting up
the stack for secondary cores, the other two values are only used for zeroing
bss on the primary core. No need to store the size of the stack at the
top of the stack (seems to be a leftover instruction from some cut-n-paste).

Fix alignment directives in arm asm code after clang 3.5 import.

The ancient gas we've been using interprets .align 0 as align to the
minimum required alignment for the current section. Clang's integrated
assembler interprets it as align to a byte boundary. Fortunately both
assemblers interpret a non-zero value as align to 2^N so just make sure
we have appropriate non-zero values everywhere.

Define a WFI macro that expands to the right form of wait-for-interrupt
depending on the architecture.

A couple small fixes to make clang 3.5 happy... Move END(sigcode) to the
end of the actual instruction sequence for the function but before some
misc data in the text segment. This eliminates a strange "size must be
constant" error from the integrated assembler. Also, the build_pagetables
function was missing an END(), but really the problem is that it shouldn't
have an ASENTRY() because it's not a function that needs to be a global
symbol with unwind info and all, it's just a little private subroutine
used in very early kernel init.

Change the order of operations for the initial cache setup. Turning off
the cache before clean/invalidate ensured that no new lines can come into
the cache or migrate between levels during the operation, but may not be
safe on some chips. Instead, if the cache was enabled on entry, do the
wbinv while it's still enabled, and then disable it and do a separate
invalidate pass. After the intitial writeback we know there are no
dirty lines left and no new dirty lines can be created as long as we
carefully avoid touching memory before turning the cache off. Add a
comment about that so no new code gets inserted between those points.

Rename locore.S to locore-v4.S and add a new locore-v6.S for starting up
armv6/7 systems. We need to use some new armv6/7 features at startup
and splitting the implemenations to separate files will be more maintainable
than adding even more #ifdef sections to locore.S.

Because of the standardized interfaces to cache and MMU operations in armv7,
we can tolerate the kernel being entered with caches enabled. This allows
running u-boot and loader(8) with caches enabled, and the performance
improvement can be dramatic (boot times can be cut from over a minute
to under 30 seconds). The new implementation also has more robust cache
and mmu sequences for launching AP cores, and it paves the way for
upcoming changes to the pmap code which will use the TEX remap feature.

Changes in mp_machdep.c work with the new behavior in locore-v6 mp_entry,
and also reuse the original boot-time page tables to get transitioned
from physical to virtual addressing before installing the normal tables.

Submitted by Svatopluk Kraus and Michal Meloun with some changes by me.