Searched refs:gfx (Results 1 - 25 of 93) sorted by relevance

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/openbsd-current/sys/dev/pci/drm/amd/amdgpu/
H A Damdgpu_rlc.c40 if (adev->gfx.rlc.in_safe_mode[xcc_id])
44 if (!adev->gfx.rlc.funcs->is_rlc_enabled(adev))
50 adev->gfx.rlc.funcs->set_safe_mode(adev, xcc_id);
51 adev->gfx.rlc.in_safe_mode[xcc_id] = true;
65 if (!(adev->gfx.rlc.in_safe_mode[xcc_id]))
69 if (!adev->gfx.rlc.funcs->is_rlc_enabled(adev))
75 adev->gfx.rlc.funcs->unset_safe_mode(adev, xcc_id);
76 adev->gfx.rlc.in_safe_mode[xcc_id] = false;
100 &adev->gfx.rlc.save_restore_obj,
101 &adev->gfx
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H A Damdgpu_gfx.c33 /* delay 0.1 second to enable gfx off feature */
47 bit += mec * adev->gfx.mec.num_pipe_per_mec
48 * adev->gfx.mec.num_queue_per_pipe;
49 bit += pipe * adev->gfx.mec.num_queue_per_pipe;
58 *queue = bit % adev->gfx.mec.num_queue_per_pipe;
59 *pipe = (bit / adev->gfx.mec.num_queue_per_pipe)
60 % adev->gfx.mec.num_pipe_per_mec;
61 *mec = (bit / adev->gfx.mec.num_queue_per_pipe)
62 / adev->gfx.mec.num_pipe_per_mec;
70 adev->gfx
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H A Dgfx_v11_0.c42 #include "ivsrcid/gfx/irqsrcs_gfx_11_0_0.h"
199 if (adev->enable_mes && !adev->gfx.kiq[0].ring.sched.ready) {
267 adev->gfx.kiq[0].pmf = &gfx_v11_0_kiq_pm4_funcs;
443 amdgpu_ucode_release(&adev->gfx.pfp_fw);
444 amdgpu_ucode_release(&adev->gfx.me_fw);
445 amdgpu_ucode_release(&adev->gfx.rlc_fw);
446 amdgpu_ucode_release(&adev->gfx.mec_fw);
448 kfree(adev->gfx.rlc.register_list_format);
480 if ((adev->gfx.me_fw_version >= 1505) &&
481 (adev->gfx
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H A Dgfx_v6_0.c341 err = amdgpu_ucode_request(adev, &adev->gfx.pfp_fw, fw_name);
344 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
345 adev->gfx.pfp_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
346 adev->gfx.pfp_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
349 err = amdgpu_ucode_request(adev, &adev->gfx.me_fw, fw_name);
352 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
353 adev->gfx.me_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
354 adev->gfx.me_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
357 err = amdgpu_ucode_request(adev, &adev->gfx.ce_fw, fw_name);
360 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx
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H A Dgfx_v8_0.c927 amdgpu_ucode_release(&adev->gfx.pfp_fw);
928 amdgpu_ucode_release(&adev->gfx.me_fw);
929 amdgpu_ucode_release(&adev->gfx.ce_fw);
930 amdgpu_ucode_release(&adev->gfx.rlc_fw);
931 amdgpu_ucode_release(&adev->gfx.mec_fw);
934 amdgpu_ucode_release(&adev->gfx.mec2_fw);
936 kfree(adev->gfx.rlc.register_list_format);
986 err = amdgpu_ucode_request(adev, &adev->gfx.pfp_fw, fw_name);
989 err = amdgpu_ucode_request(adev, &adev->gfx.pfp_fw, fw_name);
993 err = amdgpu_ucode_request(adev, &adev->gfx
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H A Dgfx_v7_0.c889 amdgpu_ucode_release(&adev->gfx.pfp_fw);
890 amdgpu_ucode_release(&adev->gfx.me_fw);
891 amdgpu_ucode_release(&adev->gfx.ce_fw);
892 amdgpu_ucode_release(&adev->gfx.mec_fw);
893 amdgpu_ucode_release(&adev->gfx.mec2_fw);
894 amdgpu_ucode_release(&adev->gfx.rlc_fw);
938 err = amdgpu_ucode_request(adev, &adev->gfx.pfp_fw, fw_name);
943 err = amdgpu_ucode_request(adev, &adev->gfx.me_fw, fw_name);
948 err = amdgpu_ucode_request(adev, &adev->gfx.ce_fw, fw_name);
953 err = amdgpu_ucode_request(adev, &adev->gfx
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H A Dgfx_v9_0.c46 #include "ivsrcid/gfx/irqsrcs_gfx_9_0.h"
893 adev->gfx.kiq[0].pmf = &gfx_v9_0_kiq_pm4_funcs;
1083 amdgpu_ucode_release(&adev->gfx.pfp_fw);
1084 amdgpu_ucode_release(&adev->gfx.me_fw);
1085 amdgpu_ucode_release(&adev->gfx.ce_fw);
1086 amdgpu_ucode_release(&adev->gfx.rlc_fw);
1087 amdgpu_ucode_release(&adev->gfx.mec_fw);
1088 amdgpu_ucode_release(&adev->gfx.mec2_fw);
1090 kfree(adev->gfx.rlc.register_list_format);
1095 adev->gfx
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H A Dgfx_v9_4_3.c34 #include "ivsrcid/gfx/irqsrcs_gfx_9_0.h"
187 num_xcc = NUM_XCC(adev->gfx.xcc_mask);
189 adev->gfx.kiq[i].pmf = &gfx_v9_4_3_kiq_pm4_funcs;
196 num_xcc = NUM_XCC(adev->gfx.xcc_mask);
343 mutex_lock(&adev->gfx.gpu_clock_mutex);
347 mutex_unlock(&adev->gfx.gpu_clock_mutex);
354 amdgpu_ucode_release(&adev->gfx.pfp_fw);
355 amdgpu_ucode_release(&adev->gfx.me_fw);
356 amdgpu_ucode_release(&adev->gfx.ce_fw);
357 amdgpu_ucode_release(&adev->gfx
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H A Damdgpu_amdkfd.c157 .num_pipe_per_mec = adev->gfx.mec.num_pipe_per_mec,
158 .num_queue_per_pipe = adev->gfx.mec.num_queue_per_pipe,
171 adev->gfx.mec_bitmap[0].queue_bitmap,
178 * adev->gfx.mec.num_pipe_per_mec
179 * adev->gfx.mec.num_queue_per_pipe;
395 return adev->gfx.pfp_fw_version;
398 return adev->gfx.me_fw_version;
401 return adev->gfx.ce_fw_version;
404 return adev->gfx.mec_fw_version;
407 return adev->gfx
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H A Damdgpu_kms.c225 fw_info->ver = adev->gfx.me_fw_version;
226 fw_info->feature = adev->gfx.me_feature_version;
229 fw_info->ver = adev->gfx.pfp_fw_version;
230 fw_info->feature = adev->gfx.pfp_feature_version;
233 fw_info->ver = adev->gfx.ce_fw_version;
234 fw_info->feature = adev->gfx.ce_feature_version;
237 fw_info->ver = adev->gfx.rlc_fw_version;
238 fw_info->feature = adev->gfx.rlc_feature_version;
241 fw_info->ver = adev->gfx.rlc_srlc_fw_version;
242 fw_info->feature = adev->gfx
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H A Damdgpu_atomfirmware.c791 adev->gfx.config.max_shader_engines = gfx_info->v24.max_shader_engines;
792 adev->gfx.config.max_cu_per_sh = gfx_info->v24.max_cu_per_sh;
793 adev->gfx.config.max_sh_per_se = gfx_info->v24.max_sh_per_se;
794 adev->gfx.config.max_backends_per_se = gfx_info->v24.max_backends_per_se;
795 adev->gfx.config.max_texture_channel_caches = gfx_info->v24.max_texture_channel_caches;
796 adev->gfx.config.max_gprs = le16_to_cpu(gfx_info->v24.gc_num_gprs);
797 adev->gfx.config.max_gs_threads = gfx_info->v24.gc_num_max_gs_thds;
798 adev->gfx.config.gs_vgt_table_depth = gfx_info->v24.gc_gs_table_depth;
799 adev->gfx.config.gs_prim_buffer_depth =
801 adev->gfx
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H A Damdgpu_ucode.c689 FW_VERSION_ATTR(me_fw_version, 0444, gfx.me_fw_version);
690 FW_VERSION_ATTR(pfp_fw_version, 0444, gfx.pfp_fw_version);
691 FW_VERSION_ATTR(ce_fw_version, 0444, gfx.ce_fw_version);
692 FW_VERSION_ATTR(rlc_fw_version, 0444, gfx.rlc_fw_version);
693 FW_VERSION_ATTR(rlc_srlc_fw_version, 0444, gfx.rlc_srlc_fw_version);
694 FW_VERSION_ATTR(rlc_srlg_fw_version, 0444, gfx.rlc_srlg_fw_version);
695 FW_VERSION_ATTR(rlc_srls_fw_version, 0444, gfx.rlc_srls_fw_version);
696 FW_VERSION_ATTR(mec_fw_version, 0444, gfx.mec_fw_version);
697 FW_VERSION_ATTR(mec2_fw_version, 0444, gfx.mec2_fw_version);
698 FW_VERSION_ATTR(imu_fw_version, 0444, gfx
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H A Damdgpu_debugfs.c130 if ((sh_bank != 0xFFFFFFFF && sh_bank >= adev->gfx.config.max_sh_per_se) ||
131 (se_bank != 0xFFFFFFFF && se_bank >= adev->gfx.config.max_shader_engines)) {
256 if ((rd->id.grbm.sh != 0xFFFFFFFF && rd->id.grbm.sh >= adev->gfx.config.max_sh_per_se) ||
257 (rd->id.grbm.se != 0xFFFFFFFF && rd->id.grbm.se >= adev->gfx.config.max_shader_engines)) {
433 if (adev->gfx.funcs->read_wave_data)
434 adev->gfx.funcs->read_wave_data(adev, rd->id.xcc_id, rd->id.simd, rd->id.wave, data, &x);
438 if (adev->gfx.funcs->read_wave_vgprs)
439 adev->gfx.funcs->read_wave_vgprs(adev, rd->id.xcc_id, rd->id.simd, rd->id.wave, rd->id.gpr.thread, *pos, size>>2, data);
441 if (adev->gfx.funcs->read_wave_sgprs)
442 adev->gfx
[all...]
H A Damdgpu_discovery.c654 adev->gfx.xcc_mask &=
940 harvest = ((1 << inst) & adev->gfx.xcc_mask) == 0;
1242 adev->gfx.xcc_mask = 0;
1328 adev->gfx.xcc_mask |=
1453 adev->gfx.config.max_shader_engines = le32_to_cpu(gc_info->v1.gc_num_se);
1454 adev->gfx.config.max_cu_per_sh = 2 * (le32_to_cpu(gc_info->v1.gc_num_wgp0_per_sa) +
1456 adev->gfx.config.max_sh_per_se = le32_to_cpu(gc_info->v1.gc_num_sa_per_se);
1457 adev->gfx.config.max_backends_per_se = le32_to_cpu(gc_info->v1.gc_num_rb_per_se);
1458 adev->gfx.config.max_texture_channel_caches = le32_to_cpu(gc_info->v1.gc_num_gl2c);
1459 adev->gfx
[all...]
H A Dgfx_v10_0.c40 #include "ivsrcid/gfx/irqsrcs_gfx_10_1.h"
3557 if (adev->enable_mes && !adev->gfx.kiq[0].ring.sched.ready) {
3625 adev->gfx.kiq[0].pmf = &gfx_v10_0_kiq_pm4_funcs;
3880 amdgpu_ucode_release(&adev->gfx.pfp_fw);
3881 amdgpu_ucode_release(&adev->gfx.me_fw);
3882 amdgpu_ucode_release(&adev->gfx.ce_fw);
3883 amdgpu_ucode_release(&adev->gfx.rlc_fw);
3884 amdgpu_ucode_release(&adev->gfx.mec_fw);
3885 amdgpu_ucode_release(&adev->gfx.mec2_fw);
3887 kfree(adev->gfx
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H A Dimu_v11_0.c53 err = amdgpu_ucode_request(adev, &adev->gfx.imu_fw, fw_name);
56 imu_hdr = (const struct imu_firmware_header_v1_0 *)adev->gfx.imu_fw->data;
57 adev->gfx.imu_fw_version = le32_to_cpu(imu_hdr->header.ucode_version);
58 //adev->gfx.imu_feature_version = le32_to_cpu(imu_hdr->ucode_feature_version);
63 info->fw = adev->gfx.imu_fw;
68 info->fw = adev->gfx.imu_fw;
78 amdgpu_ucode_release(&adev->gfx.imu_fw);
90 if (!adev->gfx.imu_fw)
93 hdr = (const struct imu_firmware_header_v1_0 *)adev->gfx.imu_fw->data;
96 fw_data = (const __le32 *)(adev->gfx
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H A Damdgpu_amdkfd_gfx_v9.c66 uint32_t mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1;
67 uint32_t pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec);
75 unsigned int bit = pipe_id * adev->gfx.mec.num_queue_per_pipe +
115 * need to do this twice, once for gfx and once for mmhub
166 mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1;
167 pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec);
307 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq[inst].ring;
316 mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1;
317 pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec);
322 spin_lock(&adev->gfx
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H A Damdgpu_amdkfd_gfx_v10_3.c60 uint32_t mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1;
61 uint32_t pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec);
69 unsigned int bit = pipe_id * adev->gfx.mec.num_queue_per_pipe +
115 mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1;
116 pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec);
197 mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1;
198 pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec);
280 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq[0].ring;
289 mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1;
290 pipe = (pipe_id % adev->gfx
[all...]
H A Damdgpu_mes_ctx.h63 /* gfx csa */
75 } __aligned(PAGE_SIZE) gfx[AMDGPU_MES_CTX_MAX_GFX_RINGS]; member in struct:amdgpu_mes_ctx_meta_data
H A Damdgpu_cgs.c173 fw_version = adev->gfx.ce_fw_version;
176 fw_version = adev->gfx.pfp_fw_version;
179 fw_version = adev->gfx.me_fw_version;
182 fw_version = adev->gfx.mec_fw_version;
185 fw_version = adev->gfx.mec_fw_version;
188 fw_version = adev->gfx.mec_fw_version;
191 fw_version = adev->gfx.rlc_fw_version;
H A Damdgpu_virt.c78 struct amdgpu_kiq *kiq = &adev->gfx.kiq[0];
552 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_ME, adev->gfx.me_fw_version);
553 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_PFP, adev->gfx.pfp_fw_version);
554 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_CE, adev->gfx.ce_fw_version);
555 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_RLC, adev->gfx.rlc_fw_version);
556 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_RLC_SRLC, adev->gfx.rlc_srlc_fw_version);
557 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_RLC_SRLG, adev->gfx.rlc_srlg_fw_version);
558 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_RLC_SRLS, adev->gfx.rlc_srls_fw_version);
559 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_MEC, adev->gfx.mec_fw_version);
560 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_MEC2, adev->gfx
[all...]
H A Daqua_vanjaram.c274 { GC_HWIP, adev->gfx.xcc_mask },
321 num_xcc = NUM_XCC(xcp_mgr->adev->gfx.xcc_mask);
380 num_xcc_xcp = adev->gfx.num_xcc_per_xcp;
414 num_xcc = NUM_XCC(xcp_mgr->adev->gfx.xcc_mask);
438 num_xcc = NUM_XCC(adev->gfx.xcc_mask);
499 num_xcc = NUM_XCC(adev->gfx.xcc_mask);
524 if (adev->gfx.funcs->switch_partition_mode)
525 adev->gfx.funcs->switch_partition_mode(xcp_mgr->adev,
544 *mem_id = xcc_id / adev->gfx.num_xcc_per_xcp;
H A Dvcn_v1_0.c353 adev->gfx.config.gb_addr_config);
355 adev->gfx.config.gb_addr_config);
357 adev->gfx.config.gb_addr_config);
359 adev->gfx.config.gb_addr_config);
361 adev->gfx.config.gb_addr_config);
363 adev->gfx.config.gb_addr_config);
365 adev->gfx.config.gb_addr_config);
367 adev->gfx.config.gb_addr_config);
369 adev->gfx.config.gb_addr_config);
371 adev->gfx
[all...]
H A Dgfx_v11_0_3.c28 #include "ivsrcid/gfx/irqsrcs_gfx_11_0_0.h"
57 ras_if = adev->gfx.ras_if;
H A Damdgpu_amdkfd_gfx_v11.c58 uint32_t mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1;
59 uint32_t pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec);
67 unsigned int bit = pipe_id * adev->gfx.mec.num_queue_per_pipe +
111 mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1;
112 pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec);
182 mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1;
183 pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec);
265 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq[0].ring;
274 mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1;
275 pipe = (pipe_id % adev->gfx
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