Lines Matching refs:gfx
33 /* delay 0.1 second to enable gfx off feature */
47 bit += mec * adev->gfx.mec.num_pipe_per_mec
48 * adev->gfx.mec.num_queue_per_pipe;
49 bit += pipe * adev->gfx.mec.num_queue_per_pipe;
58 *queue = bit % adev->gfx.mec.num_queue_per_pipe;
59 *pipe = (bit / adev->gfx.mec.num_queue_per_pipe)
60 % adev->gfx.mec.num_pipe_per_mec;
61 *mec = (bit / adev->gfx.mec.num_queue_per_pipe)
62 / adev->gfx.mec.num_pipe_per_mec;
70 adev->gfx.mec_bitmap[xcc_id].queue_bitmap);
78 bit += me * adev->gfx.me.num_pipe_per_me
79 * adev->gfx.me.num_queue_per_pipe;
80 bit += pipe * adev->gfx.me.num_queue_per_pipe;
89 *queue = bit % adev->gfx.me.num_queue_per_pipe;
90 *pipe = (bit / adev->gfx.me.num_queue_per_pipe)
91 % adev->gfx.me.num_pipe_per_me;
92 *me = (bit / adev->gfx.me.num_queue_per_pipe)
93 / adev->gfx.me.num_pipe_per_me;
100 adev->gfx.me.queue_bitmap);
152 return amdgpu_async_gfx_ring && adev->gfx.me.num_pipe_per_me > 1;
171 return adev->gfx.mec.num_mec > 1;
181 * have more than one gfx pipe.
184 adev->gfx.num_gfx_rings > 1 && pipe == 1 && queue == 0) {
189 if (ring == &adev->gfx.gfx_ring[bit])
202 if (adev->gfx.num_compute_rings > 1 &&
203 ring == &adev->gfx.compute_ring[0])
213 int max_queues_per_mec = min(adev->gfx.mec.num_pipe_per_mec *
214 adev->gfx.mec.num_queue_per_pipe,
215 adev->gfx.num_compute_rings);
216 int num_xcc = adev->gfx.xcc_mask ? NUM_XCC(adev->gfx.xcc_mask) : 1;
223 pipe = i % adev->gfx.mec.num_pipe_per_mec;
224 queue = (i / adev->gfx.mec.num_pipe_per_mec) %
225 adev->gfx.mec.num_queue_per_pipe;
227 set_bit(pipe * adev->gfx.mec.num_queue_per_pipe + queue,
228 adev->gfx.mec_bitmap[j].queue_bitmap);
235 set_bit(i, adev->gfx.mec_bitmap[j].queue_bitmap);
241 bitmap_weight(adev->gfx.mec_bitmap[j].queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES));
249 int max_queues_per_me = adev->gfx.me.num_pipe_per_me *
250 adev->gfx.me.num_queue_per_pipe;
256 pipe = i % adev->gfx.me.num_pipe_per_me;
257 queue = (i / adev->gfx.me.num_pipe_per_me) %
258 adev->gfx.me.num_queue_per_pipe;
260 set_bit(pipe * adev->gfx.me.num_queue_per_pipe + queue,
261 adev->gfx.me.queue_bitmap);
265 set_bit(i, adev->gfx.me.queue_bitmap);
269 adev->gfx.num_gfx_rings =
270 bitmap_weight(adev->gfx.me.queue_bitmap, AMDGPU_MAX_GFX_QUEUES);
279 queue_bit = adev->gfx.mec.num_mec
280 * adev->gfx.mec.num_pipe_per_mec
281 * adev->gfx.mec.num_queue_per_pipe;
284 if (test_bit(queue_bit, adev->gfx.mec_bitmap[xcc_id].queue_bitmap))
312 struct amdgpu_kiq *kiq = &adev->gfx.kiq[xcc_id];
349 struct amdgpu_kiq *kiq = &adev->gfx.kiq[xcc_id];
359 struct amdgpu_kiq *kiq = &adev->gfx.kiq[xcc_id];
380 /* create MQD for each compute/gfx queue */
385 struct amdgpu_kiq *kiq = &adev->gfx.kiq[xcc_id];
424 for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
425 ring = &adev->gfx.gfx_ring[i];
437 adev->gfx.me.mqd_backup[i] = kmalloc(mqd_size, GFP_KERNEL);
438 if (!adev->gfx.me.mqd_backup[i]) {
447 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
448 j = i + xcc_id * adev->gfx.num_compute_rings;
449 ring = &adev->gfx.compute_ring[j];
461 adev->gfx.mec.mqd_backup[j] = kmalloc(mqd_size, GFP_KERNEL);
462 if (!adev->gfx.mec.mqd_backup[j]) {
476 struct amdgpu_kiq *kiq = &adev->gfx.kiq[xcc_id];
479 for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
480 ring = &adev->gfx.gfx_ring[i];
481 kfree(adev->gfx.me.mqd_backup[i]);
488 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
489 j = i + xcc_id * adev->gfx.num_compute_rings;
490 ring = &adev->gfx.compute_ring[j];
491 kfree(adev->gfx.mec.mqd_backup[j]);
506 struct amdgpu_kiq *kiq = &adev->gfx.kiq[xcc_id];
516 adev->gfx.num_compute_rings)) {
521 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
522 j = i + xcc_id * adev->gfx.num_compute_rings;
524 &adev->gfx.compute_ring[j],
537 struct amdgpu_kiq *kiq = &adev->gfx.kiq[xcc_id];
548 adev->gfx.num_gfx_rings)) {
553 for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
554 j = i + xcc_id * adev->gfx.num_gfx_rings;
556 &adev->gfx.gfx_ring[j],
561 if (adev->gfx.kiq[0].ring.sched.ready && !adev->job_hang)
583 struct amdgpu_kiq *kiq = &adev->gfx.kiq[xcc_id];
592 if (!test_bit(i, adev->gfx.mec_bitmap[xcc_id].queue_bitmap))
612 adev->gfx.num_compute_rings +
624 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
625 j = i + xcc_id * adev->gfx.num_compute_rings;
627 &adev->gfx.compute_ring[j]);
640 struct amdgpu_kiq *kiq = &adev->gfx.kiq[xcc_id];
653 adev->gfx.num_gfx_rings);
660 for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
661 j = i + xcc_id * adev->gfx.num_gfx_rings;
663 &adev->gfx.gfx_ring[j]);
675 /* amdgpu_gfx_off_ctrl - Handle gfx off feature enable/disable
678 * @bool enable true: enable gfx off feature, false: disable gfx off feature
680 * 1. gfx off feature will be enabled by gfx ip after gfx cg gp enabled.
681 * 2. other client can send request to disable gfx off feature, the request should be honored.
682 * 3. other client can cancel their request of disable gfx off feature
683 * 4. other client should not send request to enable gfx off feature before disable gfx off feature.
693 mutex_lock(&adev->gfx.gfx_off_mutex);
700 if (WARN_ON_ONCE(adev->gfx.gfx_off_req_count == 0))
703 adev->gfx.gfx_off_req_count--;
705 if (adev->gfx.gfx_off_req_count == 0 &&
706 !adev->gfx.gfx_off_state) {
711 adev->gfx.gfx_off_state = true;
713 schedule_delayed_work(&adev->gfx.gfx_off_delay_work,
718 if (adev->gfx.gfx_off_req_count == 0) {
719 cancel_delayed_work_sync(&adev->gfx.gfx_off_delay_work);
721 if (adev->gfx.gfx_off_state &&
723 adev->gfx.gfx_off_state = false;
725 if (adev->gfx.funcs->init_spm_golden) {
733 adev->gfx.gfx_off_req_count++;
737 mutex_unlock(&adev->gfx.gfx_off_mutex);
744 mutex_lock(&adev->gfx.gfx_off_mutex);
748 mutex_unlock(&adev->gfx.gfx_off_mutex);
757 mutex_lock(&adev->gfx.gfx_off_mutex);
761 mutex_unlock(&adev->gfx.gfx_off_mutex);
770 mutex_lock(&adev->gfx.gfx_off_mutex);
774 mutex_unlock(&adev->gfx.gfx_off_mutex);
784 mutex_lock(&adev->gfx.gfx_off_mutex);
788 mutex_unlock(&adev->gfx.gfx_off_mutex);
805 if (adev->gfx.cp_ecc_error_irq.funcs) {
806 r = amdgpu_irq_get(adev, &adev->gfx.cp_ecc_error_irq, 0);
825 /* adev->gfx.ras is NULL, which means gfx does not
828 if (!adev->gfx.ras)
831 ras = adev->gfx.ras;
835 dev_err(adev->dev, "Failed to register gfx ras block!\n");
839 strlcpy(ras->ras_block.ras_comm.name, "gfx",
843 adev->gfx.ras_if = &ras->ras_block.ras_comm;
845 /* If not define special ras_late_init function, use gfx default ras_late_init */
859 if (adev->gfx.ras && adev->gfx.ras->poison_consumption_handler)
860 return adev->gfx.ras->poison_consumption_handler(adev, entry);
877 if (adev->gfx.ras && adev->gfx.ras->ras_block.hw_ops &&
878 adev->gfx.ras->ras_block.hw_ops->query_ras_error_count)
879 adev->gfx.ras->ras_block.hw_ops->query_ras_error_count(adev, err_data);
889 struct ras_common_if *ras_if = adev->gfx.ras_if;
910 int num_xcc = adev->gfx.xcc_mask ? NUM_XCC(adev->gfx.xcc_mask) : 1;
928 struct amdgpu_kiq *kiq = &adev->gfx.kiq[0];
996 struct amdgpu_kiq *kiq = &adev->gfx.kiq[0];
1074 adev->gfx.pfp_fw->data;
1075 adev->gfx.pfp_fw_version =
1077 adev->gfx.pfp_feature_version =
1079 ucode_fw = adev->gfx.pfp_fw;
1084 adev->gfx.pfp_fw->data;
1085 adev->gfx.pfp_fw_version =
1087 adev->gfx.pfp_feature_version =
1089 ucode_fw = adev->gfx.pfp_fw;
1095 adev->gfx.pfp_fw->data;
1096 ucode_fw = adev->gfx.pfp_fw;
1101 adev->gfx.me_fw->data;
1102 adev->gfx.me_fw_version =
1104 adev->gfx.me_feature_version =
1106 ucode_fw = adev->gfx.me_fw;
1111 adev->gfx.me_fw->data;
1112 adev->gfx.me_fw_version =
1114 adev->gfx.me_feature_version =
1116 ucode_fw = adev->gfx.me_fw;
1122 adev->gfx.me_fw->data;
1123 ucode_fw = adev->gfx.me_fw;
1128 adev->gfx.ce_fw->data;
1129 adev->gfx.ce_fw_version =
1131 adev->gfx.ce_feature_version =
1133 ucode_fw = adev->gfx.ce_fw;
1138 adev->gfx.mec_fw->data;
1139 adev->gfx.mec_fw_version =
1141 adev->gfx.mec_feature_version =
1143 ucode_fw = adev->gfx.mec_fw;
1149 adev->gfx.mec_fw->data;
1150 ucode_fw = adev->gfx.mec_fw;
1155 adev->gfx.mec2_fw->data;
1156 adev->gfx.mec2_fw_version =
1158 adev->gfx.mec2_feature_version =
1160 ucode_fw = adev->gfx.mec2_fw;
1166 adev->gfx.mec2_fw->data;
1167 ucode_fw = adev->gfx.mec2_fw;
1172 adev->gfx.mec_fw->data;
1173 adev->gfx.mec_fw_version =
1175 adev->gfx.mec_feature_version =
1177 ucode_fw = adev->gfx.mec_fw;
1185 adev->gfx.mec_fw->data;
1186 ucode_fw = adev->gfx.mec_fw;
1203 return !(xcc_id % (adev->gfx.num_xcc_per_xcp ?
1204 adev->gfx.num_xcc_per_xcp : 1));
1230 num_xcc = NUM_XCC(adev->gfx.xcc_mask);
1275 switch (NUM_XCC(adev->gfx.xcc_mask)) {