Lines Matching refs:gfx
889 amdgpu_ucode_release(&adev->gfx.pfp_fw);
890 amdgpu_ucode_release(&adev->gfx.me_fw);
891 amdgpu_ucode_release(&adev->gfx.ce_fw);
892 amdgpu_ucode_release(&adev->gfx.mec_fw);
893 amdgpu_ucode_release(&adev->gfx.mec2_fw);
894 amdgpu_ucode_release(&adev->gfx.rlc_fw);
938 err = amdgpu_ucode_request(adev, &adev->gfx.pfp_fw, fw_name);
943 err = amdgpu_ucode_request(adev, &adev->gfx.me_fw, fw_name);
948 err = amdgpu_ucode_request(adev, &adev->gfx.ce_fw, fw_name);
953 err = amdgpu_ucode_request(adev, &adev->gfx.mec_fw, fw_name);
959 err = amdgpu_ucode_request(adev, &adev->gfx.mec2_fw, fw_name);
965 err = amdgpu_ucode_request(adev, &adev->gfx.rlc_fw, fw_name);
990 ARRAY_SIZE(adev->gfx.config.tile_mode_array);
992 ARRAY_SIZE(adev->gfx.config.macrotile_mode_array);
996 tile = adev->gfx.config.tile_mode_array;
997 macrotile = adev->gfx.config.macrotile_mode_array;
999 switch (adev->gfx.config.mem_row_size_in_kb) {
1596 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se /
1597 adev->gfx.config.max_sh_per_se);
1639 unsigned sh_per_se = max_t(unsigned, adev->gfx.config.max_sh_per_se, 1);
1640 unsigned num_se = max_t(unsigned, adev->gfx.config.max_shader_engines, 1);
1756 u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se /
1757 adev->gfx.config.max_sh_per_se;
1761 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
1762 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
1765 active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) *
1771 adev->gfx.config.backend_enable_mask = active_rbs;
1772 adev->gfx.config.num_rbs = hweight32(active_rbs);
1774 num_rb_pipes = min_t(unsigned, adev->gfx.config.max_backends_per_se *
1775 adev->gfx.config.max_shader_engines, 16);
1779 if (!adev->gfx.config.backend_enable_mask ||
1780 adev->gfx.config.num_rbs >= num_rb_pipes) {
1785 adev->gfx.config.backend_enable_mask,
1790 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
1791 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
1793 adev->gfx.config.rb_config[i][j].rb_backend_disable =
1795 adev->gfx.config.rb_config[i][j].user_rb_backend_disable =
1797 adev->gfx.config.rb_config[i][j].raster_config =
1799 adev->gfx.config.rb_config[i][j].raster_config_1 =
1859 * Initialize all compute and user-gfx VMIDs to have no GDS, GWS, or OA
1874 adev->gfx.config.double_offchip_lds_buf = 1;
1882 * init the gfx constants such as the 3D engine, tiling configuration
1893 WREG32(mmGB_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
1894 WREG32(mmHDP_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
1895 WREG32(mmDMIF_ADDR_CALC, adev->gfx.config.gb_addr_config);
1979 ((adev->gfx.config.sc_prim_fifo_size_frontend << PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIFT) |
1980 (adev->gfx.config.sc_prim_fifo_size_backend << PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT) |
1981 (adev->gfx.config.sc_hiz_tile_fifo_size << PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT) |
1982 (adev->gfx.config.sc_earlyz_tile_fifo_size << PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT)));
2018 * gfx_v7_0_ring_test_ring - basic gfx ring test
2022 * Allocate a scratch register and write to it using the gfx ring (CIK).
2023 * Provides a basic gfx ring test to verify that the ring is working.
2105 * gfx_v7_0_ring_emit_fence_gfx - emit a fence on the gfx ring
2112 * Emits a fence sequence number on the gfx ring and flushes
2190 * on the gfx ring. IBs are usually generated by userspace
2193 * on the gfx ring for execution by the GPU.
2286 * Allocate an IB and execute it on the gfx ring (CIK).
2287 * Provides a basic gfx ring test to verify that IBs are working.
2334 * On CIK, gfx and compute now have independent command processors.
2337 * Gfx consists of a single ring and can process both gfx jobs and
2338 * compute jobs. The gfx CP consists of three microengines (ME):
2356 * gfx_v7_0_cp_gfx_enable - enable/disable the gfx CP MEs
2361 * Halts or unhalts the gfx MEs.
2375 * gfx_v7_0_cp_gfx_load_microcode - load the gfx CP ME ucode
2379 * Loads the gfx PFP, ME, and CE ucode.
2390 if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw)
2393 pfp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
2394 ce_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
2395 me_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
2400 adev->gfx.pfp_fw_version = le32_to_cpu(pfp_hdr->header.ucode_version);
2401 adev->gfx.ce_fw_version = le32_to_cpu(ce_hdr->header.ucode_version);
2402 adev->gfx.me_fw_version = le32_to_cpu(me_hdr->header.ucode_version);
2403 adev->gfx.me_feature_version = le32_to_cpu(me_hdr->ucode_feature_version);
2404 adev->gfx.ce_feature_version = le32_to_cpu(ce_hdr->ucode_feature_version);
2405 adev->gfx.pfp_feature_version = le32_to_cpu(pfp_hdr->ucode_feature_version);
2411 (adev->gfx.pfp_fw->data +
2417 WREG32(mmCP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version);
2421 (adev->gfx.ce_fw->data +
2427 WREG32(mmCP_CE_UCODE_ADDR, adev->gfx.ce_fw_version);
2431 (adev->gfx.me_fw->data +
2437 WREG32(mmCP_ME_RAM_WADDR, adev->gfx.me_fw_version);
2443 * gfx_v7_0_cp_gfx_start - start the gfx ring
2453 struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0];
2459 WREG32(mmCP_MAX_CONTEXT, adev->gfx.config.max_hw_contexts - 1);
2471 /* init the CE partitions. CE only used for gfx on CIK */
2485 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
2499 amdgpu_ring_write(ring, adev->gfx.config.rb_config[0][0].raster_config);
2500 amdgpu_ring_write(ring, adev->gfx.config.rb_config[0][0].raster_config_1);
2519 * gfx_v7_0_cp_gfx_resume - setup the gfx ring buffer registers
2523 * Program the location and size of the gfx ring buffer
2547 /* ring 0 - compute and gfx */
2549 ring = &adev->gfx.gfx_ring[0];
2653 if (!adev->gfx.mec_fw)
2656 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
2658 adev->gfx.mec_fw_version = le32_to_cpu(mec_hdr->header.ucode_version);
2659 adev->gfx.mec_feature_version = le32_to_cpu(
2666 (adev->gfx.mec_fw->data +
2677 if (!adev->gfx.mec2_fw)
2680 mec2_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec2_fw->data;
2682 adev->gfx.mec2_fw_version = le32_to_cpu(mec2_hdr->header.ucode_version);
2683 adev->gfx.mec2_feature_version = le32_to_cpu(
2688 (adev->gfx.mec2_fw->data +
2712 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
2713 struct amdgpu_ring *ring = &adev->gfx.compute_ring[i];
2721 amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL);
2730 bitmap_zero(adev->gfx.mec_bitmap[0].queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
2736 mec_hpd_size = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe_per_mec
2742 &adev->gfx.mec.hpd_eop_obj,
2743 &adev->gfx.mec.hpd_eop_gpu_addr,
2754 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj);
2755 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);
2803 size_t eop_offset = (mec * adev->gfx.mec.num_pipe_per_mec + pipe)
2807 eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr + eop_offset;
3002 struct amdgpu_ring *ring = &adev->gfx.compute_ring[ring_id];
3048 for (i = 0; i < adev->gfx.mec.num_mec; i++)
3049 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++)
3053 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
3063 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
3064 ring = &adev->gfx.compute_ring[i];
3236 adev->gfx.rlc.reg_list = spectre_rlc_save_restore_register_list;
3237 adev->gfx.rlc.reg_list_size =
3240 adev->gfx.rlc.reg_list = kalindi_rlc_save_restore_register_list;
3241 adev->gfx.rlc.reg_list_size =
3245 adev->gfx.rlc.cs_data = ci_cs_data;
3246 adev->gfx.rlc.cp_table_size = ALIGN(CP_ME_TABLE_SIZE * 5 * 4, 2048); /* CP JT */
3247 adev->gfx.rlc.cp_table_size += 64 * 1024; /* GDS */
3249 src_ptr = adev->gfx.rlc.reg_list;
3250 dws = adev->gfx.rlc.reg_list_size;
3253 cs_data = adev->gfx.rlc.cs_data;
3269 if (adev->gfx.rlc.cp_table_size) {
3276 if (adev->gfx.rlc.funcs->update_spm_vmid)
3277 adev->gfx.rlc.funcs->update_spm_vmid(adev, 0xf);
3300 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
3301 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
3452 if (!adev->gfx.rlc_fw)
3455 hdr = (const struct rlc_firmware_header_v1_0 *)adev->gfx.rlc_fw->data;
3457 adev->gfx.rlc_fw_version = le32_to_cpu(hdr->header.ucode_version);
3458 adev->gfx.rlc_feature_version = le32_to_cpu(
3461 adev->gfx.rlc.funcs->stop(adev);
3467 adev->gfx.rlc.funcs->reset(adev);
3485 (adev->gfx.rlc_fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
3490 WREG32(mmRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version);
3498 adev->gfx.rlc.funcs->start(adev);
3778 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh);
3787 WREG32(mmRLC_PG_ALWAYS_ON_CU_MASK, adev->gfx.cu_info.ao_cu_mask);
3791 tmp |= (adev->gfx.cu_info.number << RLC_MAX_PG_CU__MAX_POWERED_UP_CU__SHIFT);
3831 if (adev->gfx.rlc.cs_data) {
3833 WREG32(mmRLC_GPM_SCRATCH_DATA, upper_32_bits(adev->gfx.rlc.clear_state_gpu_addr));
3834 WREG32(mmRLC_GPM_SCRATCH_DATA, lower_32_bits(adev->gfx.rlc.clear_state_gpu_addr));
3835 WREG32(mmRLC_GPM_SCRATCH_DATA, adev->gfx.rlc.clear_state_size);
3841 if (adev->gfx.rlc.reg_list) {
3843 for (i = 0; i < adev->gfx.rlc.reg_list_size; i++)
3844 WREG32(mmRLC_GPM_SCRATCH_DATA, adev->gfx.rlc.reg_list[i]);
3852 WREG32(mmRLC_SAVE_AND_RESTORE_BASE, adev->gfx.rlc.save_restore_gpu_addr >> 8);
3853 WREG32(mmRLC_JUMP_TABLE_RESTORE, adev->gfx.rlc.cp_table_gpu_addr >> 8);
3888 if (adev->gfx.rlc.cs_data == NULL)
3896 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
3921 if (adev->gfx.rlc.cs_data == NULL)
3933 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
4028 mutex_lock(&adev->gfx.gpu_clock_mutex);
4032 mutex_unlock(&adev->gfx.gpu_clock_mutex);
4179 adev->gfx.xcc_mask = 1;
4180 adev->gfx.num_gfx_rings = GFX7_NUM_GFX_RINGS;
4181 adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev),
4183 adev->gfx.funcs = &gfx_v7_0_gfx_funcs;
4184 adev->gfx.rlc.funcs = &gfx_v7_0_rlc_funcs;
4197 r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0);
4201 r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0);
4217 adev->gfx.config.max_shader_engines = 2;
4218 adev->gfx.config.max_tile_pipes = 4;
4219 adev->gfx.config.max_cu_per_sh = 7;
4220 adev->gfx.config.max_sh_per_se = 1;
4221 adev->gfx.config.max_backends_per_se = 2;
4222 adev->gfx.config.max_texture_channel_caches = 4;
4223 adev->gfx.config.max_gprs = 256;
4224 adev->gfx.config.max_gs_threads = 32;
4225 adev->gfx.config.max_hw_contexts = 8;
4227 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
4228 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
4229 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
4230 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
4234 adev->gfx.config.max_shader_engines = 4;
4235 adev->gfx.config.max_tile_pipes = 16;
4236 adev->gfx.config.max_cu_per_sh = 11;
4237 adev->gfx.config.max_sh_per_se = 1;
4238 adev->gfx.config.max_backends_per_se = 4;
4239 adev->gfx.config.max_texture_channel_caches = 16;
4240 adev->gfx.config.max_gprs = 256;
4241 adev->gfx.config.max_gs_threads = 32;
4242 adev->gfx.config.max_hw_contexts = 8;
4244 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
4245 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
4246 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
4247 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
4251 adev->gfx.config.max_shader_engines = 1;
4252 adev->gfx.config.max_tile_pipes = 4;
4253 adev->gfx.config.max_cu_per_sh = 8;
4254 adev->gfx.config.max_backends_per_se = 2;
4255 adev->gfx.config.max_sh_per_se = 1;
4256 adev->gfx.config.max_texture_channel_caches = 4;
4257 adev->gfx.config.max_gprs = 256;
4258 adev->gfx.config.max_gs_threads = 16;
4259 adev->gfx.config.max_hw_contexts = 8;
4261 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
4262 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
4263 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
4264 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
4270 adev->gfx.config.max_shader_engines = 1;
4271 adev->gfx.config.max_tile_pipes = 2;
4272 adev->gfx.config.max_cu_per_sh = 2;
4273 adev->gfx.config.max_sh_per_se = 1;
4274 adev->gfx.config.max_backends_per_se = 1;
4275 adev->gfx.config.max_texture_channel_caches = 2;
4276 adev->gfx.config.max_gprs = 256;
4277 adev->gfx.config.max_gs_threads = 16;
4278 adev->gfx.config.max_hw_contexts = 8;
4280 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
4281 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
4282 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
4283 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
4288 adev->gfx.config.mc_arb_ramcfg = RREG32(mmMC_ARB_RAMCFG);
4289 mc_arb_ramcfg = adev->gfx.config.mc_arb_ramcfg;
4291 adev->gfx.config.num_banks = REG_GET_FIELD(mc_arb_ramcfg,
4293 adev->gfx.config.num_ranks = REG_GET_FIELD(mc_arb_ramcfg,
4296 adev->gfx.config.num_tile_pipes = adev->gfx.config.max_tile_pipes;
4297 adev->gfx.config.mem_max_burst_length_bytes = 256;
4321 adev->gfx.config.mem_row_size_in_kb = 2;
4323 adev->gfx.config.mem_row_size_in_kb = 1;
4326 adev->gfx.config.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024;
4327 if (adev->gfx.config.mem_row_size_in_kb > 4)
4328 adev->gfx.config.mem_row_size_in_kb = 4;
4331 adev->gfx.config.shader_engine_tile_size = 32;
4332 adev->gfx.config.num_gpus = 1;
4333 adev->gfx.config.multi_gpu_tile_size = 64;
4337 switch (adev->gfx.config.mem_row_size_in_kb) {
4349 adev->gfx.config.gb_addr_config = gb_addr_config;
4357 struct amdgpu_ring *ring = &adev->gfx.compute_ring[ring_id];
4370 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec)
4375 &adev->gfx.eop_irq, irq_type,
4392 adev->gfx.mec.num_mec = 2;
4399 adev->gfx.mec.num_mec = 1;
4402 adev->gfx.mec.num_pipe_per_mec = 4;
4403 adev->gfx.mec.num_queue_per_pipe = 8;
4406 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 181, &adev->gfx.eop_irq);
4412 &adev->gfx.priv_reg_irq);
4418 &adev->gfx.priv_inst_irq);
4424 DRM_ERROR("Failed to load gfx firmware!\n");
4428 r = adev->gfx.rlc.funcs->init(adev);
4441 for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
4442 ring = &adev->gfx.gfx_ring[i];
4444 snprintf(ring->name, sizeof(ring->name), "gfx");
4446 &adev->gfx.eop_irq,
4455 for (i = 0; i < adev->gfx.mec.num_mec; ++i) {
4456 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) {
4457 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) {
4473 adev->gfx.ce_ram_size = 0x8000;
4485 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
4486 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]);
4487 for (i = 0; i < adev->gfx.num_compute_rings; i++)
4488 amdgpu_ring_fini(&adev->gfx.compute_ring[i]);
4493 amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj,
4494 &adev->gfx.rlc.clear_state_gpu_addr,
4495 (void **)&adev->gfx.rlc.cs_ptr);
4496 if (adev->gfx.rlc.cp_table_size) {
4497 amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj,
4498 &adev->gfx.rlc.cp_table_gpu_addr,
4499 (void **)&adev->gfx.rlc.cp_table_ptr);
4514 adev->gfx.rlc.funcs->get_csb_buffer(adev, adev->gfx.rlc.cs_ptr);
4516 r = adev->gfx.rlc.funcs->resume(adev);
4531 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0);
4532 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0);
4534 adev->gfx.rlc.funcs->stop(adev);
4619 adev->gfx.rlc.funcs->stop(adev);
4834 amdgpu_fence_process(&adev->gfx.gfx_ring[0]);
4838 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
4839 ring = &adev->gfx.compute_ring[i];
4859 drm_sched_fault(&adev->gfx.gfx_ring[0].sched);
4863 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
4864 ring = &adev->gfx.compute_ring[i];
4886 // XXX soft reset the gfx block only
5051 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
5052 adev->gfx.gfx_ring[i].funcs = &gfx_v7_0_ring_funcs_gfx;
5053 for (i = 0; i < adev->gfx.num_compute_rings; i++)
5054 adev->gfx.compute_ring[i].funcs = &gfx_v7_0_ring_funcs_compute;
5074 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST;
5075 adev->gfx.eop_irq.funcs = &gfx_v7_0_eop_irq_funcs;
5077 adev->gfx.priv_reg_irq.num_types = 1;
5078 adev->gfx.priv_reg_irq.funcs = &gfx_v7_0_priv_reg_irq_funcs;
5080 adev->gfx.priv_inst_irq.num_types = 1;
5081 adev->gfx.priv_inst_irq.funcs = &gfx_v7_0_priv_inst_irq_funcs;
5098 struct amdgpu_cu_info *cu_info = &adev->gfx.cu_info;
5105 ao_cu_num = adev->gfx.config.max_cu_per_sh;
5112 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
5113 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
5124 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) {