Lines Matching refs:gfx
46 #include "ivsrcid/gfx/irqsrcs_gfx_9_0.h"
893 adev->gfx.kiq[0].pmf = &gfx_v9_0_kiq_pm4_funcs;
1083 amdgpu_ucode_release(&adev->gfx.pfp_fw);
1084 amdgpu_ucode_release(&adev->gfx.me_fw);
1085 amdgpu_ucode_release(&adev->gfx.ce_fw);
1086 amdgpu_ucode_release(&adev->gfx.rlc_fw);
1087 amdgpu_ucode_release(&adev->gfx.mec_fw);
1088 amdgpu_ucode_release(&adev->gfx.mec2_fw);
1090 kfree(adev->gfx.rlc.register_list_format);
1095 adev->gfx.me_fw_write_wait = false;
1096 adev->gfx.mec_fw_write_wait = false;
1099 ((adev->gfx.mec_fw_version < 0x000001a5) ||
1100 (adev->gfx.mec_feature_version < 46) ||
1101 (adev->gfx.pfp_fw_version < 0x000000b7) ||
1102 (adev->gfx.pfp_feature_version < 46)))
1107 if ((adev->gfx.me_fw_version >= 0x0000009c) &&
1108 (adev->gfx.me_feature_version >= 42) &&
1109 (adev->gfx.pfp_fw_version >= 0x000000b1) &&
1110 (adev->gfx.pfp_feature_version >= 42))
1111 adev->gfx.me_fw_write_wait = true;
1113 if ((adev->gfx.mec_fw_version >= 0x00000193) &&
1114 (adev->gfx.mec_feature_version >= 42))
1115 adev->gfx.mec_fw_write_wait = true;
1118 if ((adev->gfx.me_fw_version >= 0x0000009c) &&
1119 (adev->gfx.me_feature_version >= 44) &&
1120 (adev->gfx.pfp_fw_version >= 0x000000b2) &&
1121 (adev->gfx.pfp_feature_version >= 44))
1122 adev->gfx.me_fw_write_wait = true;
1124 if ((adev->gfx.mec_fw_version >= 0x00000196) &&
1125 (adev->gfx.mec_feature_version >= 44))
1126 adev->gfx.mec_fw_write_wait = true;
1129 if ((adev->gfx.me_fw_version >= 0x0000009c) &&
1130 (adev->gfx.me_feature_version >= 44) &&
1131 (adev->gfx.pfp_fw_version >= 0x000000b2) &&
1132 (adev->gfx.pfp_feature_version >= 44))
1133 adev->gfx.me_fw_write_wait = true;
1135 if ((adev->gfx.mec_fw_version >= 0x00000197) &&
1136 (adev->gfx.mec_feature_version >= 44))
1137 adev->gfx.mec_fw_write_wait = true;
1141 if ((adev->gfx.me_fw_version >= 0x0000009c) &&
1142 (adev->gfx.me_feature_version >= 42) &&
1143 (adev->gfx.pfp_fw_version >= 0x000000b1) &&
1144 (adev->gfx.pfp_feature_version >= 42))
1145 adev->gfx.me_fw_write_wait = true;
1147 if ((adev->gfx.mec_fw_version >= 0x00000192) &&
1148 (adev->gfx.mec_feature_version >= 42))
1149 adev->gfx.mec_fw_write_wait = true;
1152 adev->gfx.me_fw_write_wait = true;
1153 adev->gfx.mec_fw_write_wait = true;
1206 (adev->gfx.me_fw_version >= 0x000000a5) &&
1207 (adev->gfx.me_feature_version >= 52))
1228 adev->gfx.rlc_fw_version < 531) ||
1229 (adev->gfx.rlc_feature_version < 1) ||
1230 !adev->gfx.rlc.is_rlc_v2_1))
1256 err = amdgpu_ucode_request(adev, &adev->gfx.pfp_fw, fw_name);
1262 err = amdgpu_ucode_request(adev, &adev->gfx.me_fw, fw_name);
1268 err = amdgpu_ucode_request(adev, &adev->gfx.ce_fw, fw_name);
1275 amdgpu_ucode_release(&adev->gfx.pfp_fw);
1276 amdgpu_ucode_release(&adev->gfx.me_fw);
1277 amdgpu_ucode_release(&adev->gfx.ce_fw);
1312 err = amdgpu_ucode_request(adev, &adev->gfx.rlc_fw, fw_name);
1315 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
1322 amdgpu_ucode_release(&adev->gfx.rlc_fw);
1348 err = amdgpu_ucode_request(adev, &adev->gfx.mec_fw, fw_name);
1361 err = amdgpu_ucode_request(adev, &adev->gfx.mec2_fw, fw_name);
1367 amdgpu_ucode_release(&adev->gfx.mec2_fw);
1370 adev->gfx.mec2_fw_version = adev->gfx.mec_fw_version;
1371 adev->gfx.mec2_feature_version = adev->gfx.mec_feature_version;
1379 amdgpu_ucode_release(&adev->gfx.mec_fw);
1392 if (adev->gfx.num_gfx_rings) {
1444 if (adev->gfx.rlc.cs_data == NULL)
1456 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
1480 struct amdgpu_cu_info *cu_info = &adev->gfx.cu_info;
1494 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
1495 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
1501 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k ++) {
1637 reg_access_ctrl = &adev->gfx.rlc.reg_access_ctrl[0];
1645 adev->gfx.rlc.rlcg_reg_access_supported = true;
1653 adev->gfx.rlc.cs_data = gfx9_cs_data;
1655 cs_data = adev->gfx.rlc.cs_data;
1666 adev->gfx.rlc.cp_table_size = ALIGN(96 * 5 * 4, 2048) + (64 * 1024); /* JT + GDS */
1677 amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL);
1678 amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_obj, NULL, NULL);
1692 bitmap_zero(adev->gfx.mec_bitmap[0].queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
1696 mec_hpd_size = adev->gfx.num_compute_rings * GFX9_MEC_HPD_SIZE;
1701 &adev->gfx.mec.hpd_eop_obj,
1702 &adev->gfx.mec.hpd_eop_gpu_addr,
1712 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj);
1713 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);
1716 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
1719 (adev->gfx.mec_fw->data +
1725 &adev->gfx.mec.mec_fw_obj,
1726 &adev->gfx.mec.mec_fw_gpu_addr,
1736 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj);
1737 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj);
1841 adev->gfx.config.max_hw_contexts = 8;
1842 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1843 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1844 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1845 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
1849 adev->gfx.config.max_hw_contexts = 8;
1850 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1851 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1852 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1853 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
1855 DRM_INFO("fix gfx.config for vega12\n");
1858 adev->gfx.ras = &gfx_v9_0_ras;
1859 adev->gfx.config.max_hw_contexts = 8;
1860 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1861 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1862 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1863 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
1874 adev->gfx.config.max_hw_contexts = 8;
1875 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1876 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1877 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1878 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
1885 adev->gfx.ras = &gfx_v9_4_ras;
1886 adev->gfx.config.max_hw_contexts = 8;
1887 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1888 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1889 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1890 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
1896 adev->gfx.config.max_hw_contexts = 8;
1897 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1898 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1899 adev->gfx.config.sc_hiz_tile_fifo_size = 0x80;
1900 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
1906 adev->gfx.ras = &gfx_v9_4_2_ras;
1907 adev->gfx.config.max_hw_contexts = 8;
1908 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1909 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1910 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1911 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
1925 adev->gfx.config.gb_addr_config = gb_addr_config;
1927 adev->gfx.config.gb_addr_config_fields.num_pipes = 1 <<
1929 adev->gfx.config.gb_addr_config,
1933 adev->gfx.config.max_tile_pipes =
1934 adev->gfx.config.gb_addr_config_fields.num_pipes;
1936 adev->gfx.config.gb_addr_config_fields.num_banks = 1 <<
1938 adev->gfx.config.gb_addr_config,
1941 adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 <<
1943 adev->gfx.config.gb_addr_config,
1946 adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 <<
1948 adev->gfx.config.gb_addr_config,
1951 adev->gfx.config.gb_addr_config_fields.num_se = 1 <<
1953 adev->gfx.config.gb_addr_config,
1956 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 +
1958 adev->gfx.config.gb_addr_config,
1969 struct amdgpu_ring *ring = &adev->gfx.compute_ring[ring_id];
1972 ring = &adev->gfx.compute_ring[ring_id];
1982 ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr
1988 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec)
1993 return amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type,
2014 adev->gfx.mec.num_mec = 2;
2017 adev->gfx.mec.num_mec = 1;
2021 adev->gfx.mec.num_pipe_per_mec = 4;
2022 adev->gfx.mec.num_queue_per_pipe = 8;
2025 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_9_0__SRCID__CP_EOP_INTERRUPT, &adev->gfx.eop_irq);
2031 &adev->gfx.priv_reg_irq);
2037 &adev->gfx.priv_inst_irq);
2043 &adev->gfx.cp_ecc_error_irq);
2049 &adev->gfx.cp_ecc_error_irq);
2053 adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE;
2055 if (adev->gfx.rlc.funcs) {
2056 if (adev->gfx.rlc.funcs->init) {
2057 r = adev->gfx.rlc.funcs->init(adev);
2071 /* set up the gfx ring */
2072 for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
2073 ring = &adev->gfx.gfx_ring[i];
2076 snprintf(ring->name, sizeof(ring->name), "gfx");
2085 r = amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq,
2093 if (adev->gfx.num_gfx_rings) {
2095 ring = &adev->gfx.sw_gfx_ring[i];
2103 r = amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq,
2112 r = amdgpu_ring_mux_init(&adev->gfx.muxer, &adev->gfx.gfx_ring[0],
2119 r = amdgpu_ring_mux_add_sw_ring(&adev->gfx.muxer,
2120 &adev->gfx.sw_gfx_ring[i]);
2130 for (i = 0; i < adev->gfx.mec.num_mec; ++i) {
2131 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) {
2132 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) {
2154 kiq = &adev->gfx.kiq[0];
2164 adev->gfx.ce_ram_size = 0x8000;
2171 dev_err(adev->dev, "Failed to initialize gfx ras block!\n");
2184 if (adev->gfx.num_gfx_rings) {
2186 amdgpu_ring_fini(&adev->gfx.sw_gfx_ring[i]);
2187 amdgpu_ring_mux_fini(&adev->gfx.muxer);
2190 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
2191 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]);
2192 for (i = 0; i < adev->gfx.num_compute_rings; i++)
2193 amdgpu_ring_fini(&adev->gfx.compute_ring[i]);
2196 amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq[0].ring);
2200 amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj,
2201 &adev->gfx.rlc.clear_state_gpu_addr,
2202 (void **)&adev->gfx.rlc.cs_ptr);
2204 amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj,
2205 &adev->gfx.rlc.cp_table_gpu_addr,
2206 (void **)&adev->gfx.rlc.cp_table_ptr);
2252 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se /
2253 adev->gfx.config.max_sh_per_se);
2263 u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se /
2264 adev->gfx.config.max_sh_per_se;
2267 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
2268 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
2271 active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) *
2278 adev->gfx.config.backend_enable_mask = active_rbs;
2279 adev->gfx.config.num_rbs = hweight32(active_rbs);
2349 * Initialize all compute and user-gfx VMIDs to have no GDS, GWS, or OA
2387 if (adev->gfx.num_gfx_rings)
2389 gfx_v9_0_get_cu_info(adev, &adev->gfx.cu_info);
2390 adev->gfx.config.db_debug2 = RREG32_SOC15(GC, 0, mmDB_DEBUG2);
2433 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
2434 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
2477 if(adev->gfx.num_gfx_rings)
2485 adev->gfx.rlc.funcs->get_csb_buffer(adev, adev->gfx.rlc.cs_ptr);
2488 adev->gfx.rlc.clear_state_gpu_addr >> 32);
2490 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc);
2492 adev->gfx.rlc.clear_state_size);
2545 kmemdup(adev->gfx.rlc.register_list_format,
2546 adev->gfx.rlc.reg_list_format_size_bytes, GFP_KERNEL);
2553 adev->gfx.rlc.reg_list_format_direct_reg_list_length,
2554 adev->gfx.rlc.reg_list_format_size_bytes >> 2,
2569 for (i = 0; i < adev->gfx.rlc.reg_list_size_bytes >> 2; i++)
2571 adev->gfx.rlc.register_restore[i]);
2575 adev->gfx.rlc.reg_list_format_start);
2578 for (i = 0; i < adev->gfx.rlc.reg_list_format_direct_reg_list_length; i++)
2583 while (i < (adev->gfx.rlc.reg_list_format_size_bytes >> 2)) {
2605 list_size = adev->gfx.rlc.reg_list_size_bytes >> 2;
2608 adev->gfx.rlc.reg_restore_list_size);
2613 adev->gfx.rlc.starting_offsets_start);
2814 if (adev->gfx.rlc.is_rlc_v2_1) {
2828 adev->gfx.rlc.cp_table_gpu_addr >> 8);
2868 rlc_ucode_ver, adev->gfx.rlc_fw_version);
2886 if (!adev->gfx.rlc_fw)
2889 hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
2892 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
2900 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version);
2914 adev->gfx.rlc.funcs->stop(adev);
2950 adev->gfx.rlc.funcs->start(adev);
2974 if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw)
2978 adev->gfx.pfp_fw->data;
2980 adev->gfx.ce_fw->data;
2982 adev->gfx.me_fw->data;
2992 (adev->gfx.pfp_fw->data +
2998 WREG32_SOC15(GC, 0, mmCP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version);
3002 (adev->gfx.ce_fw->data +
3008 WREG32_SOC15(GC, 0, mmCP_CE_UCODE_ADDR, adev->gfx.ce_fw_version);
3012 (adev->gfx.me_fw->data +
3018 WREG32_SOC15(GC, 0, mmCP_ME_RAM_WADDR, adev->gfx.me_fw_version);
3025 struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0];
3031 WREG32_SOC15(GC, 0, mmCP_MAX_CONTEXT, adev->gfx.config.max_hw_contexts - 1);
3107 ring = &adev->gfx.gfx_ring[0];
3169 adev->gfx.kiq[0].ring.sched.ready = false;
3181 if (!adev->gfx.mec_fw)
3186 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
3190 (adev->gfx.mec_fw->data +
3198 adev->gfx.mec.mec_fw_gpu_addr & 0xFFFFF000);
3200 upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr));
3210 adev->gfx.mec_fw_version);
3542 tmp_mqd = (struct v9_mqd *)adev->gfx.kiq[0].mqd_backup;
3545 if (adev->gfx.kiq[0].mqd_backup)
3546 memcpy(mqd, adev->gfx.kiq[0].mqd_backup, sizeof(struct v9_mqd_allocation));
3570 if (adev->gfx.kiq[0].mqd_backup)
3571 memcpy(adev->gfx.kiq[0].mqd_backup, mqd, sizeof(struct v9_mqd_allocation));
3581 int mqd_idx = ring - &adev->gfx.compute_ring[0];
3587 tmp_mqd = (struct v9_mqd *)adev->gfx.mec.mqd_backup[mqd_idx];
3600 if (adev->gfx.mec.mqd_backup[mqd_idx])
3601 memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(struct v9_mqd_allocation));
3604 if (adev->gfx.mec.mqd_backup[mqd_idx])
3605 memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(struct v9_mqd_allocation));
3620 ring = &adev->gfx.kiq[0].ring;
3646 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
3647 ring = &adev->gfx.compute_ring[i];
3677 if (adev->gfx.num_gfx_rings) {
3693 if (adev->gfx.num_gfx_rings) {
3703 if (adev->gfx.num_gfx_rings) {
3704 ring = &adev->gfx.gfx_ring[0];
3710 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
3711 ring = &adev->gfx.compute_ring[i];
3740 if (adev->gfx.num_gfx_rings)
3757 r = adev->gfx.rlc.funcs->resume(adev);
3776 amdgpu_irq_put(adev, &adev->gfx.cp_ecc_error_irq, 0);
3777 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0);
3778 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0);
3801 soc15_grbm_select(adev, adev->gfx.kiq[0].ring.me,
3802 adev->gfx.kiq[0].ring.pipe,
3803 adev->gfx.kiq[0].ring.queue, 0, 0);
3804 gfx_v9_0_kiq_fini_register(&adev->gfx.kiq[0].ring);
3818 adev->gfx.rlc.funcs->stop(adev);
3890 adev->gfx.rlc.funcs->stop(adev);
3892 if (adev->gfx.num_gfx_rings)
3925 struct amdgpu_kiq *kiq = &adev->gfx.kiq[0];
4015 mutex_lock(&adev->gfx.gpu_clock_mutex);
4023 mutex_unlock(&adev->gfx.gpu_clock_mutex);
4297 struct amdgpu_ring *ring = &adev->gfx.compute_ring[0];
4344 struct amdgpu_ring *ring = &adev->gfx.compute_ring[0];
4351 int compute_dim_x = adev->gfx.config.max_shader_engines *
4352 adev->gfx.config.max_cu_per_sh *
4353 adev->gfx.config.max_sh_per_se;
4355 int gpr_reg_size = adev->gfx.config.max_shader_engines + 6;
4518 adev->gfx.funcs = &gfx_v9_0_gfx_funcs;
4522 adev->gfx.num_gfx_rings = 0;
4524 adev->gfx.num_gfx_rings = GFX9_NUM_GFX_RINGS;
4525 adev->gfx.xcc_mask = 1;
4526 adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev),
4567 if (adev->gfx.ras &&
4568 adev->gfx.ras->enable_watchdog_timer)
4569 adev->gfx.ras->enable_watchdog_timer(adev);
4579 r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0);
4583 r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0);
4755 if (!adev->gfx.num_gfx_rings)
4982 /* update gfx cgpg state */
5196 gfx[0].gfx_meta_data) +
5228 gfx[0].gfx_meta_data) +
5427 gfx[0].gfx_meta_data) +
5461 struct amdgpu_kiq *kiq = &adev->gfx.kiq[0];
5525 gfx[0].gfx_meta_data) +
5533 gfx[0].gds_backup) +
5689 adev->gfx.me_fw_write_wait : adev->gfx.mec_fw_write_wait;
5910 if (adev->gfx.num_gfx_rings &&
5911 !amdgpu_mcbp_handle_trailing_fence_irq(&adev->gfx.muxer)) {
5914 amdgpu_fence_process(&adev->gfx.sw_gfx_ring[i]);
5919 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
5920 ring = &adev->gfx.compute_ring[i];
5945 drm_sched_fault(&adev->gfx.gfx_ring[0].sched);
5949 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
5950 ring = &adev->gfx.compute_ring[i];
6828 * number of gfx waves. Setting 5 bit will make sure gfx only gets
6841 for (i = 0; i < adev->gfx.mec.num_pipe_per_mec; i++) {
7044 adev->gfx.kiq[0].ring.funcs = &gfx_v9_0_ring_funcs_kiq;
7046 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
7047 adev->gfx.gfx_ring[i].funcs = &gfx_v9_0_ring_funcs_gfx;
7049 if (adev->gfx.num_gfx_rings) {
7051 adev->gfx.sw_gfx_ring[i].funcs = &gfx_v9_0_sw_ring_funcs_gfx;
7054 for (i = 0; i < adev->gfx.num_compute_rings; i++)
7055 adev->gfx.compute_ring[i].funcs = &gfx_v9_0_ring_funcs_compute;
7081 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST;
7082 adev->gfx.eop_irq.funcs = &gfx_v9_0_eop_irq_funcs;
7084 adev->gfx.priv_reg_irq.num_types = 1;
7085 adev->gfx.priv_reg_irq.funcs = &gfx_v9_0_priv_reg_irq_funcs;
7087 adev->gfx.priv_inst_irq.num_types = 1;
7088 adev->gfx.priv_inst_irq.funcs = &gfx_v9_0_priv_inst_irq_funcs;
7090 adev->gfx.cp_ecc_error_irq.num_types = 2; /*C5 ECC error and C9 FUE error*/
7091 adev->gfx.cp_ecc_error_irq.funcs = &gfx_v9_0_cp_ecc_error_irq_funcs;
7105 adev->gfx.rlc.funcs = &gfx_v9_0_rlc_funcs;
7193 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh);
7211 if (adev->gfx.config.max_shader_engines *
7212 adev->gfx.config.max_sh_per_se > 16)
7216 adev->gfx.config.max_shader_engines,
7217 adev->gfx.config.max_sh_per_se);
7220 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
7221 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
7227 adev, disable_masks[i * adev->gfx.config.max_sh_per_se + j]);
7244 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k ++) {
7246 if (counter < adev->gfx.config.max_cu_per_sh)