Lines Matching refs:gfx
157 .num_pipe_per_mec = adev->gfx.mec.num_pipe_per_mec,
158 .num_queue_per_pipe = adev->gfx.mec.num_queue_per_pipe,
171 adev->gfx.mec_bitmap[0].queue_bitmap,
178 * adev->gfx.mec.num_pipe_per_mec
179 * adev->gfx.mec.num_queue_per_pipe;
395 return adev->gfx.pfp_fw_version;
398 return adev->gfx.me_fw_version;
401 return adev->gfx.ce_fw_version;
404 return adev->gfx.mec_fw_version;
407 return adev->gfx.mec2_fw_version;
410 return adev->gfx.rlc_fw_version;
461 if (adev->gfx.funcs->get_gpu_clock_counter)
462 return adev->gfx.funcs->get_gpu_clock_counter(adev);
477 struct amdgpu_cu_info acu_info = adev->gfx.cu_info;
487 cu_info->num_shader_engines = adev->gfx.config.max_shader_engines;
488 cu_info->num_shader_arrays_per_engine = adev->gfx.config.max_sh_per_se;
489 cu_info->num_cu_per_sh = adev->gfx.config.max_cu_per_sh;
665 ring = &adev->gfx.compute_ring[0];
794 if (adev->gfx.ras && adev->gfx.ras->query_utcl2_poison_status)
795 return adev->gfx.ras->query_utcl2_poison_status(adev);
828 struct amdgpu_kiq *kiq = &adev->gfx.kiq[inst];