Lines Matching refs:gfx
40 #include "ivsrcid/gfx/irqsrcs_gfx_10_1.h"
3557 if (adev->enable_mes && !adev->gfx.kiq[0].ring.sched.ready) {
3625 adev->gfx.kiq[0].pmf = &gfx_v10_0_kiq_pm4_funcs;
3880 amdgpu_ucode_release(&adev->gfx.pfp_fw);
3881 amdgpu_ucode_release(&adev->gfx.me_fw);
3882 amdgpu_ucode_release(&adev->gfx.ce_fw);
3883 amdgpu_ucode_release(&adev->gfx.rlc_fw);
3884 amdgpu_ucode_release(&adev->gfx.mec_fw);
3885 amdgpu_ucode_release(&adev->gfx.mec2_fw);
3887 kfree(adev->gfx.rlc.register_list_format);
3892 adev->gfx.cp_fw_write_wait = false;
3900 if ((adev->gfx.me_fw_version >= 0x00000046) &&
3901 (adev->gfx.me_feature_version >= 27) &&
3902 (adev->gfx.pfp_fw_version >= 0x00000068) &&
3903 (adev->gfx.pfp_feature_version >= 27) &&
3904 (adev->gfx.mec_fw_version >= 0x0000005b) &&
3905 (adev->gfx.mec_feature_version >= 27))
3906 adev->gfx.cp_fw_write_wait = true;
3916 adev->gfx.cp_fw_write_wait = true;
3922 if (!adev->gfx.cp_fw_write_wait)
3973 err = amdgpu_ucode_request(adev, &adev->gfx.pfp_fw, fw_name);
3979 err = amdgpu_ucode_request(adev, &adev->gfx.me_fw, fw_name);
3985 err = amdgpu_ucode_request(adev, &adev->gfx.ce_fw, fw_name);
3992 err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev);
3999 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
4008 err = amdgpu_ucode_request(adev, &adev->gfx.mec_fw, fw_name);
4015 err = amdgpu_ucode_request(adev, &adev->gfx.mec2_fw, fw_name);
4021 adev->gfx.mec2_fw = NULL;
4027 amdgpu_ucode_release(&adev->gfx.pfp_fw);
4028 amdgpu_ucode_release(&adev->gfx.me_fw);
4029 amdgpu_ucode_release(&adev->gfx.ce_fw);
4030 amdgpu_ucode_release(&adev->gfx.rlc_fw);
4031 amdgpu_ucode_release(&adev->gfx.mec_fw);
4032 amdgpu_ucode_release(&adev->gfx.mec2_fw);
4078 if (adev->gfx.rlc.cs_data == NULL)
4090 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
4109 buffer[count++] = cpu_to_le32(adev->gfx.config.pa_sc_tile_steering_override);
4121 amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj,
4122 &adev->gfx.rlc.clear_state_gpu_addr,
4123 (void **)&adev->gfx.rlc.cs_ptr);
4126 amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj,
4127 &adev->gfx.rlc.cp_table_gpu_addr,
4128 (void **)&adev->gfx.rlc.cp_table_ptr);
4135 reg_access_ctrl = &adev->gfx.rlc.reg_access_ctrl[0];
4152 adev->gfx.rlc.rlcg_reg_access_supported = true;
4160 adev->gfx.rlc.cs_data = gfx10_cs_data;
4162 cs_data = adev->gfx.rlc.cs_data;
4176 amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL);
4177 amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_obj, NULL, NULL);
4182 bitmap_zero(adev->gfx.me.queue_bitmap, AMDGPU_MAX_GFX_QUEUES);
4198 bitmap_zero(adev->gfx.mec_bitmap[0].queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
4202 mec_hpd_size = adev->gfx.num_compute_rings * GFX10_MEC_HPD_SIZE;
4207 &adev->gfx.mec.hpd_eop_obj,
4208 &adev->gfx.mec.hpd_eop_gpu_addr,
4218 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj);
4219 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);
4223 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
4225 fw_data = (const __le32 *) (adev->gfx.mec_fw->data +
4231 &adev->gfx.mec.mec_fw_obj,
4232 &adev->gfx.mec.mec_fw_gpu_addr,
4242 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj);
4243 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj);
4360 adev->gfx.config.max_hw_contexts = 8;
4361 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
4362 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
4363 adev->gfx.config.sc_hiz_tile_fifo_size = 0;
4364 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
4375 adev->gfx.config.max_hw_contexts = 8;
4376 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
4377 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
4378 adev->gfx.config.sc_hiz_tile_fifo_size = 0;
4379 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
4381 adev->gfx.config.gb_addr_config_fields.num_pkrs =
4386 adev->gfx.config.max_hw_contexts = 8;
4387 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
4388 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
4389 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
4390 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
4398 adev->gfx.config.gb_addr_config = gb_addr_config;
4400 adev->gfx.config.gb_addr_config_fields.num_pipes = 1 <<
4401 REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4404 adev->gfx.config.max_tile_pipes =
4405 adev->gfx.config.gb_addr_config_fields.num_pipes;
4407 adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 <<
4408 REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4410 adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 <<
4411 REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4413 adev->gfx.config.gb_addr_config_fields.num_se = 1 <<
4414 REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4416 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 +
4417 REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4428 ring = &adev->gfx.gfx_ring[ring_id];
4447 return amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type,
4458 ring = &adev->gfx.compute_ring[ring_id];
4468 ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr
4474 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec)
4479 return amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type,
4495 adev->gfx.me.num_me = 1;
4496 adev->gfx.me.num_pipe_per_me = 1;
4497 adev->gfx.me.num_queue_per_pipe = 1;
4498 adev->gfx.mec.num_mec = 2;
4499 adev->gfx.mec.num_pipe_per_mec = 4;
4500 adev->gfx.mec.num_queue_per_pipe = 8;
4510 adev->gfx.me.num_me = 1;
4511 adev->gfx.me.num_pipe_per_me = 1;
4512 adev->gfx.me.num_queue_per_pipe = 1;
4513 adev->gfx.mec.num_mec = 2;
4514 adev->gfx.mec.num_pipe_per_mec = 4;
4515 adev->gfx.mec.num_queue_per_pipe = 4;
4518 adev->gfx.me.num_me = 1;
4519 adev->gfx.me.num_pipe_per_me = 1;
4520 adev->gfx.me.num_queue_per_pipe = 1;
4521 adev->gfx.mec.num_mec = 1;
4522 adev->gfx.mec.num_pipe_per_mec = 4;
4523 adev->gfx.mec.num_queue_per_pipe = 8;
4530 &adev->gfx.kiq[0].irq);
4537 &adev->gfx.eop_irq);
4543 &adev->gfx.priv_reg_irq);
4549 &adev->gfx.priv_inst_irq);
4553 adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE;
4557 if (adev->gfx.rlc.funcs) {
4558 if (adev->gfx.rlc.funcs->init) {
4559 r = adev->gfx.rlc.funcs->init(adev);
4573 /* set up the gfx ring */
4574 for (i = 0; i < adev->gfx.me.num_me; i++) {
4575 for (j = 0; j < adev->gfx.me.num_queue_per_pipe; j++) {
4576 for (k = 0; k < adev->gfx.me.num_pipe_per_me; k++) {
4591 for (i = 0; i < adev->gfx.mec.num_mec; ++i) {
4592 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) {
4593 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) {
4615 kiq = &adev->gfx.kiq[0];
4632 adev->gfx.ce_ram_size = F32_CE_PROGRAM_RAM_SIZE;
4641 amdgpu_bo_free_kernel(&adev->gfx.pfp.pfp_fw_obj,
4642 &adev->gfx.pfp.pfp_fw_gpu_addr,
4643 (void **)&adev->gfx.pfp.pfp_fw_ptr);
4648 amdgpu_bo_free_kernel(&adev->gfx.ce.ce_fw_obj,
4649 &adev->gfx.ce.ce_fw_gpu_addr,
4650 (void **)&adev->gfx.ce.ce_fw_ptr);
4655 amdgpu_bo_free_kernel(&adev->gfx.me.me_fw_obj,
4656 &adev->gfx.me.me_fw_gpu_addr,
4657 (void **)&adev->gfx.me.me_fw_ptr);
4665 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
4666 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]);
4667 for (i = 0; i < adev->gfx.num_compute_rings; i++)
4668 amdgpu_ring_fini(&adev->gfx.compute_ring[i]);
4673 amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq[0].ring);
4728 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se /
4729 adev->gfx.config.max_sh_per_se);
4740 u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se /
4741 adev->gfx.config.max_sh_per_se;
4744 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
4745 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
4746 bitmap = i * adev->gfx.config.max_sh_per_se + j;
4754 active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) *
4761 adev->gfx.config.backend_enable_mask = active_rbs;
4762 adev->gfx.config.num_rbs = hweight32(active_rbs);
4781 num_sc = adev->gfx.config.max_shader_engines * adev->gfx.config.max_sh_per_se *
4782 adev->gfx.config.num_sc_per_sh;
4786 num_rb_per_sc = enabled_rb_per_sh / adev->gfx.config.num_sc_per_sh;
4788 num_packer_per_sc = adev->gfx.config.num_packer_per_sc;
4872 * Initialize all compute and user-gfx VMIDs to have no GDS, GWS, or OA
4889 int max_wgp_per_sh = adev->gfx.config.max_cu_per_sh >> 1;
4914 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
4915 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
4966 adev->gfx.config.tcc_disabled_mask =
4979 gfx_v10_0_get_cu_info(adev, &adev->gfx.cu_info);
4981 adev->gfx.config.pa_sc_tile_steering_override =
5032 adev->gfx.rlc.funcs->get_csb_buffer(adev, adev->gfx.rlc.cs_ptr);
5037 adev->gfx.rlc.clear_state_gpu_addr >> 32);
5039 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc);
5040 WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size);
5043 adev->gfx.rlc.clear_state_gpu_addr >> 32);
5045 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc);
5046 WREG32_SOC15(GC, 0, mmRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size);
5119 if (!adev->gfx.rlc_fw)
5122 hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
5125 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
5136 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version);
5164 adev->gfx.rlc.funcs->stop(adev);
5188 adev->gfx.rlc.funcs->start(adev);
5213 &adev->gfx.rlc.rlc_toc_bo,
5214 &adev->gfx.rlc.rlc_toc_gpu_addr,
5215 (void **)&adev->gfx.rlc.rlc_toc_buf);
5222 memcpy(adev->gfx.rlc.rlc_toc_buf, adev->psp.toc.start_addr, adev->psp.toc.size_bytes);
5224 rlc_toc = (RLC_TABLE_OF_CONTENT *)adev->gfx.rlc.rlc_toc_buf;
5275 &adev->gfx.rlc.rlc_autoload_bo,
5276 &adev->gfx.rlc.rlc_autoload_gpu_addr,
5277 (void **)&adev->gfx.rlc.rlc_autoload_ptr);
5288 amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_toc_bo,
5289 &adev->gfx.rlc.rlc_toc_gpu_addr,
5290 (void **)&adev->gfx.rlc.rlc_toc_buf);
5291 amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_autoload_bo,
5292 &adev->gfx.rlc.rlc_autoload_gpu_addr,
5293 (void **)&adev->gfx.rlc.rlc_autoload_ptr);
5303 char *ptr = adev->gfx.rlc.rlc_autoload_ptr;
5328 data = adev->gfx.rlc.rlc_toc_buf;
5345 adev->gfx.pfp_fw->data;
5346 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data +
5355 adev->gfx.ce_fw->data;
5356 fw_data = (const __le32 *)(adev->gfx.ce_fw->data +
5365 adev->gfx.me_fw->data;
5366 fw_data = (const __le32 *)(adev->gfx.me_fw->data +
5375 adev->gfx.rlc_fw->data;
5376 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
5385 adev->gfx.mec_fw->data;
5386 fw_data = (const __le32 *) (adev->gfx.mec_fw->data +
5442 gpu_addr = adev->gfx.rlc.rlc_autoload_gpu_addr + rlc_g_offset;
5491 addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
5528 addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
5565 addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
5602 addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
5679 DRM_ERROR("failed to %s cp gfx\n", enable ? "unhalt" : "halt");
5694 adev->gfx.pfp_fw->data;
5698 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data +
5704 &adev->gfx.pfp.pfp_fw_obj,
5705 &adev->gfx.pfp.pfp_fw_gpu_addr,
5706 (void **)&adev->gfx.pfp.pfp_fw_ptr);
5713 memcpy(adev->gfx.pfp.pfp_fw_ptr, fw_data, fw_size);
5715 amdgpu_bo_kunmap(adev->gfx.pfp.pfp_fw_obj);
5716 amdgpu_bo_unreserve(adev->gfx.pfp.pfp_fw_obj);
5747 adev->gfx.pfp.pfp_fw_gpu_addr & 0xFFFFF000);
5749 upper_32_bits(adev->gfx.pfp.pfp_fw_gpu_addr));
5757 WREG32_SOC15(GC, 0, mmCP_HYP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version);
5772 adev->gfx.ce_fw->data;
5776 fw_data = (const __le32 *)(adev->gfx.ce_fw->data +
5782 &adev->gfx.ce.ce_fw_obj,
5783 &adev->gfx.ce.ce_fw_gpu_addr,
5784 (void **)&adev->gfx.ce.ce_fw_ptr);
5791 memcpy(adev->gfx.ce.ce_fw_ptr, fw_data, fw_size);
5793 amdgpu_bo_kunmap(adev->gfx.ce.ce_fw_obj);
5794 amdgpu_bo_unreserve(adev->gfx.ce.ce_fw_obj);
5824 adev->gfx.ce.ce_fw_gpu_addr & 0xFFFFF000);
5826 upper_32_bits(adev->gfx.ce.ce_fw_gpu_addr));
5834 WREG32_SOC15(GC, 0, mmCP_HYP_CE_UCODE_ADDR, adev->gfx.ce_fw_version);
5849 adev->gfx.me_fw->data;
5853 fw_data = (const __le32 *)(adev->gfx.me_fw->data +
5859 &adev->gfx.me.me_fw_obj,
5860 &adev->gfx.me.me_fw_gpu_addr,
5861 (void **)&adev->gfx.me.me_fw_ptr);
5868 memcpy(adev->gfx.me.me_fw_ptr, fw_data, fw_size);
5870 amdgpu_bo_kunmap(adev->gfx.me.me_fw_obj);
5871 amdgpu_bo_unreserve(adev->gfx.me.me_fw_obj);
5901 adev->gfx.me.me_fw_gpu_addr & 0xFFFFF000);
5903 upper_32_bits(adev->gfx.me.me_fw_gpu_addr));
5911 WREG32_SOC15(GC, 0, mmCP_HYP_ME_UCODE_ADDR, adev->gfx.me_fw_version);
5920 if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw)
5956 adev->gfx.config.max_hw_contexts - 1);
5961 ring = &adev->gfx.gfx_ring[0];
5993 amdgpu_ring_write(ring, adev->gfx.config.pa_sc_tile_steering_override);
6009 if (adev->gfx.num_gfx_rings > 1) {
6010 /* maximum supported gfx ring is 2 */
6011 ring = &adev->gfx.gfx_ring[1];
6095 /* Init gfx ring 0 for pipe 0 */
6100 ring = &adev->gfx.gfx_ring[0];
6138 /* Init gfx ring 1 for pipe 1 */
6139 if (adev->gfx.num_gfx_rings > 1) {
6142 /* maximum supported gfx ring is 2 */
6143 ring = &adev->gfx.gfx_ring[1];
6223 adev->gfx.kiq[0].ring.sched.ready = false;
6236 if (!adev->gfx.mec_fw)
6241 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
6245 (adev->gfx.mec_fw->data +
6276 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO, adev->gfx.mec.mec_fw_gpu_addr &
6279 upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr));
6288 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR, adev->gfx.mec_fw_version);
6357 /* set up gfx hqd wptr */
6377 /* set up gfx queue priority */
6385 /* set up gfx hqd base. this is similar as CP_RB_BASE */
6436 int mqd_idx = ring - &adev->gfx.gfx_ring[0];
6445 * if there are 2 gfx rings, set the lower doorbell
6454 if (adev->gfx.me.mqd_backup[mqd_idx])
6455 memcpy_fromio(adev->gfx.me.mqd_backup[mqd_idx], mqd, sizeof(*mqd));
6458 if (adev->gfx.me.mqd_backup[mqd_idx])
6459 memcpy_toio(mqd, adev->gfx.me.mqd_backup[mqd_idx], sizeof(*mqd));
6474 for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
6475 ring = &adev->gfx.gfx_ring[i];
6732 if (adev->gfx.kiq[0].mqd_backup)
6733 memcpy_toio(mqd, adev->gfx.kiq[0].mqd_backup, sizeof(*mqd));
6755 if (adev->gfx.kiq[0].mqd_backup)
6756 memcpy_fromio(adev->gfx.kiq[0].mqd_backup, mqd, sizeof(*mqd));
6766 int mqd_idx = ring - &adev->gfx.compute_ring[0];
6776 if (adev->gfx.mec.mqd_backup[mqd_idx])
6777 memcpy_fromio(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd));
6780 if (adev->gfx.mec.mqd_backup[mqd_idx])
6781 memcpy_toio(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd));
6796 ring = &adev->gfx.kiq[0].ring;
6822 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
6823 ring = &adev->gfx.compute_ring[i];
6884 for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
6885 ring = &adev->gfx.gfx_ring[i];
6891 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
6892 ring = &adev->gfx.compute_ring[i];
7111 * For gfx 10, rlc firmware loading relies on smu firmware is
7159 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0);
7160 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0);
7395 adev->gfx.funcs = &gfx_v10_0_gfx_funcs;
7403 adev->gfx.num_gfx_rings = GFX10_NUM_GFX_RINGS_NV1X;
7413 adev->gfx.num_gfx_rings = GFX10_NUM_GFX_RINGS_Sienna_Cichlid;
7419 adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev),
7440 r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0);
7444 r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0);
8305 if (ring->adev->gfx.mcbp && (ib->flags & AMDGPU_IB_FLAG_PREEMPT)) {
8480 if (ring->adev->gfx.mcbp)
8541 struct amdgpu_kiq *kiq = &adev->gfx.kiq[0];
8596 gfx[0].gfx_meta_data) +
8634 gfx[0].gfx_meta_data) +
8642 gfx[0].gds_backup) +
8738 fw_version_ok = adev->gfx.cp_fw_write_wait;
8929 amdgpu_fence_process(&adev->gfx.gfx_ring[0]);
8931 amdgpu_fence_process(&adev->gfx.gfx_ring[1]);
8935 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
8936 ring = &adev->gfx.compute_ring[i];
9004 for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
9005 ring = &adev->gfx.gfx_ring[i];
9006 /* we only enabled 1 gfx queue per pipe for now */
9013 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
9014 ring = &adev->gfx.compute_ring[i];
9049 struct amdgpu_ring *ring = &(adev->gfx.kiq[0].ring);
9093 struct amdgpu_ring *ring = &(adev->gfx.kiq[0].ring);
9269 adev->gfx.kiq[0].ring.funcs = &gfx_v10_0_ring_funcs_kiq;
9271 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
9272 adev->gfx.gfx_ring[i].funcs = &gfx_v10_0_ring_funcs_gfx;
9274 for (i = 0; i < adev->gfx.num_compute_rings; i++)
9275 adev->gfx.compute_ring[i].funcs = &gfx_v10_0_ring_funcs_compute;
9300 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST;
9301 adev->gfx.eop_irq.funcs = &gfx_v10_0_eop_irq_funcs;
9303 adev->gfx.kiq[0].irq.num_types = AMDGPU_CP_KIQ_IRQ_LAST;
9304 adev->gfx.kiq[0].irq.funcs = &gfx_v10_0_kiq_irq_funcs;
9306 adev->gfx.priv_reg_irq.num_types = 1;
9307 adev->gfx.priv_reg_irq.funcs = &gfx_v10_0_priv_reg_irq_funcs;
9309 adev->gfx.priv_inst_irq.num_types = 1;
9310 adev->gfx.priv_inst_irq.funcs = &gfx_v10_0_priv_inst_irq_funcs;
9327 adev->gfx.rlc.funcs = &gfx_v10_0_rlc_funcs;
9331 adev->gfx.rlc.funcs = &gfx_v10_0_rlc_funcs_sriov;
9340 unsigned int total_cu = adev->gfx.config.max_cu_per_sh *
9341 adev->gfx.config.max_sh_per_se *
9342 adev->gfx.config.max_shader_engines;
9352 /* set gfx eng mqd */
9381 ~amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh >> 1);
9429 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
9430 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
9431 bitmap = i * adev->gfx.config.max_sh_per_se + j;
9448 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) {
9450 if (counter < adev->gfx.config.max_cu_per_sh)
9484 max_sa_mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_sh_per_se *
9485 adev->gfx.config.max_shader_engines);
9499 max_sa_per_se = adev->gfx.config.max_sh_per_se;
9501 max_shader_engines = adev->gfx.config.max_shader_engines;