Lines Matching refs:gfx
42 #include "ivsrcid/gfx/irqsrcs_gfx_11_0_0.h"
199 if (adev->enable_mes && !adev->gfx.kiq[0].ring.sched.ready) {
267 adev->gfx.kiq[0].pmf = &gfx_v11_0_kiq_pm4_funcs;
443 amdgpu_ucode_release(&adev->gfx.pfp_fw);
444 amdgpu_ucode_release(&adev->gfx.me_fw);
445 amdgpu_ucode_release(&adev->gfx.rlc_fw);
446 amdgpu_ucode_release(&adev->gfx.mec_fw);
448 kfree(adev->gfx.rlc.register_list_format);
480 if ((adev->gfx.me_fw_version >= 1505) &&
481 (adev->gfx.pfp_fw_version >= 1600) &&
482 (adev->gfx.mec_fw_version >= 512)) {
484 adev->gfx.cp_gfx_shadow = true;
486 adev->gfx.cp_gfx_shadow = false;
490 adev->gfx.cp_gfx_shadow = false;
509 err = amdgpu_ucode_request(adev, &adev->gfx.pfp_fw, fw_name);
513 adev->gfx.rs64_enable = amdgpu_ucode_hdr_version(
515 adev->gfx.pfp_fw->data, 2, 0);
516 if (adev->gfx.rs64_enable) {
526 err = amdgpu_ucode_request(adev, &adev->gfx.me_fw, fw_name);
529 if (adev->gfx.rs64_enable) {
539 err = amdgpu_ucode_request(adev, &adev->gfx.rlc_fw, fw_name);
542 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
551 err = amdgpu_ucode_request(adev, &adev->gfx.mec_fw, fw_name);
554 if (adev->gfx.rs64_enable) {
568 /* only one MEC for gfx 11.0.0. */
569 adev->gfx.mec2_fw = NULL;
574 amdgpu_ucode_release(&adev->gfx.pfp_fw);
575 amdgpu_ucode_release(&adev->gfx.me_fw);
576 amdgpu_ucode_release(&adev->gfx.rlc_fw);
577 amdgpu_ucode_release(&adev->gfx.mec_fw);
621 if (adev->gfx.rlc.cs_data == NULL)
633 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
652 buffer[count++] = cpu_to_le32(adev->gfx.config.pa_sc_tile_steering_override);
664 amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj,
665 &adev->gfx.rlc.clear_state_gpu_addr,
666 (void **)&adev->gfx.rlc.cs_ptr);
669 amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj,
670 &adev->gfx.rlc.cp_table_gpu_addr,
671 (void **)&adev->gfx.rlc.cp_table_ptr);
678 reg_access_ctrl = &adev->gfx.rlc.reg_access_ctrl[0];
686 adev->gfx.rlc.rlcg_reg_access_supported = true;
694 adev->gfx.rlc.cs_data = gfx11_cs_data;
696 cs_data = adev->gfx.rlc.cs_data;
706 if (adev->gfx.rlc.funcs->update_spm_vmid)
707 adev->gfx.rlc.funcs->update_spm_vmid(adev, 0xf);
714 amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL);
715 amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_obj, NULL, NULL);
716 amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_data_obj, NULL, NULL);
721 bitmap_zero(adev->gfx.me.queue_bitmap, AMDGPU_MAX_GFX_QUEUES);
732 bitmap_zero(adev->gfx.mec_bitmap[0].queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
736 mec_hpd_size = adev->gfx.num_compute_rings * GFX11_MEC_HPD_SIZE;
741 &adev->gfx.mec.hpd_eop_obj,
742 &adev->gfx.mec.hpd_eop_gpu_addr,
752 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj);
753 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);
842 if (adev->gfx.cp_gfx_shadow) {
871 adev->gfx.config.max_hw_contexts = 8;
872 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
873 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
874 adev->gfx.config.sc_hiz_tile_fifo_size = 0;
875 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
878 adev->gfx.ras = &gfx_v11_0_3_ras;
879 adev->gfx.config.max_hw_contexts = 8;
880 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
881 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
882 adev->gfx.config.sc_hiz_tile_fifo_size = 0;
883 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
887 adev->gfx.config.max_hw_contexts = 8;
888 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
889 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
890 adev->gfx.config.sc_hiz_tile_fifo_size = 0x80;
891 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x300;
908 ring = &adev->gfx.gfx_ring[ring_id];
925 r = amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type,
940 ring = &adev->gfx.compute_ring[ring_id];
950 ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr
956 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec)
961 r = amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type,
1017 &adev->gfx.rlc.rlc_autoload_bo,
1018 &adev->gfx.rlc.rlc_autoload_gpu_addr,
1019 (void **)&adev->gfx.rlc.rlc_autoload_ptr);
1037 char *ptr = adev->gfx.rlc.rlc_autoload_ptr;
1092 if (adev->gfx.rs64_enable) {
1095 adev->gfx.pfp_fw->data;
1097 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data +
1103 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data +
1112 adev->gfx.me_fw->data;
1114 fw_data = (const __le32 *)(adev->gfx.me_fw->data +
1120 fw_data = (const __le32 *)(adev->gfx.me_fw->data +
1129 adev->gfx.mec_fw->data;
1131 fw_data = (const __le32 *) (adev->gfx.mec_fw->data +
1137 fw_data = (const __le32 *) (adev->gfx.mec_fw->data +
1151 adev->gfx.pfp_fw->data;
1152 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data +
1160 adev->gfx.me_fw->data;
1161 fw_data = (const __le32 *)(adev->gfx.me_fw->data +
1169 adev->gfx.mec_fw->data;
1170 fw_data = (const __le32 *) (adev->gfx.mec_fw->data +
1180 adev->gfx.rlc_fw->data;
1181 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
1191 rlcv22_hdr = (const struct rlc_firmware_header_v2_2 *)adev->gfx.rlc_fw->data;
1193 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
1199 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
1284 gpu_addr = adev->gfx.rlc.rlc_autoload_gpu_addr + rlc_g_offset;
1292 if (adev->gfx.imu.funcs->load_microcode)
1293 adev->gfx.imu.funcs->load_microcode(adev);
1295 if (adev->gfx.imu.funcs->setup_imu)
1296 adev->gfx.imu.funcs->setup_imu(adev);
1297 if (adev->gfx.imu.funcs->start_imu)
1298 adev->gfx.imu.funcs->start_imu(adev);
1318 adev->gfx.me.num_me = 1;
1319 adev->gfx.me.num_pipe_per_me = 1;
1320 adev->gfx.me.num_queue_per_pipe = 1;
1321 adev->gfx.mec.num_mec = 2;
1322 adev->gfx.mec.num_pipe_per_mec = 4;
1323 adev->gfx.mec.num_queue_per_pipe = 4;
1327 adev->gfx.me.num_me = 1;
1328 adev->gfx.me.num_pipe_per_me = 1;
1329 adev->gfx.me.num_queue_per_pipe = 1;
1330 adev->gfx.mec.num_mec = 1;
1331 adev->gfx.mec.num_pipe_per_mec = 4;
1332 adev->gfx.mec.num_queue_per_pipe = 4;
1335 adev->gfx.me.num_me = 1;
1336 adev->gfx.me.num_pipe_per_me = 1;
1337 adev->gfx.me.num_queue_per_pipe = 1;
1338 adev->gfx.mec.num_mec = 1;
1339 adev->gfx.mec.num_pipe_per_mec = 4;
1340 adev->gfx.mec.num_queue_per_pipe = 8;
1352 &adev->gfx.eop_irq);
1359 &adev->gfx.priv_reg_irq);
1366 &adev->gfx.priv_inst_irq);
1373 &adev->gfx.rlc_gc_fed_irq);
1377 adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE;
1379 if (adev->gfx.imu.funcs) {
1380 if (adev->gfx.imu.funcs->init_microcode) {
1381 r = adev->gfx.imu.funcs->init_microcode(adev);
1401 /* set up the gfx ring */
1402 for (i = 0; i < adev->gfx.me.num_me; i++) {
1403 for (j = 0; j < adev->gfx.me.num_queue_per_pipe; j++) {
1404 for (k = 0; k < adev->gfx.me.num_pipe_per_me; k++) {
1419 for (i = 0; i < adev->gfx.mec.num_mec; ++i) {
1420 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) {
1421 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) {
1443 kiq = &adev->gfx.kiq[0];
1465 dev_err(adev->dev, "Failed to initialize gfx ras block!\n");
1474 amdgpu_bo_free_kernel(&adev->gfx.pfp.pfp_fw_obj,
1475 &adev->gfx.pfp.pfp_fw_gpu_addr,
1476 (void **)&adev->gfx.pfp.pfp_fw_ptr);
1478 amdgpu_bo_free_kernel(&adev->gfx.pfp.pfp_fw_data_obj,
1479 &adev->gfx.pfp.pfp_fw_data_gpu_addr,
1480 (void **)&adev->gfx.pfp.pfp_fw_data_ptr);
1485 amdgpu_bo_free_kernel(&adev->gfx.me.me_fw_obj,
1486 &adev->gfx.me.me_fw_gpu_addr,
1487 (void **)&adev->gfx.me.me_fw_ptr);
1489 amdgpu_bo_free_kernel(&adev->gfx.me.me_fw_data_obj,
1490 &adev->gfx.me.me_fw_data_gpu_addr,
1491 (void **)&adev->gfx.me.me_fw_data_ptr);
1496 amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_autoload_bo,
1497 &adev->gfx.rlc.rlc_autoload_gpu_addr,
1498 (void **)&adev->gfx.rlc.rlc_autoload_ptr);
1506 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
1507 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]);
1508 for (i = 0; i < adev->gfx.num_compute_rings; i++)
1509 amdgpu_ring_fini(&adev->gfx.compute_ring[i]);
1514 amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq[0].ring);
1570 sa_mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_sh_per_se *
1571 adev->gfx.config.max_shader_engines);
1589 rb_mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se *
1590 adev->gfx.config.max_shader_engines);
1610 max_sa = adev->gfx.config.max_shader_engines *
1611 adev->gfx.config.max_sh_per_se;
1612 rb_bitmap_width_per_sa = adev->gfx.config.max_backends_per_se /
1613 adev->gfx.config.max_sh_per_se;
1620 adev->gfx.config.backend_enable_mask = active_rb_bitmap;
1621 adev->gfx.config.num_rbs = hweight32(active_rb_bitmap);
1673 * Initialize all compute and user-gfx VMIDs to have no GDS, GWS, or OA
1697 adev->gfx.config.tcc_disabled_mask =
1711 gfx_v11_0_get_cu_info(adev, &adev->gfx.cu_info);
1713 adev->gfx.config.pa_sc_tile_steering_override = 0;
1717 adev->gfx.config.ta_cntl2_truncate_coord_mode =
1767 adev->gfx.rlc.funcs->get_csb_buffer(adev, adev->gfx.rlc.cs_ptr);
1770 adev->gfx.rlc.clear_state_gpu_addr >> 32);
1772 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc);
1773 WREG32_SOC15(GC, 0, regRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size);
1844 hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
1845 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
1856 WREG32_SOC15(GC, 0, regRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version);
1866 hdr = (const struct rlc_firmware_header_v2_2 *)adev->gfx.rlc_fw->data;
1868 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
1881 WREG32_SOC15(GC, 0, regRLC_LX6_IRAM_ADDR, adev->gfx.rlc_fw_version);
1883 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
1895 WREG32_SOC15(GC, 0, regRLC_LX6_IRAM_ADDR, adev->gfx.rlc_fw_version);
1910 hdr = (const struct rlc_firmware_header_v2_3 *)adev->gfx.rlc_fw->data;
1912 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
1925 WREG32_SOC15(GC, 0, regRLC_PACE_UCODE_ADDR, adev->gfx.rlc_fw_version);
1931 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
1944 WREG32_SOC15(GC, 0, regRLC_GPU_IOV_UCODE_ADDR, adev->gfx.rlc_fw_version);
1957 if (!adev->gfx.rlc_fw)
1960 hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
1996 adev->gfx.rlc.funcs->stop(adev);
2013 adev->gfx.rlc.funcs->start(adev);
2158 adev->gfx.pfp_fw->data;
2208 for (pipe_id = 0; pipe_id < adev->gfx.me.num_pipe_per_me; pipe_id++) {
2280 adev->gfx.me_fw->data;
2331 for (pipe_id = 0; pipe_id < adev->gfx.me.num_pipe_per_me; pipe_id++) {
2403 adev->gfx.mec_fw->data;
2417 for (i = 0; i < adev->gfx.mec.num_pipe_per_mec; i++) {
2486 adev->gfx.mec_fw->data;
2488 adev->gfx.me_fw->data;
2490 adev->gfx.pfp_fw->data;
2594 if (adev->gfx.rs64_enable) {
2595 addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
2597 addr2 = adev->gfx.rlc.rlc_autoload_gpu_addr +
2602 addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
2604 addr2 = adev->gfx.rlc.rlc_autoload_gpu_addr +
2609 addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
2611 addr2 = adev->gfx.rlc.rlc_autoload_gpu_addr +
2617 addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
2622 addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
2627 addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
2654 DRM_ERROR("failed to %s cp gfx\n", enable ? "unhalt" : "halt");
2667 adev->gfx.pfp_fw->data;
2671 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data +
2677 &adev->gfx.pfp.pfp_fw_obj,
2678 &adev->gfx.pfp.pfp_fw_gpu_addr,
2679 (void **)&adev->gfx.pfp.pfp_fw_ptr);
2686 memcpy(adev->gfx.pfp.pfp_fw_ptr, fw_data, fw_size);
2688 amdgpu_bo_kunmap(adev->gfx.pfp.pfp_fw_obj);
2689 amdgpu_bo_unreserve(adev->gfx.pfp.pfp_fw_obj);
2691 gfx_v11_0_config_pfp_cache(adev, adev->gfx.pfp.pfp_fw_gpu_addr);
2699 WREG32_SOC15(GC, 0, regCP_HYP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version);
2714 adev->gfx.pfp_fw->data;
2719 fw_ucode = (const __le32 *)(adev->gfx.pfp_fw->data +
2723 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data +
2732 &adev->gfx.pfp.pfp_fw_obj,
2733 &adev->gfx.pfp.pfp_fw_gpu_addr,
2734 (void **)&adev->gfx.pfp.pfp_fw_ptr);
2745 &adev->gfx.pfp.pfp_fw_data_obj,
2746 &adev->gfx.pfp.pfp_fw_data_gpu_addr,
2747 (void **)&adev->gfx.pfp.pfp_fw_data_ptr);
2754 memcpy(adev->gfx.pfp.pfp_fw_ptr, fw_ucode, fw_ucode_size);
2755 memcpy(adev->gfx.pfp.pfp_fw_data_ptr, fw_data, fw_data_size);
2757 amdgpu_bo_kunmap(adev->gfx.pfp.pfp_fw_obj);
2758 amdgpu_bo_kunmap(adev->gfx.pfp.pfp_fw_data_obj);
2759 amdgpu_bo_unreserve(adev->gfx.pfp.pfp_fw_obj);
2760 amdgpu_bo_unreserve(adev->gfx.pfp.pfp_fw_data_obj);
2766 lower_32_bits(adev->gfx.pfp.pfp_fw_gpu_addr));
2768 upper_32_bits(adev->gfx.pfp.pfp_fw_gpu_addr));
2813 for (pipe_id = 0; pipe_id < adev->gfx.me.num_pipe_per_me; pipe_id++) {
2844 lower_32_bits(adev->gfx.pfp.pfp_fw_data_gpu_addr));
2846 upper_32_bits(adev->gfx.pfp.pfp_fw_data_gpu_addr));
2885 adev->gfx.me_fw->data;
2889 fw_data = (const __le32 *)(adev->gfx.me_fw->data +
2895 &adev->gfx.me.me_fw_obj,
2896 &adev->gfx.me.me_fw_gpu_addr,
2897 (void **)&adev->gfx.me.me_fw_ptr);
2904 memcpy(adev->gfx.me.me_fw_ptr, fw_data, fw_size);
2906 amdgpu_bo_kunmap(adev->gfx.me.me_fw_obj);
2907 amdgpu_bo_unreserve(adev->gfx.me.me_fw_obj);
2909 gfx_v11_0_config_me_cache(adev, adev->gfx.me.me_fw_gpu_addr);
2917 WREG32_SOC15(GC, 0, regCP_HYP_ME_UCODE_ADDR, adev->gfx.me_fw_version);
2932 adev->gfx.me_fw->data;
2937 fw_ucode = (const __le32 *)(adev->gfx.me_fw->data +
2941 fw_data = (const __le32 *)(adev->gfx.me_fw->data +
2950 &adev->gfx.me.me_fw_obj,
2951 &adev->gfx.me.me_fw_gpu_addr,
2952 (void **)&adev->gfx.me.me_fw_ptr);
2963 &adev->gfx.me.me_fw_data_obj,
2964 &adev->gfx.me.me_fw_data_gpu_addr,
2965 (void **)&adev->gfx.me.me_fw_data_ptr);
2972 memcpy(adev->gfx.me.me_fw_ptr, fw_ucode, fw_ucode_size);
2973 memcpy(adev->gfx.me.me_fw_data_ptr, fw_data, fw_data_size);
2975 amdgpu_bo_kunmap(adev->gfx.me.me_fw_obj);
2976 amdgpu_bo_kunmap(adev->gfx.me.me_fw_data_obj);
2977 amdgpu_bo_unreserve(adev->gfx.me.me_fw_obj);
2978 amdgpu_bo_unreserve(adev->gfx.me.me_fw_data_obj);
2984 lower_32_bits(adev->gfx.me.me_fw_gpu_addr));
2986 upper_32_bits(adev->gfx.me.me_fw_gpu_addr));
3032 for (pipe_id = 0; pipe_id < adev->gfx.me.num_pipe_per_me; pipe_id++) {
3063 lower_32_bits(adev->gfx.me.me_fw_data_gpu_addr));
3065 upper_32_bits(adev->gfx.me.me_fw_data_gpu_addr));
3100 if (!adev->gfx.me_fw || !adev->gfx.pfp_fw)
3105 if (adev->gfx.rs64_enable)
3114 if (adev->gfx.rs64_enable)
3136 adev->gfx.config.max_hw_contexts - 1);
3142 ring = &adev->gfx.gfx_ring[0];
3174 amdgpu_ring_write(ring, adev->gfx.config.pa_sc_tile_steering_override);
3185 if (adev->gfx.num_gfx_rings > 1) {
3186 /* maximum supported gfx ring is 2 */
3187 ring = &adev->gfx.gfx_ring[1];
3251 /* Init gfx ring 0 for pipe 0 */
3256 ring = &adev->gfx.gfx_ring[0];
3291 /* Init gfx ring 1 for pipe 1 */
3292 if (adev->gfx.num_gfx_rings > 1) {
3295 /* maximum supported gfx ring is 2 */
3296 ring = &adev->gfx.gfx_ring[1];
3342 if (adev->gfx.rs64_enable) {
3391 if (!adev->gfx.mec_fw)
3396 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
3400 (adev->gfx.mec_fw->data +
3406 &adev->gfx.mec.mec_fw_obj,
3407 &adev->gfx.mec.mec_fw_gpu_addr,
3417 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj);
3418 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj);
3420 gfx_v11_0_config_mec_cache(adev, adev->gfx.mec.mec_fw_gpu_addr);
3429 WREG32_SOC15(GC, 0, regCP_MEC_ME1_UCODE_ADDR, adev->gfx.mec_fw_version);
3443 if (!adev->gfx.mec_fw)
3448 mec_hdr = (const struct gfx_firmware_header_v2_0 *)adev->gfx.mec_fw->data;
3451 fw_ucode = (const __le32 *) (adev->gfx.mec_fw->data +
3455 fw_data = (const __le32 *) (adev->gfx.mec_fw->data +
3463 &adev->gfx.mec.mec_fw_obj,
3464 &adev->gfx.mec.mec_fw_gpu_addr,
3476 &adev->gfx.mec.mec_fw_data_obj,
3477 &adev->gfx.mec.mec_fw_data_gpu_addr,
3488 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj);
3489 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_data_obj);
3490 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj);
3491 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_data_obj);
3505 for (i = 0; i < adev->gfx.mec.num_pipe_per_mec; i++) {
3508 WREG32_SOC15(GC, 0, regCP_MEC_MDBASE_LO, adev->gfx.mec.mec_fw_data_gpu_addr);
3510 upper_32_bits(adev->gfx.mec.mec_fw_data_gpu_addr));
3518 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_LO, adev->gfx.mec.mec_fw_gpu_addr);
3520 upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr));
3603 /* set up gfx hqd wptr */
3634 /* set up gfx hqd base. this is similar as CP_RB_BASE */
3685 int mqd_idx = ring - &adev->gfx.gfx_ring[0];
3694 if (adev->gfx.me.mqd_backup[mqd_idx])
3695 memcpy_fromio(adev->gfx.me.mqd_backup[mqd_idx], mqd, sizeof(*mqd));
3698 if (adev->gfx.me.mqd_backup[mqd_idx])
3699 memcpy_toio(mqd, adev->gfx.me.mqd_backup[mqd_idx], sizeof(*mqd));
3714 for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
3715 ring = &adev->gfx.gfx_ring[i];
3987 if (adev->gfx.kiq[0].mqd_backup)
3988 memcpy_toio(mqd, adev->gfx.kiq[0].mqd_backup, sizeof(*mqd));
4010 if (adev->gfx.kiq[0].mqd_backup)
4011 memcpy_fromio(adev->gfx.kiq[0].mqd_backup, mqd, sizeof(*mqd));
4021 int mqd_idx = ring - &adev->gfx.compute_ring[0];
4031 if (adev->gfx.mec.mqd_backup[mqd_idx])
4032 memcpy_fromio(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd));
4035 if (adev->gfx.mec.mqd_backup[mqd_idx])
4036 memcpy_toio(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd));
4051 ring = &adev->gfx.kiq[0].ring;
4079 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
4080 ring = &adev->gfx.compute_ring[i];
4115 if (adev->gfx.rs64_enable)
4151 for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
4152 ring = &adev->gfx.gfx_ring[i];
4158 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
4159 ring = &adev->gfx.compute_ring[i];
4199 if (adev->gfx.rs64_enable) {
4221 adev->gfx.config.gb_addr_config_fields.num_pkrs =
4224 adev->gfx.config.gb_addr_config = gb_addr_config;
4226 adev->gfx.config.gb_addr_config_fields.num_pipes = 1 <<
4227 REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4230 adev->gfx.config.max_tile_pipes =
4231 adev->gfx.config.gb_addr_config_fields.num_pipes;
4233 adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 <<
4234 REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4236 adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 <<
4237 REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4239 adev->gfx.config.gb_addr_config_fields.num_se = 1 <<
4240 REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4242 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 +
4243 REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4268 if (adev->gfx.imu.funcs) {
4270 if (adev->gfx.imu.funcs->program_rlc_ram)
4271 adev->gfx.imu.funcs->program_rlc_ram(adev);
4279 if (adev->gfx.imu.funcs && (amdgpu_dpm > 0)) {
4280 if (adev->gfx.imu.funcs->load_microcode)
4281 adev->gfx.imu.funcs->load_microcode(adev);
4282 if (adev->gfx.imu.funcs->setup_imu)
4283 adev->gfx.imu.funcs->setup_imu(adev);
4284 if (adev->gfx.imu.funcs->start_imu)
4285 adev->gfx.imu.funcs->start_imu(adev);
4302 adev->gfx.is_poweron = true;
4308 adev->gfx.rs64_enable)
4321 * For gfx 11, rlc firmware loading relies on smu firmware is
4361 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0);
4362 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0);
4389 adev->gfx.is_poweron = false;
4449 for (i = 0; i < adev->gfx.mec.num_mec; ++i) {
4450 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) {
4451 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) {
4463 for (i = 0; i < adev->gfx.me.num_me; ++i) {
4464 for (j = 0; j < adev->gfx.me.num_queue_per_pipe; j++) {
4465 for (k = 0; k < adev->gfx.me.num_pipe_per_me; k++) {
4559 for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
4560 ring = &adev->gfx.gfx_ring[i];
4566 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
4567 ring = &adev->gfx.compute_ring[i];
4591 mutex_lock(&adev->gfx.gpu_clock_mutex);
4597 mutex_unlock(&adev->gfx.gpu_clock_mutex);
4646 adev->gfx.funcs = &gfx_v11_0_gfx_funcs;
4648 adev->gfx.num_gfx_rings = GFX11_NUM_GFX_RINGS;
4649 adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev),
4670 r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0);
4674 r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0);
5300 if (ring->adev->gfx.mcbp && (ib->flags & AMDGPU_IB_FLAG_PREEMPT)) {
5495 if (!adev->gfx.cp_gfx_shadow)
5542 struct amdgpu_kiq *kiq = &adev->gfx.kiq[0];
5595 gfx[0].gfx_meta_data) +
5603 gfx[0].gds_backup) +
5878 amdgpu_fence_process(&adev->gfx.gfx_ring[0]);
5880 amdgpu_fence_process(&adev->gfx.gfx_ring[1]);
5884 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
5885 ring = &adev->gfx.compute_ring[i];
5953 for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
5954 ring = &adev->gfx.gfx_ring[i];
5955 /* we only enabled 1 gfx queue per pipe for now */
5962 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
5963 ring = &adev->gfx.compute_ring[i];
5997 if (adev->gfx.ras && adev->gfx.ras->rlc_gc_fed_irq)
5998 return adev->gfx.ras->rlc_gc_fed_irq(adev, source, entry);
6010 struct amdgpu_ring *ring = &(adev->gfx.kiq[0].ring);
6208 adev->gfx.kiq[0].ring.funcs = &gfx_v11_0_ring_funcs_kiq;
6210 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
6211 adev->gfx.gfx_ring[i].funcs = &gfx_v11_0_ring_funcs_gfx;
6213 for (i = 0; i < adev->gfx.num_compute_rings; i++)
6214 adev->gfx.compute_ring[i].funcs = &gfx_v11_0_ring_funcs_compute;
6238 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST;
6239 adev->gfx.eop_irq.funcs = &gfx_v11_0_eop_irq_funcs;
6241 adev->gfx.priv_reg_irq.num_types = 1;
6242 adev->gfx.priv_reg_irq.funcs = &gfx_v11_0_priv_reg_irq_funcs;
6244 adev->gfx.priv_inst_irq.num_types = 1;
6245 adev->gfx.priv_inst_irq.funcs = &gfx_v11_0_priv_inst_irq_funcs;
6247 adev->gfx.rlc_gc_fed_irq.num_types = 1; /* 0x80 FED error */
6248 adev->gfx.rlc_gc_fed_irq.funcs = &gfx_v11_0_rlc_gc_fed_irq_funcs;
6255 adev->gfx.imu.mode = MISSION_MODE;
6257 adev->gfx.imu.mode = DEBUG_MODE;
6259 adev->gfx.imu.funcs = &gfx_v11_0_imu_funcs;
6264 adev->gfx.rlc.funcs = &gfx_v11_0_rlc_funcs;
6269 unsigned total_cu = adev->gfx.config.max_cu_per_sh *
6270 adev->gfx.config.max_sh_per_se *
6271 adev->gfx.config.max_shader_engines;
6281 /* set gfx eng mqd */
6317 amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh >> 1);
6353 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
6354 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
6355 bitmap = i * adev->gfx.config.max_sh_per_se + j;
6383 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) {