1/* 2 * Copyright 2014 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 */ 25 26#include <linux/firmware.h> 27#include "amdgpu.h" 28#include "amdgpu_gfx.h" 29#include "amdgpu_rlc.h" 30#include "amdgpu_ras.h" 31#include "amdgpu_xcp.h" 32 33/* delay 0.1 second to enable gfx off feature */ 34#define GFX_OFF_DELAY_ENABLE msecs_to_jiffies(100) 35 36#define GFX_OFF_NO_DELAY 0 37 38/* 39 * GPU GFX IP block helpers function. 40 */ 41 42int amdgpu_gfx_mec_queue_to_bit(struct amdgpu_device *adev, int mec, 43 int pipe, int queue) 44{ 45 int bit = 0; 46 47 bit += mec * adev->gfx.mec.num_pipe_per_mec 48 * adev->gfx.mec.num_queue_per_pipe; 49 bit += pipe * adev->gfx.mec.num_queue_per_pipe; 50 bit += queue; 51 52 return bit; 53} 54 55void amdgpu_queue_mask_bit_to_mec_queue(struct amdgpu_device *adev, int bit, 56 int *mec, int *pipe, int *queue) 57{ 58 *queue = bit % adev->gfx.mec.num_queue_per_pipe; 59 *pipe = (bit / adev->gfx.mec.num_queue_per_pipe) 60 % adev->gfx.mec.num_pipe_per_mec; 61 *mec = (bit / adev->gfx.mec.num_queue_per_pipe) 62 / adev->gfx.mec.num_pipe_per_mec; 63 64} 65 66bool amdgpu_gfx_is_mec_queue_enabled(struct amdgpu_device *adev, 67 int xcc_id, int mec, int pipe, int queue) 68{ 69 return test_bit(amdgpu_gfx_mec_queue_to_bit(adev, mec, pipe, queue), 70 adev->gfx.mec_bitmap[xcc_id].queue_bitmap); 71} 72 73int amdgpu_gfx_me_queue_to_bit(struct amdgpu_device *adev, 74 int me, int pipe, int queue) 75{ 76 int bit = 0; 77 78 bit += me * adev->gfx.me.num_pipe_per_me 79 * adev->gfx.me.num_queue_per_pipe; 80 bit += pipe * adev->gfx.me.num_queue_per_pipe; 81 bit += queue; 82 83 return bit; 84} 85 86void amdgpu_gfx_bit_to_me_queue(struct amdgpu_device *adev, int bit, 87 int *me, int *pipe, int *queue) 88{ 89 *queue = bit % adev->gfx.me.num_queue_per_pipe; 90 *pipe = (bit / adev->gfx.me.num_queue_per_pipe) 91 % adev->gfx.me.num_pipe_per_me; 92 *me = (bit / adev->gfx.me.num_queue_per_pipe) 93 / adev->gfx.me.num_pipe_per_me; 94} 95 96bool amdgpu_gfx_is_me_queue_enabled(struct amdgpu_device *adev, 97 int me, int pipe, int queue) 98{ 99 return test_bit(amdgpu_gfx_me_queue_to_bit(adev, me, pipe, queue), 100 adev->gfx.me.queue_bitmap); 101} 102 103/** 104 * amdgpu_gfx_parse_disable_cu - Parse the disable_cu module parameter 105 * 106 * @mask: array in which the per-shader array disable masks will be stored 107 * @max_se: number of SEs 108 * @max_sh: number of SHs 109 * 110 * The bitmask of CUs to be disabled in the shader array determined by se and 111 * sh is stored in mask[se * max_sh + sh]. 112 */ 113void amdgpu_gfx_parse_disable_cu(unsigned int *mask, unsigned int max_se, unsigned int max_sh) 114{ 115 unsigned int se, sh, cu; 116 const char *p; 117 118 memset(mask, 0, sizeof(*mask) * max_se * max_sh); 119 120 if (!amdgpu_disable_cu || !*amdgpu_disable_cu) 121 return; 122 123#ifdef notyet 124 p = amdgpu_disable_cu; 125 for (;;) { 126 char *next; 127 int ret = sscanf(p, "%u.%u.%u", &se, &sh, &cu); 128 129 if (ret < 3) { 130 DRM_ERROR("amdgpu: could not parse disable_cu\n"); 131 return; 132 } 133 134 if (se < max_se && sh < max_sh && cu < 16) { 135 DRM_INFO("amdgpu: disabling CU %u.%u.%u\n", se, sh, cu); 136 mask[se * max_sh + sh] |= 1u << cu; 137 } else { 138 DRM_ERROR("amdgpu: disable_cu %u.%u.%u is out of range\n", 139 se, sh, cu); 140 } 141 142 next = strchr(p, ','); 143 if (!next) 144 break; 145 p = next + 1; 146 } 147#endif 148} 149 150static bool amdgpu_gfx_is_graphics_multipipe_capable(struct amdgpu_device *adev) 151{ 152 return amdgpu_async_gfx_ring && adev->gfx.me.num_pipe_per_me > 1; 153} 154 155static bool amdgpu_gfx_is_compute_multipipe_capable(struct amdgpu_device *adev) 156{ 157 if (amdgpu_compute_multipipe != -1) { 158 DRM_INFO("amdgpu: forcing compute pipe policy %d\n", 159 amdgpu_compute_multipipe); 160 return amdgpu_compute_multipipe == 1; 161 } 162 163 if (adev->ip_versions[GC_HWIP][0] > IP_VERSION(9, 0, 0)) 164 return true; 165 166 /* FIXME: spreading the queues across pipes causes perf regressions 167 * on POLARIS11 compute workloads */ 168 if (adev->asic_type == CHIP_POLARIS11) 169 return false; 170 171 return adev->gfx.mec.num_mec > 1; 172} 173 174bool amdgpu_gfx_is_high_priority_graphics_queue(struct amdgpu_device *adev, 175 struct amdgpu_ring *ring) 176{ 177 int queue = ring->queue; 178 int pipe = ring->pipe; 179 180 /* Policy: use pipe1 queue0 as high priority graphics queue if we 181 * have more than one gfx pipe. 182 */ 183 if (amdgpu_gfx_is_graphics_multipipe_capable(adev) && 184 adev->gfx.num_gfx_rings > 1 && pipe == 1 && queue == 0) { 185 int me = ring->me; 186 int bit; 187 188 bit = amdgpu_gfx_me_queue_to_bit(adev, me, pipe, queue); 189 if (ring == &adev->gfx.gfx_ring[bit]) 190 return true; 191 } 192 193 return false; 194} 195 196bool amdgpu_gfx_is_high_priority_compute_queue(struct amdgpu_device *adev, 197 struct amdgpu_ring *ring) 198{ 199 /* Policy: use 1st queue as high priority compute queue if we 200 * have more than one compute queue. 201 */ 202 if (adev->gfx.num_compute_rings > 1 && 203 ring == &adev->gfx.compute_ring[0]) 204 return true; 205 206 return false; 207} 208 209void amdgpu_gfx_compute_queue_acquire(struct amdgpu_device *adev) 210{ 211 int i, j, queue, pipe; 212 bool multipipe_policy = amdgpu_gfx_is_compute_multipipe_capable(adev); 213 int max_queues_per_mec = min(adev->gfx.mec.num_pipe_per_mec * 214 adev->gfx.mec.num_queue_per_pipe, 215 adev->gfx.num_compute_rings); 216 int num_xcc = adev->gfx.xcc_mask ? NUM_XCC(adev->gfx.xcc_mask) : 1; 217 218 if (multipipe_policy) { 219 /* policy: make queues evenly cross all pipes on MEC1 only 220 * for multiple xcc, just use the original policy for simplicity */ 221 for (j = 0; j < num_xcc; j++) { 222 for (i = 0; i < max_queues_per_mec; i++) { 223 pipe = i % adev->gfx.mec.num_pipe_per_mec; 224 queue = (i / adev->gfx.mec.num_pipe_per_mec) % 225 adev->gfx.mec.num_queue_per_pipe; 226 227 set_bit(pipe * adev->gfx.mec.num_queue_per_pipe + queue, 228 adev->gfx.mec_bitmap[j].queue_bitmap); 229 } 230 } 231 } else { 232 /* policy: amdgpu owns all queues in the given pipe */ 233 for (j = 0; j < num_xcc; j++) { 234 for (i = 0; i < max_queues_per_mec; ++i) 235 set_bit(i, adev->gfx.mec_bitmap[j].queue_bitmap); 236 } 237 } 238 239 for (j = 0; j < num_xcc; j++) { 240 dev_dbg(adev->dev, "mec queue bitmap weight=%d\n", 241 bitmap_weight(adev->gfx.mec_bitmap[j].queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES)); 242 } 243} 244 245void amdgpu_gfx_graphics_queue_acquire(struct amdgpu_device *adev) 246{ 247 int i, queue, pipe; 248 bool multipipe_policy = amdgpu_gfx_is_graphics_multipipe_capable(adev); 249 int max_queues_per_me = adev->gfx.me.num_pipe_per_me * 250 adev->gfx.me.num_queue_per_pipe; 251 252 if (multipipe_policy) { 253 /* policy: amdgpu owns the first queue per pipe at this stage 254 * will extend to mulitple queues per pipe later */ 255 for (i = 0; i < max_queues_per_me; i++) { 256 pipe = i % adev->gfx.me.num_pipe_per_me; 257 queue = (i / adev->gfx.me.num_pipe_per_me) % 258 adev->gfx.me.num_queue_per_pipe; 259 260 set_bit(pipe * adev->gfx.me.num_queue_per_pipe + queue, 261 adev->gfx.me.queue_bitmap); 262 } 263 } else { 264 for (i = 0; i < max_queues_per_me; ++i) 265 set_bit(i, adev->gfx.me.queue_bitmap); 266 } 267 268 /* update the number of active graphics rings */ 269 adev->gfx.num_gfx_rings = 270 bitmap_weight(adev->gfx.me.queue_bitmap, AMDGPU_MAX_GFX_QUEUES); 271} 272 273static int amdgpu_gfx_kiq_acquire(struct amdgpu_device *adev, 274 struct amdgpu_ring *ring, int xcc_id) 275{ 276 int queue_bit; 277 int mec, pipe, queue; 278 279 queue_bit = adev->gfx.mec.num_mec 280 * adev->gfx.mec.num_pipe_per_mec 281 * adev->gfx.mec.num_queue_per_pipe; 282 283 while (--queue_bit >= 0) { 284 if (test_bit(queue_bit, adev->gfx.mec_bitmap[xcc_id].queue_bitmap)) 285 continue; 286 287 amdgpu_queue_mask_bit_to_mec_queue(adev, queue_bit, &mec, &pipe, &queue); 288 289 /* 290 * 1. Using pipes 2/3 from MEC 2 seems cause problems. 291 * 2. It must use queue id 0, because CGPG_IDLE/SAVE/LOAD/RUN 292 * only can be issued on queue 0. 293 */ 294 if ((mec == 1 && pipe > 1) || queue != 0) 295 continue; 296 297 ring->me = mec + 1; 298 ring->pipe = pipe; 299 ring->queue = queue; 300 301 return 0; 302 } 303 304 dev_err(adev->dev, "Failed to find a queue for KIQ\n"); 305 return -EINVAL; 306} 307 308int amdgpu_gfx_kiq_init_ring(struct amdgpu_device *adev, 309 struct amdgpu_ring *ring, 310 struct amdgpu_irq_src *irq, int xcc_id) 311{ 312 struct amdgpu_kiq *kiq = &adev->gfx.kiq[xcc_id]; 313 int r = 0; 314 315 mtx_init(&kiq->ring_lock, IPL_TTY); 316 317 ring->adev = NULL; 318 ring->ring_obj = NULL; 319 ring->use_doorbell = true; 320 ring->xcc_id = xcc_id; 321 ring->vm_hub = AMDGPU_GFXHUB(xcc_id); 322 ring->doorbell_index = 323 (adev->doorbell_index.kiq + 324 xcc_id * adev->doorbell_index.xcc_doorbell_range) 325 << 1; 326 327 r = amdgpu_gfx_kiq_acquire(adev, ring, xcc_id); 328 if (r) 329 return r; 330 331 ring->eop_gpu_addr = kiq->eop_gpu_addr; 332 ring->no_scheduler = true; 333 snprintf(ring->name, sizeof(ring->name), "kiq_%d.%d.%d.%d", xcc_id, ring->me, ring->pipe, ring->queue); 334 r = amdgpu_ring_init(adev, ring, 1024, irq, AMDGPU_CP_KIQ_IRQ_DRIVER0, 335 AMDGPU_RING_PRIO_DEFAULT, NULL); 336 if (r) 337 dev_warn(adev->dev, "(%d) failed to init kiq ring\n", r); 338 339 return r; 340} 341 342void amdgpu_gfx_kiq_free_ring(struct amdgpu_ring *ring) 343{ 344 amdgpu_ring_fini(ring); 345} 346 347void amdgpu_gfx_kiq_fini(struct amdgpu_device *adev, int xcc_id) 348{ 349 struct amdgpu_kiq *kiq = &adev->gfx.kiq[xcc_id]; 350 351 amdgpu_bo_free_kernel(&kiq->eop_obj, &kiq->eop_gpu_addr, NULL); 352} 353 354int amdgpu_gfx_kiq_init(struct amdgpu_device *adev, 355 unsigned int hpd_size, int xcc_id) 356{ 357 int r; 358 u32 *hpd; 359 struct amdgpu_kiq *kiq = &adev->gfx.kiq[xcc_id]; 360 361 r = amdgpu_bo_create_kernel(adev, hpd_size, PAGE_SIZE, 362 AMDGPU_GEM_DOMAIN_GTT, &kiq->eop_obj, 363 &kiq->eop_gpu_addr, (void **)&hpd); 364 if (r) { 365 dev_warn(adev->dev, "failed to create KIQ bo (%d).\n", r); 366 return r; 367 } 368 369 memset(hpd, 0, hpd_size); 370 371 r = amdgpu_bo_reserve(kiq->eop_obj, true); 372 if (unlikely(r != 0)) 373 dev_warn(adev->dev, "(%d) reserve kiq eop bo failed\n", r); 374 amdgpu_bo_kunmap(kiq->eop_obj); 375 amdgpu_bo_unreserve(kiq->eop_obj); 376 377 return 0; 378} 379 380/* create MQD for each compute/gfx queue */ 381int amdgpu_gfx_mqd_sw_init(struct amdgpu_device *adev, 382 unsigned int mqd_size, int xcc_id) 383{ 384 int r, i, j; 385 struct amdgpu_kiq *kiq = &adev->gfx.kiq[xcc_id]; 386 struct amdgpu_ring *ring = &kiq->ring; 387 u32 domain = AMDGPU_GEM_DOMAIN_GTT; 388 389#if !defined(CONFIG_ARM) && !defined(CONFIG_ARM64) 390 /* Only enable on gfx10 and 11 for now to avoid changing behavior on older chips */ 391 if (adev->ip_versions[GC_HWIP][0] >= IP_VERSION(10, 0, 0)) 392 domain |= AMDGPU_GEM_DOMAIN_VRAM; 393#endif 394 395 /* create MQD for KIQ */ 396 if (!adev->enable_mes_kiq && !ring->mqd_obj) { 397 /* originaly the KIQ MQD is put in GTT domain, but for SRIOV VRAM domain is a must 398 * otherwise hypervisor trigger SAVE_VF fail after driver unloaded which mean MQD 399 * deallocated and gart_unbind, to strict diverage we decide to use VRAM domain for 400 * KIQ MQD no matter SRIOV or Bare-metal 401 */ 402 r = amdgpu_bo_create_kernel(adev, mqd_size, PAGE_SIZE, 403 AMDGPU_GEM_DOMAIN_VRAM | 404 AMDGPU_GEM_DOMAIN_GTT, 405 &ring->mqd_obj, 406 &ring->mqd_gpu_addr, 407 &ring->mqd_ptr); 408 if (r) { 409 dev_warn(adev->dev, "failed to create ring mqd ob (%d)", r); 410 return r; 411 } 412 413 /* prepare MQD backup */ 414 kiq->mqd_backup = kmalloc(mqd_size, GFP_KERNEL); 415 if (!kiq->mqd_backup) { 416 dev_warn(adev->dev, 417 "no memory to create MQD backup for ring %s\n", ring->name); 418 return -ENOMEM; 419 } 420 } 421 422 if (adev->asic_type >= CHIP_NAVI10 && amdgpu_async_gfx_ring) { 423 /* create MQD for each KGQ */ 424 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 425 ring = &adev->gfx.gfx_ring[i]; 426 if (!ring->mqd_obj) { 427 r = amdgpu_bo_create_kernel(adev, mqd_size, PAGE_SIZE, 428 domain, &ring->mqd_obj, 429 &ring->mqd_gpu_addr, &ring->mqd_ptr); 430 if (r) { 431 dev_warn(adev->dev, "failed to create ring mqd bo (%d)", r); 432 return r; 433 } 434 435 ring->mqd_size = mqd_size; 436 /* prepare MQD backup */ 437 adev->gfx.me.mqd_backup[i] = kmalloc(mqd_size, GFP_KERNEL); 438 if (!adev->gfx.me.mqd_backup[i]) { 439 dev_warn(adev->dev, "no memory to create MQD backup for ring %s\n", ring->name); 440 return -ENOMEM; 441 } 442 } 443 } 444 } 445 446 /* create MQD for each KCQ */ 447 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 448 j = i + xcc_id * adev->gfx.num_compute_rings; 449 ring = &adev->gfx.compute_ring[j]; 450 if (!ring->mqd_obj) { 451 r = amdgpu_bo_create_kernel(adev, mqd_size, PAGE_SIZE, 452 domain, &ring->mqd_obj, 453 &ring->mqd_gpu_addr, &ring->mqd_ptr); 454 if (r) { 455 dev_warn(adev->dev, "failed to create ring mqd bo (%d)", r); 456 return r; 457 } 458 459 ring->mqd_size = mqd_size; 460 /* prepare MQD backup */ 461 adev->gfx.mec.mqd_backup[j] = kmalloc(mqd_size, GFP_KERNEL); 462 if (!adev->gfx.mec.mqd_backup[j]) { 463 dev_warn(adev->dev, "no memory to create MQD backup for ring %s\n", ring->name); 464 return -ENOMEM; 465 } 466 } 467 } 468 469 return 0; 470} 471 472void amdgpu_gfx_mqd_sw_fini(struct amdgpu_device *adev, int xcc_id) 473{ 474 struct amdgpu_ring *ring = NULL; 475 int i, j; 476 struct amdgpu_kiq *kiq = &adev->gfx.kiq[xcc_id]; 477 478 if (adev->asic_type >= CHIP_NAVI10 && amdgpu_async_gfx_ring) { 479 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 480 ring = &adev->gfx.gfx_ring[i]; 481 kfree(adev->gfx.me.mqd_backup[i]); 482 amdgpu_bo_free_kernel(&ring->mqd_obj, 483 &ring->mqd_gpu_addr, 484 &ring->mqd_ptr); 485 } 486 } 487 488 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 489 j = i + xcc_id * adev->gfx.num_compute_rings; 490 ring = &adev->gfx.compute_ring[j]; 491 kfree(adev->gfx.mec.mqd_backup[j]); 492 amdgpu_bo_free_kernel(&ring->mqd_obj, 493 &ring->mqd_gpu_addr, 494 &ring->mqd_ptr); 495 } 496 497 ring = &kiq->ring; 498 kfree(kiq->mqd_backup); 499 amdgpu_bo_free_kernel(&ring->mqd_obj, 500 &ring->mqd_gpu_addr, 501 &ring->mqd_ptr); 502} 503 504int amdgpu_gfx_disable_kcq(struct amdgpu_device *adev, int xcc_id) 505{ 506 struct amdgpu_kiq *kiq = &adev->gfx.kiq[xcc_id]; 507 struct amdgpu_ring *kiq_ring = &kiq->ring; 508 int i, r = 0; 509 int j; 510 511 if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues) 512 return -EINVAL; 513 514 spin_lock(&kiq->ring_lock); 515 if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size * 516 adev->gfx.num_compute_rings)) { 517 spin_unlock(&kiq->ring_lock); 518 return -ENOMEM; 519 } 520 521 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 522 j = i + xcc_id * adev->gfx.num_compute_rings; 523 kiq->pmf->kiq_unmap_queues(kiq_ring, 524 &adev->gfx.compute_ring[j], 525 RESET_QUEUES, 0, 0); 526 } 527 528 if (kiq_ring->sched.ready && !adev->job_hang) 529 r = amdgpu_ring_test_helper(kiq_ring); 530 spin_unlock(&kiq->ring_lock); 531 532 return r; 533} 534 535int amdgpu_gfx_disable_kgq(struct amdgpu_device *adev, int xcc_id) 536{ 537 struct amdgpu_kiq *kiq = &adev->gfx.kiq[xcc_id]; 538 struct amdgpu_ring *kiq_ring = &kiq->ring; 539 int i, r = 0; 540 int j; 541 542 if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues) 543 return -EINVAL; 544 545 spin_lock(&kiq->ring_lock); 546 if (amdgpu_gfx_is_master_xcc(adev, xcc_id)) { 547 if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size * 548 adev->gfx.num_gfx_rings)) { 549 spin_unlock(&kiq->ring_lock); 550 return -ENOMEM; 551 } 552 553 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 554 j = i + xcc_id * adev->gfx.num_gfx_rings; 555 kiq->pmf->kiq_unmap_queues(kiq_ring, 556 &adev->gfx.gfx_ring[j], 557 PREEMPT_QUEUES, 0, 0); 558 } 559 } 560 561 if (adev->gfx.kiq[0].ring.sched.ready && !adev->job_hang) 562 r = amdgpu_ring_test_helper(kiq_ring); 563 spin_unlock(&kiq->ring_lock); 564 565 return r; 566} 567 568int amdgpu_queue_mask_bit_to_set_resource_bit(struct amdgpu_device *adev, 569 int queue_bit) 570{ 571 int mec, pipe, queue; 572 int set_resource_bit = 0; 573 574 amdgpu_queue_mask_bit_to_mec_queue(adev, queue_bit, &mec, &pipe, &queue); 575 576 set_resource_bit = mec * 4 * 8 + pipe * 8 + queue; 577 578 return set_resource_bit; 579} 580 581int amdgpu_gfx_enable_kcq(struct amdgpu_device *adev, int xcc_id) 582{ 583 struct amdgpu_kiq *kiq = &adev->gfx.kiq[xcc_id]; 584 struct amdgpu_ring *kiq_ring = &kiq->ring; 585 uint64_t queue_mask = 0; 586 int r, i, j; 587 588 if (!kiq->pmf || !kiq->pmf->kiq_map_queues || !kiq->pmf->kiq_set_resources) 589 return -EINVAL; 590 591 for (i = 0; i < AMDGPU_MAX_COMPUTE_QUEUES; ++i) { 592 if (!test_bit(i, adev->gfx.mec_bitmap[xcc_id].queue_bitmap)) 593 continue; 594 595 /* This situation may be hit in the future if a new HW 596 * generation exposes more than 64 queues. If so, the 597 * definition of queue_mask needs updating */ 598 if (WARN_ON(i > (sizeof(queue_mask)*8))) { 599 DRM_ERROR("Invalid KCQ enabled: %d\n", i); 600 break; 601 } 602 603 queue_mask |= (1ull << amdgpu_queue_mask_bit_to_set_resource_bit(adev, i)); 604 } 605 606 DRM_INFO("kiq ring mec %d pipe %d q %d\n", kiq_ring->me, kiq_ring->pipe, 607 kiq_ring->queue); 608 amdgpu_device_flush_hdp(adev, NULL); 609 610 spin_lock(&kiq->ring_lock); 611 r = amdgpu_ring_alloc(kiq_ring, kiq->pmf->map_queues_size * 612 adev->gfx.num_compute_rings + 613 kiq->pmf->set_resources_size); 614 if (r) { 615 DRM_ERROR("Failed to lock KIQ (%d).\n", r); 616 spin_unlock(&kiq->ring_lock); 617 return r; 618 } 619 620 if (adev->enable_mes) 621 queue_mask = ~0ULL; 622 623 kiq->pmf->kiq_set_resources(kiq_ring, queue_mask); 624 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 625 j = i + xcc_id * adev->gfx.num_compute_rings; 626 kiq->pmf->kiq_map_queues(kiq_ring, 627 &adev->gfx.compute_ring[j]); 628 } 629 630 r = amdgpu_ring_test_helper(kiq_ring); 631 spin_unlock(&kiq->ring_lock); 632 if (r) 633 DRM_ERROR("KCQ enable failed\n"); 634 635 return r; 636} 637 638int amdgpu_gfx_enable_kgq(struct amdgpu_device *adev, int xcc_id) 639{ 640 struct amdgpu_kiq *kiq = &adev->gfx.kiq[xcc_id]; 641 struct amdgpu_ring *kiq_ring = &kiq->ring; 642 int r, i, j; 643 644 if (!kiq->pmf || !kiq->pmf->kiq_map_queues) 645 return -EINVAL; 646 647 amdgpu_device_flush_hdp(adev, NULL); 648 649 spin_lock(&kiq->ring_lock); 650 /* No need to map kcq on the slave */ 651 if (amdgpu_gfx_is_master_xcc(adev, xcc_id)) { 652 r = amdgpu_ring_alloc(kiq_ring, kiq->pmf->map_queues_size * 653 adev->gfx.num_gfx_rings); 654 if (r) { 655 DRM_ERROR("Failed to lock KIQ (%d).\n", r); 656 spin_unlock(&kiq->ring_lock); 657 return r; 658 } 659 660 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 661 j = i + xcc_id * adev->gfx.num_gfx_rings; 662 kiq->pmf->kiq_map_queues(kiq_ring, 663 &adev->gfx.gfx_ring[j]); 664 } 665 } 666 667 r = amdgpu_ring_test_helper(kiq_ring); 668 spin_unlock(&kiq->ring_lock); 669 if (r) 670 DRM_ERROR("KCQ enable failed\n"); 671 672 return r; 673} 674 675/* amdgpu_gfx_off_ctrl - Handle gfx off feature enable/disable 676 * 677 * @adev: amdgpu_device pointer 678 * @bool enable true: enable gfx off feature, false: disable gfx off feature 679 * 680 * 1. gfx off feature will be enabled by gfx ip after gfx cg gp enabled. 681 * 2. other client can send request to disable gfx off feature, the request should be honored. 682 * 3. other client can cancel their request of disable gfx off feature 683 * 4. other client should not send request to enable gfx off feature before disable gfx off feature. 684 */ 685 686void amdgpu_gfx_off_ctrl(struct amdgpu_device *adev, bool enable) 687{ 688 unsigned long delay = GFX_OFF_DELAY_ENABLE; 689 690 if (!(adev->pm.pp_feature & PP_GFXOFF_MASK)) 691 return; 692 693 mutex_lock(&adev->gfx.gfx_off_mutex); 694 695 if (enable) { 696 /* If the count is already 0, it means there's an imbalance bug somewhere. 697 * Note that the bug may be in a different caller than the one which triggers the 698 * WARN_ON_ONCE. 699 */ 700 if (WARN_ON_ONCE(adev->gfx.gfx_off_req_count == 0)) 701 goto unlock; 702 703 adev->gfx.gfx_off_req_count--; 704 705 if (adev->gfx.gfx_off_req_count == 0 && 706 !adev->gfx.gfx_off_state) { 707 /* If going to s2idle, no need to wait */ 708 if (adev->in_s0ix) { 709 if (!amdgpu_dpm_set_powergating_by_smu(adev, 710 AMD_IP_BLOCK_TYPE_GFX, true)) 711 adev->gfx.gfx_off_state = true; 712 } else { 713 schedule_delayed_work(&adev->gfx.gfx_off_delay_work, 714 delay); 715 } 716 } 717 } else { 718 if (adev->gfx.gfx_off_req_count == 0) { 719 cancel_delayed_work_sync(&adev->gfx.gfx_off_delay_work); 720 721 if (adev->gfx.gfx_off_state && 722 !amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_GFX, false)) { 723 adev->gfx.gfx_off_state = false; 724 725 if (adev->gfx.funcs->init_spm_golden) { 726 dev_dbg(adev->dev, 727 "GFXOFF is disabled, re-init SPM golden settings\n"); 728 amdgpu_gfx_init_spm_golden(adev); 729 } 730 } 731 } 732 733 adev->gfx.gfx_off_req_count++; 734 } 735 736unlock: 737 mutex_unlock(&adev->gfx.gfx_off_mutex); 738} 739 740int amdgpu_set_gfx_off_residency(struct amdgpu_device *adev, bool value) 741{ 742 int r = 0; 743 744 mutex_lock(&adev->gfx.gfx_off_mutex); 745 746 r = amdgpu_dpm_set_residency_gfxoff(adev, value); 747 748 mutex_unlock(&adev->gfx.gfx_off_mutex); 749 750 return r; 751} 752 753int amdgpu_get_gfx_off_residency(struct amdgpu_device *adev, u32 *value) 754{ 755 int r = 0; 756 757 mutex_lock(&adev->gfx.gfx_off_mutex); 758 759 r = amdgpu_dpm_get_residency_gfxoff(adev, value); 760 761 mutex_unlock(&adev->gfx.gfx_off_mutex); 762 763 return r; 764} 765 766int amdgpu_get_gfx_off_entrycount(struct amdgpu_device *adev, u64 *value) 767{ 768 int r = 0; 769 770 mutex_lock(&adev->gfx.gfx_off_mutex); 771 772 r = amdgpu_dpm_get_entrycount_gfxoff(adev, value); 773 774 mutex_unlock(&adev->gfx.gfx_off_mutex); 775 776 return r; 777} 778 779int amdgpu_get_gfx_off_status(struct amdgpu_device *adev, uint32_t *value) 780{ 781 782 int r = 0; 783 784 mutex_lock(&adev->gfx.gfx_off_mutex); 785 786 r = amdgpu_dpm_get_status_gfxoff(adev, value); 787 788 mutex_unlock(&adev->gfx.gfx_off_mutex); 789 790 return r; 791} 792 793int amdgpu_gfx_ras_late_init(struct amdgpu_device *adev, struct ras_common_if *ras_block) 794{ 795 int r; 796 797 if (amdgpu_ras_is_supported(adev, ras_block->block)) { 798 if (!amdgpu_persistent_edc_harvesting_supported(adev)) 799 amdgpu_ras_reset_error_status(adev, AMDGPU_RAS_BLOCK__GFX); 800 801 r = amdgpu_ras_block_late_init(adev, ras_block); 802 if (r) 803 return r; 804 805 if (adev->gfx.cp_ecc_error_irq.funcs) { 806 r = amdgpu_irq_get(adev, &adev->gfx.cp_ecc_error_irq, 0); 807 if (r) 808 goto late_fini; 809 } 810 } else { 811 amdgpu_ras_feature_enable_on_boot(adev, ras_block, 0); 812 } 813 814 return 0; 815late_fini: 816 amdgpu_ras_block_late_fini(adev, ras_block); 817 return r; 818} 819 820int amdgpu_gfx_ras_sw_init(struct amdgpu_device *adev) 821{ 822 int err = 0; 823 struct amdgpu_gfx_ras *ras = NULL; 824 825 /* adev->gfx.ras is NULL, which means gfx does not 826 * support ras function, then do nothing here. 827 */ 828 if (!adev->gfx.ras) 829 return 0; 830 831 ras = adev->gfx.ras; 832 833 err = amdgpu_ras_register_ras_block(adev, &ras->ras_block); 834 if (err) { 835 dev_err(adev->dev, "Failed to register gfx ras block!\n"); 836 return err; 837 } 838 839 strlcpy(ras->ras_block.ras_comm.name, "gfx", 840 sizeof(ras->ras_block.ras_comm.name)); 841 ras->ras_block.ras_comm.block = AMDGPU_RAS_BLOCK__GFX; 842 ras->ras_block.ras_comm.type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE; 843 adev->gfx.ras_if = &ras->ras_block.ras_comm; 844 845 /* If not define special ras_late_init function, use gfx default ras_late_init */ 846 if (!ras->ras_block.ras_late_init) 847 ras->ras_block.ras_late_init = amdgpu_gfx_ras_late_init; 848 849 /* If not defined special ras_cb function, use default ras_cb */ 850 if (!ras->ras_block.ras_cb) 851 ras->ras_block.ras_cb = amdgpu_gfx_process_ras_data_cb; 852 853 return 0; 854} 855 856int amdgpu_gfx_poison_consumption_handler(struct amdgpu_device *adev, 857 struct amdgpu_iv_entry *entry) 858{ 859 if (adev->gfx.ras && adev->gfx.ras->poison_consumption_handler) 860 return adev->gfx.ras->poison_consumption_handler(adev, entry); 861 862 return 0; 863} 864 865int amdgpu_gfx_process_ras_data_cb(struct amdgpu_device *adev, 866 void *err_data, 867 struct amdgpu_iv_entry *entry) 868{ 869 /* TODO ue will trigger an interrupt. 870 * 871 * When ���Full RAS��� is enabled, the per-IP interrupt sources should 872 * be disabled and the driver should only look for the aggregated 873 * interrupt via sync flood 874 */ 875 if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__GFX)) { 876 kgd2kfd_set_sram_ecc_flag(adev->kfd.dev); 877 if (adev->gfx.ras && adev->gfx.ras->ras_block.hw_ops && 878 adev->gfx.ras->ras_block.hw_ops->query_ras_error_count) 879 adev->gfx.ras->ras_block.hw_ops->query_ras_error_count(adev, err_data); 880 amdgpu_ras_reset_gpu(adev); 881 } 882 return AMDGPU_RAS_SUCCESS; 883} 884 885int amdgpu_gfx_cp_ecc_error_irq(struct amdgpu_device *adev, 886 struct amdgpu_irq_src *source, 887 struct amdgpu_iv_entry *entry) 888{ 889 struct ras_common_if *ras_if = adev->gfx.ras_if; 890 struct ras_dispatch_if ih_data = { 891 .entry = entry, 892 }; 893 894 if (!ras_if) 895 return 0; 896 897 ih_data.head = *ras_if; 898 899 DRM_ERROR("CP ECC ERROR IRQ\n"); 900 amdgpu_ras_interrupt_dispatch(adev, &ih_data); 901 return 0; 902} 903 904void amdgpu_gfx_ras_error_func(struct amdgpu_device *adev, 905 void *ras_error_status, 906 void (*func)(struct amdgpu_device *adev, void *ras_error_status, 907 int xcc_id)) 908{ 909 int i; 910 int num_xcc = adev->gfx.xcc_mask ? NUM_XCC(adev->gfx.xcc_mask) : 1; 911 uint32_t xcc_mask = GENMASK(num_xcc - 1, 0); 912 struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status; 913 914 if (err_data) { 915 err_data->ue_count = 0; 916 err_data->ce_count = 0; 917 } 918 919 for_each_inst(i, xcc_mask) 920 func(adev, ras_error_status, i); 921} 922 923uint32_t amdgpu_kiq_rreg(struct amdgpu_device *adev, uint32_t reg) 924{ 925 signed long r, cnt = 0; 926 unsigned long flags; 927 uint32_t seq, reg_val_offs = 0, value = 0; 928 struct amdgpu_kiq *kiq = &adev->gfx.kiq[0]; 929 struct amdgpu_ring *ring = &kiq->ring; 930 931 if (amdgpu_device_skip_hw_access(adev)) 932 return 0; 933 934 if (adev->mes.ring.sched.ready) 935 return amdgpu_mes_rreg(adev, reg); 936 937 BUG_ON(!ring->funcs->emit_rreg); 938 939 spin_lock_irqsave(&kiq->ring_lock, flags); 940 if (amdgpu_device_wb_get(adev, ®_val_offs)) { 941 pr_err("critical bug! too many kiq readers\n"); 942 goto failed_unlock; 943 } 944 amdgpu_ring_alloc(ring, 32); 945 amdgpu_ring_emit_rreg(ring, reg, reg_val_offs); 946 r = amdgpu_fence_emit_polling(ring, &seq, MAX_KIQ_REG_WAIT); 947 if (r) 948 goto failed_undo; 949 950 amdgpu_ring_commit(ring); 951 spin_unlock_irqrestore(&kiq->ring_lock, flags); 952 953 r = amdgpu_fence_wait_polling(ring, seq, MAX_KIQ_REG_WAIT); 954 955 /* don't wait anymore for gpu reset case because this way may 956 * block gpu_recover() routine forever, e.g. this virt_kiq_rreg 957 * is triggered in TTM and ttm_bo_lock_delayed_workqueue() will 958 * never return if we keep waiting in virt_kiq_rreg, which cause 959 * gpu_recover() hang there. 960 * 961 * also don't wait anymore for IRQ context 962 * */ 963 if (r < 1 && (amdgpu_in_reset(adev) || in_interrupt())) 964 goto failed_kiq_read; 965 966 might_sleep(); 967 while (r < 1 && cnt++ < MAX_KIQ_REG_TRY) { 968 drm_msleep(MAX_KIQ_REG_BAILOUT_INTERVAL); 969 r = amdgpu_fence_wait_polling(ring, seq, MAX_KIQ_REG_WAIT); 970 } 971 972 if (cnt > MAX_KIQ_REG_TRY) 973 goto failed_kiq_read; 974 975 mb(); 976 value = adev->wb.wb[reg_val_offs]; 977 amdgpu_device_wb_free(adev, reg_val_offs); 978 return value; 979 980failed_undo: 981 amdgpu_ring_undo(ring); 982failed_unlock: 983 spin_unlock_irqrestore(&kiq->ring_lock, flags); 984failed_kiq_read: 985 if (reg_val_offs) 986 amdgpu_device_wb_free(adev, reg_val_offs); 987 dev_err(adev->dev, "failed to read reg:%x\n", reg); 988 return ~0; 989} 990 991void amdgpu_kiq_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v) 992{ 993 signed long r, cnt = 0; 994 unsigned long flags; 995 uint32_t seq; 996 struct amdgpu_kiq *kiq = &adev->gfx.kiq[0]; 997 struct amdgpu_ring *ring = &kiq->ring; 998 999 BUG_ON(!ring->funcs->emit_wreg); 1000 1001 if (amdgpu_device_skip_hw_access(adev)) 1002 return; 1003 1004 if (adev->mes.ring.sched.ready) { 1005 amdgpu_mes_wreg(adev, reg, v); 1006 return; 1007 } 1008 1009 spin_lock_irqsave(&kiq->ring_lock, flags); 1010 amdgpu_ring_alloc(ring, 32); 1011 amdgpu_ring_emit_wreg(ring, reg, v); 1012 r = amdgpu_fence_emit_polling(ring, &seq, MAX_KIQ_REG_WAIT); 1013 if (r) 1014 goto failed_undo; 1015 1016 amdgpu_ring_commit(ring); 1017 spin_unlock_irqrestore(&kiq->ring_lock, flags); 1018 1019 r = amdgpu_fence_wait_polling(ring, seq, MAX_KIQ_REG_WAIT); 1020 1021 /* don't wait anymore for gpu reset case because this way may 1022 * block gpu_recover() routine forever, e.g. this virt_kiq_rreg 1023 * is triggered in TTM and ttm_bo_lock_delayed_workqueue() will 1024 * never return if we keep waiting in virt_kiq_rreg, which cause 1025 * gpu_recover() hang there. 1026 * 1027 * also don't wait anymore for IRQ context 1028 * */ 1029 if (r < 1 && (amdgpu_in_reset(adev) || in_interrupt())) 1030 goto failed_kiq_write; 1031 1032 might_sleep(); 1033 while (r < 1 && cnt++ < MAX_KIQ_REG_TRY) { 1034 1035 drm_msleep(MAX_KIQ_REG_BAILOUT_INTERVAL); 1036 r = amdgpu_fence_wait_polling(ring, seq, MAX_KIQ_REG_WAIT); 1037 } 1038 1039 if (cnt > MAX_KIQ_REG_TRY) 1040 goto failed_kiq_write; 1041 1042 return; 1043 1044failed_undo: 1045 amdgpu_ring_undo(ring); 1046 spin_unlock_irqrestore(&kiq->ring_lock, flags); 1047failed_kiq_write: 1048 dev_err(adev->dev, "failed to write reg:%x\n", reg); 1049} 1050 1051int amdgpu_gfx_get_num_kcq(struct amdgpu_device *adev) 1052{ 1053 if (amdgpu_num_kcq == -1) { 1054 return 8; 1055 } else if (amdgpu_num_kcq > 8 || amdgpu_num_kcq < 0) { 1056 dev_warn(adev->dev, "set kernel compute queue number to 8 due to invalid parameter provided by user\n"); 1057 return 8; 1058 } 1059 return amdgpu_num_kcq; 1060} 1061 1062void amdgpu_gfx_cp_init_microcode(struct amdgpu_device *adev, 1063 uint32_t ucode_id) 1064{ 1065 const struct gfx_firmware_header_v1_0 *cp_hdr; 1066 const struct gfx_firmware_header_v2_0 *cp_hdr_v2_0; 1067 struct amdgpu_firmware_info *info = NULL; 1068 const struct firmware *ucode_fw; 1069 unsigned int fw_size; 1070 1071 switch (ucode_id) { 1072 case AMDGPU_UCODE_ID_CP_PFP: 1073 cp_hdr = (const struct gfx_firmware_header_v1_0 *) 1074 adev->gfx.pfp_fw->data; 1075 adev->gfx.pfp_fw_version = 1076 le32_to_cpu(cp_hdr->header.ucode_version); 1077 adev->gfx.pfp_feature_version = 1078 le32_to_cpu(cp_hdr->ucode_feature_version); 1079 ucode_fw = adev->gfx.pfp_fw; 1080 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes); 1081 break; 1082 case AMDGPU_UCODE_ID_CP_RS64_PFP: 1083 cp_hdr_v2_0 = (const struct gfx_firmware_header_v2_0 *) 1084 adev->gfx.pfp_fw->data; 1085 adev->gfx.pfp_fw_version = 1086 le32_to_cpu(cp_hdr_v2_0->header.ucode_version); 1087 adev->gfx.pfp_feature_version = 1088 le32_to_cpu(cp_hdr_v2_0->ucode_feature_version); 1089 ucode_fw = adev->gfx.pfp_fw; 1090 fw_size = le32_to_cpu(cp_hdr_v2_0->ucode_size_bytes); 1091 break; 1092 case AMDGPU_UCODE_ID_CP_RS64_PFP_P0_STACK: 1093 case AMDGPU_UCODE_ID_CP_RS64_PFP_P1_STACK: 1094 cp_hdr_v2_0 = (const struct gfx_firmware_header_v2_0 *) 1095 adev->gfx.pfp_fw->data; 1096 ucode_fw = adev->gfx.pfp_fw; 1097 fw_size = le32_to_cpu(cp_hdr_v2_0->data_size_bytes); 1098 break; 1099 case AMDGPU_UCODE_ID_CP_ME: 1100 cp_hdr = (const struct gfx_firmware_header_v1_0 *) 1101 adev->gfx.me_fw->data; 1102 adev->gfx.me_fw_version = 1103 le32_to_cpu(cp_hdr->header.ucode_version); 1104 adev->gfx.me_feature_version = 1105 le32_to_cpu(cp_hdr->ucode_feature_version); 1106 ucode_fw = adev->gfx.me_fw; 1107 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes); 1108 break; 1109 case AMDGPU_UCODE_ID_CP_RS64_ME: 1110 cp_hdr_v2_0 = (const struct gfx_firmware_header_v2_0 *) 1111 adev->gfx.me_fw->data; 1112 adev->gfx.me_fw_version = 1113 le32_to_cpu(cp_hdr_v2_0->header.ucode_version); 1114 adev->gfx.me_feature_version = 1115 le32_to_cpu(cp_hdr_v2_0->ucode_feature_version); 1116 ucode_fw = adev->gfx.me_fw; 1117 fw_size = le32_to_cpu(cp_hdr_v2_0->ucode_size_bytes); 1118 break; 1119 case AMDGPU_UCODE_ID_CP_RS64_ME_P0_STACK: 1120 case AMDGPU_UCODE_ID_CP_RS64_ME_P1_STACK: 1121 cp_hdr_v2_0 = (const struct gfx_firmware_header_v2_0 *) 1122 adev->gfx.me_fw->data; 1123 ucode_fw = adev->gfx.me_fw; 1124 fw_size = le32_to_cpu(cp_hdr_v2_0->data_size_bytes); 1125 break; 1126 case AMDGPU_UCODE_ID_CP_CE: 1127 cp_hdr = (const struct gfx_firmware_header_v1_0 *) 1128 adev->gfx.ce_fw->data; 1129 adev->gfx.ce_fw_version = 1130 le32_to_cpu(cp_hdr->header.ucode_version); 1131 adev->gfx.ce_feature_version = 1132 le32_to_cpu(cp_hdr->ucode_feature_version); 1133 ucode_fw = adev->gfx.ce_fw; 1134 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes); 1135 break; 1136 case AMDGPU_UCODE_ID_CP_MEC1: 1137 cp_hdr = (const struct gfx_firmware_header_v1_0 *) 1138 adev->gfx.mec_fw->data; 1139 adev->gfx.mec_fw_version = 1140 le32_to_cpu(cp_hdr->header.ucode_version); 1141 adev->gfx.mec_feature_version = 1142 le32_to_cpu(cp_hdr->ucode_feature_version); 1143 ucode_fw = adev->gfx.mec_fw; 1144 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes) - 1145 le32_to_cpu(cp_hdr->jt_size) * 4; 1146 break; 1147 case AMDGPU_UCODE_ID_CP_MEC1_JT: 1148 cp_hdr = (const struct gfx_firmware_header_v1_0 *) 1149 adev->gfx.mec_fw->data; 1150 ucode_fw = adev->gfx.mec_fw; 1151 fw_size = le32_to_cpu(cp_hdr->jt_size) * 4; 1152 break; 1153 case AMDGPU_UCODE_ID_CP_MEC2: 1154 cp_hdr = (const struct gfx_firmware_header_v1_0 *) 1155 adev->gfx.mec2_fw->data; 1156 adev->gfx.mec2_fw_version = 1157 le32_to_cpu(cp_hdr->header.ucode_version); 1158 adev->gfx.mec2_feature_version = 1159 le32_to_cpu(cp_hdr->ucode_feature_version); 1160 ucode_fw = adev->gfx.mec2_fw; 1161 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes) - 1162 le32_to_cpu(cp_hdr->jt_size) * 4; 1163 break; 1164 case AMDGPU_UCODE_ID_CP_MEC2_JT: 1165 cp_hdr = (const struct gfx_firmware_header_v1_0 *) 1166 adev->gfx.mec2_fw->data; 1167 ucode_fw = adev->gfx.mec2_fw; 1168 fw_size = le32_to_cpu(cp_hdr->jt_size) * 4; 1169 break; 1170 case AMDGPU_UCODE_ID_CP_RS64_MEC: 1171 cp_hdr_v2_0 = (const struct gfx_firmware_header_v2_0 *) 1172 adev->gfx.mec_fw->data; 1173 adev->gfx.mec_fw_version = 1174 le32_to_cpu(cp_hdr_v2_0->header.ucode_version); 1175 adev->gfx.mec_feature_version = 1176 le32_to_cpu(cp_hdr_v2_0->ucode_feature_version); 1177 ucode_fw = adev->gfx.mec_fw; 1178 fw_size = le32_to_cpu(cp_hdr_v2_0->ucode_size_bytes); 1179 break; 1180 case AMDGPU_UCODE_ID_CP_RS64_MEC_P0_STACK: 1181 case AMDGPU_UCODE_ID_CP_RS64_MEC_P1_STACK: 1182 case AMDGPU_UCODE_ID_CP_RS64_MEC_P2_STACK: 1183 case AMDGPU_UCODE_ID_CP_RS64_MEC_P3_STACK: 1184 cp_hdr_v2_0 = (const struct gfx_firmware_header_v2_0 *) 1185 adev->gfx.mec_fw->data; 1186 ucode_fw = adev->gfx.mec_fw; 1187 fw_size = le32_to_cpu(cp_hdr_v2_0->data_size_bytes); 1188 break; 1189 default: 1190 break; 1191 } 1192 1193 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 1194 info = &adev->firmware.ucode[ucode_id]; 1195 info->ucode_id = ucode_id; 1196 info->fw = ucode_fw; 1197 adev->firmware.fw_size += ALIGN(fw_size, PAGE_SIZE); 1198 } 1199} 1200 1201bool amdgpu_gfx_is_master_xcc(struct amdgpu_device *adev, int xcc_id) 1202{ 1203 return !(xcc_id % (adev->gfx.num_xcc_per_xcp ? 1204 adev->gfx.num_xcc_per_xcp : 1)); 1205} 1206 1207static ssize_t amdgpu_gfx_get_current_compute_partition(struct device *dev, 1208 struct device_attribute *addr, 1209 char *buf) 1210{ 1211 struct drm_device *ddev = dev_get_drvdata(dev); 1212 struct amdgpu_device *adev = drm_to_adev(ddev); 1213 int mode; 1214 1215 mode = amdgpu_xcp_query_partition_mode(adev->xcp_mgr, 1216 AMDGPU_XCP_FL_NONE); 1217 1218 return sysfs_emit(buf, "%s\n", amdgpu_gfx_compute_mode_desc(mode)); 1219} 1220 1221static ssize_t amdgpu_gfx_set_compute_partition(struct device *dev, 1222 struct device_attribute *addr, 1223 const char *buf, size_t count) 1224{ 1225 struct drm_device *ddev = dev_get_drvdata(dev); 1226 struct amdgpu_device *adev = drm_to_adev(ddev); 1227 enum amdgpu_gfx_partition mode; 1228 int ret = 0, num_xcc; 1229 1230 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1231 if (num_xcc % 2 != 0) 1232 return -EINVAL; 1233 1234 if (!strncasecmp("SPX", buf, strlen("SPX"))) { 1235 mode = AMDGPU_SPX_PARTITION_MODE; 1236 } else if (!strncasecmp("DPX", buf, strlen("DPX"))) { 1237 /* 1238 * DPX mode needs AIDs to be in multiple of 2. 1239 * Each AID connects 2 XCCs. 1240 */ 1241 if (num_xcc%4) 1242 return -EINVAL; 1243 mode = AMDGPU_DPX_PARTITION_MODE; 1244 } else if (!strncasecmp("TPX", buf, strlen("TPX"))) { 1245 if (num_xcc != 6) 1246 return -EINVAL; 1247 mode = AMDGPU_TPX_PARTITION_MODE; 1248 } else if (!strncasecmp("QPX", buf, strlen("QPX"))) { 1249 if (num_xcc != 8) 1250 return -EINVAL; 1251 mode = AMDGPU_QPX_PARTITION_MODE; 1252 } else if (!strncasecmp("CPX", buf, strlen("CPX"))) { 1253 mode = AMDGPU_CPX_PARTITION_MODE; 1254 } else { 1255 return -EINVAL; 1256 } 1257 1258 ret = amdgpu_xcp_switch_partition_mode(adev->xcp_mgr, mode); 1259 1260 if (ret) 1261 return ret; 1262 1263 return count; 1264} 1265 1266static ssize_t amdgpu_gfx_get_available_compute_partition(struct device *dev, 1267 struct device_attribute *addr, 1268 char *buf) 1269{ 1270 struct drm_device *ddev = dev_get_drvdata(dev); 1271 struct amdgpu_device *adev = drm_to_adev(ddev); 1272 char *supported_partition; 1273 1274 /* TBD */ 1275 switch (NUM_XCC(adev->gfx.xcc_mask)) { 1276 case 8: 1277 supported_partition = "SPX, DPX, QPX, CPX"; 1278 break; 1279 case 6: 1280 supported_partition = "SPX, TPX, CPX"; 1281 break; 1282 case 4: 1283 supported_partition = "SPX, DPX, CPX"; 1284 break; 1285 /* this seems only existing in emulation phase */ 1286 case 2: 1287 supported_partition = "SPX, CPX"; 1288 break; 1289 default: 1290 supported_partition = "Not supported"; 1291 break; 1292 } 1293 1294 return sysfs_emit(buf, "%s\n", supported_partition); 1295} 1296 1297static DEVICE_ATTR(current_compute_partition, 0644, 1298 amdgpu_gfx_get_current_compute_partition, 1299 amdgpu_gfx_set_compute_partition); 1300 1301static DEVICE_ATTR(available_compute_partition, 0444, 1302 amdgpu_gfx_get_available_compute_partition, NULL); 1303 1304int amdgpu_gfx_sysfs_init(struct amdgpu_device *adev) 1305{ 1306 int r; 1307 1308 r = device_create_file(adev->dev, &dev_attr_current_compute_partition); 1309 if (r) 1310 return r; 1311 1312 r = device_create_file(adev->dev, &dev_attr_available_compute_partition); 1313 1314 return r; 1315} 1316 1317void amdgpu_gfx_sysfs_fini(struct amdgpu_device *adev) 1318{ 1319 device_remove_file(adev->dev, &dev_attr_current_compute_partition); 1320 device_remove_file(adev->dev, &dev_attr_available_compute_partition); 1321} 1322