amd/amdgpu/amdgpu_kms.c

225 		fw_info->ver = adev->gfx.me_fw_version;
226 		fw_info->feature = adev->gfx.me_feature_version;
229 		fw_info->ver = adev->gfx.pfp_fw_version;
230 		fw_info->feature = adev->gfx.pfp_feature_version;
233 		fw_info->ver = adev->gfx.ce_fw_version;
234 		fw_info->feature = adev->gfx.ce_feature_version;
237 		fw_info->ver = adev->gfx.rlc_fw_version;
238 		fw_info->feature = adev->gfx.rlc_feature_version;
241 		fw_info->ver = adev->gfx.rlc_srlc_fw_version;
242 		fw_info->feature = adev->gfx.rlc_srlc_feature_version;
245 		fw_info->ver = adev->gfx.rlc_srlg_fw_version;
246 		fw_info->feature = adev->gfx.rlc_srlg_feature_version;
249 		fw_info->ver = adev->gfx.rlc_srls_fw_version;
250 		fw_info->feature = adev->gfx.rlc_srls_feature_version;
253 		fw_info->ver = adev->gfx.rlcp_ucode_version;
254 		fw_info->feature = adev->gfx.rlcp_ucode_feature_version;
257 		fw_info->ver = adev->gfx.rlcv_ucode_version;
258 		fw_info->feature = adev->gfx.rlcv_ucode_feature_version;
262 			fw_info->ver = adev->gfx.mec_fw_version;
263 			fw_info->feature = adev->gfx.mec_feature_version;
265 			fw_info->ver = adev->gfx.mec2_fw_version;
266 			fw_info->feature = adev->gfx.mec2_feature_version;
352 		fw_info->ver = adev->gfx.imu_fw_version;
377 		for (i = 0; i < adev->gfx.num_gfx_rings; i++)
378 			if (adev->gfx.gfx_ring[i].sched.ready)
385 		for (i = 0; i < adev->gfx.num_compute_rings; i++)
386 			if (adev->gfx.compute_ring[i].sched.ready)
786 		dev_info->num_shader_engines = adev->gfx.config.max_shader_engines;
787 		dev_info->num_shader_arrays_per_engine = adev->gfx.config.max_sh_per_se;
803 		dev_info->enabled_rb_pipes_mask = adev->gfx.config.backend_enable_mask;
804 		dev_info->num_rb_pipes = adev->gfx.config.max_backends_per_se *
805 			adev->gfx.config.max_shader_engines;
806 		dev_info->num_hw_gfx_contexts = adev->gfx.config.max_hw_contexts;
810 		if (adev->gfx.mcbp)
814 		if (adev->gfx.config.ta_cntl2_truncate_coord_mode)
836 		dev_info->cu_active_number = adev->gfx.cu_info.number;
837 		dev_info->cu_ao_mask = adev->gfx.cu_info.ao_cu_mask;
838 		dev_info->ce_ram_size = adev->gfx.ce_ram_size;
839 		memcpy(&dev_info->cu_ao_bitmap[0], &adev->gfx.cu_info.ao_cu_bitmap[0],
840 		       sizeof(adev->gfx.cu_info.ao_cu_bitmap));
841 		memcpy(&dev_info->cu_bitmap[0], &adev->gfx.cu_info.bitmap[0],
847 			adev->gfx.config.double_offchip_lds_buf;
848 		dev_info->wave_front_size = adev->gfx.cu_info.wave_front_size;
849 		dev_info->num_shader_visible_vgprs = adev->gfx.config.max_gprs;
850 		dev_info->num_cu_per_sh = adev->gfx.config.max_cu_per_sh;
851 		dev_info->num_tcc_blocks = adev->gfx.config.max_texture_channel_caches;
852 		dev_info->gs_vgt_table_depth = adev->gfx.config.gs_vgt_table_depth;
853 		dev_info->gs_prim_buffer_depth = adev->gfx.config.gs_prim_buffer_depth;
854 		dev_info->max_gs_waves_per_vgt = adev->gfx.config.max_gs_threads;
858 				adev->gfx.config.pa_sc_tile_steering_override;
860 		dev_info->tcc_disabled_mask = adev->gfx.config.tcc_disabled_mask;
873 		dev_info->tcp_cache_size = adev->gfx.config.gc_tcp_l1_size;
874 		dev_info->num_sqc_per_wgp = adev->gfx.config.gc_num_sqc_per_wgp;
875 		dev_info->sqc_data_cache_size = adev->gfx.config.gc_l1_data_cache_size_per_sqc;
876 		dev_info->sqc_inst_cache_size = adev->gfx.config.gc_l1_instruction_cache_size_per_sqc;
877 		dev_info->gl1c_cache_size = adev->gfx.config.gc_gl1c_size_per_instance *
878 					    adev->gfx.config.gc_gl1c_per_sa;
879 		dev_info->gl2c_cache_size = adev->gfx.config.gc_gl2c_per_gpu;
883 		if (adev->gfx.funcs->get_gfx_shadow_info) {
1265 	if (adev->gfx.mcbp) {
1610 	if (adev->gfx.mec2_fw) {