Lines Matching refs:gfx
34 #include "ivsrcid/gfx/irqsrcs_gfx_9_0.h"
187 num_xcc = NUM_XCC(adev->gfx.xcc_mask);
189 adev->gfx.kiq[i].pmf = &gfx_v9_4_3_kiq_pm4_funcs;
196 num_xcc = NUM_XCC(adev->gfx.xcc_mask);
343 mutex_lock(&adev->gfx.gpu_clock_mutex);
347 mutex_unlock(&adev->gfx.gpu_clock_mutex);
354 amdgpu_ucode_release(&adev->gfx.pfp_fw);
355 amdgpu_ucode_release(&adev->gfx.me_fw);
356 amdgpu_ucode_release(&adev->gfx.ce_fw);
357 amdgpu_ucode_release(&adev->gfx.rlc_fw);
358 amdgpu_ucode_release(&adev->gfx.mec_fw);
359 amdgpu_ucode_release(&adev->gfx.mec2_fw);
361 kfree(adev->gfx.rlc.register_list_format);
375 err = amdgpu_ucode_request(adev, &adev->gfx.rlc_fw, fw_name);
378 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
385 amdgpu_ucode_release(&adev->gfx.rlc_fw);
409 err = amdgpu_ucode_request(adev, &adev->gfx.mec_fw, fw_name);
415 adev->gfx.mec2_fw_version = adev->gfx.mec_fw_version;
416 adev->gfx.mec2_feature_version = adev->gfx.mec_feature_version;
422 amdgpu_ucode_release(&adev->gfx.mec_fw);
446 amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL);
447 amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_obj, NULL, NULL);
461 num_xcc = NUM_XCC(adev->gfx.xcc_mask);
463 bitmap_zero(adev->gfx.mec_bitmap[i].queue_bitmap,
469 adev->gfx.num_compute_rings * num_xcc * GFX9_MEC_HPD_SIZE;
474 &adev->gfx.mec.hpd_eop_obj,
475 &adev->gfx.mec.hpd_eop_gpu_addr,
493 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj);
494 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);
497 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
500 (adev->gfx.mec_fw->data +
506 &adev->gfx.mec.mec_fw_obj,
507 &adev->gfx.mec.mec_fw_gpu_addr,
517 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj);
518 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj);
630 NUM_XCC(adev->gfx.xcc_mask) /
636 num_xcc = NUM_XCC(adev->gfx.xcc_mask);
649 adev->gfx.num_xcc_per_xcp = num_xccs_per_xcp;
658 xcc = hweight8(adev->gfx.xcc_mask & GENMASK(ih_node / 2, 0));
682 adev->gfx.funcs = &gfx_v9_4_3_gfx_funcs;
683 adev->gfx.ras = &gfx_v9_4_3_ras;
687 adev->gfx.config.max_hw_contexts = 8;
688 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
689 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
690 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
691 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
699 adev->gfx.config.gb_addr_config = gb_addr_config;
701 adev->gfx.config.gb_addr_config_fields.num_pipes = 1 <<
703 adev->gfx.config.gb_addr_config,
707 adev->gfx.config.max_tile_pipes =
708 adev->gfx.config.gb_addr_config_fields.num_pipes;
710 adev->gfx.config.gb_addr_config_fields.num_banks = 1 <<
712 adev->gfx.config.gb_addr_config,
715 adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 <<
717 adev->gfx.config.gb_addr_config,
720 adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 <<
722 adev->gfx.config.gb_addr_config,
725 adev->gfx.config.gb_addr_config_fields.num_se = 1 <<
727 adev->gfx.config.gb_addr_config,
730 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 +
732 adev->gfx.config.gb_addr_config,
743 struct amdgpu_ring *ring = &adev->gfx.compute_ring[ring_id];
747 ring = &adev->gfx.compute_ring[xcc_id * adev->gfx.num_compute_rings +
761 ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr +
762 (ring_id + xcc_id * adev->gfx.num_compute_rings) *
769 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec)
774 return amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type,
784 adev->gfx.mec.num_mec = 2;
785 adev->gfx.mec.num_pipe_per_mec = 4;
786 adev->gfx.mec.num_queue_per_pipe = 8;
788 num_xcc = NUM_XCC(adev->gfx.xcc_mask);
791 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_9_0__SRCID__CP_EOP_INTERRUPT, &adev->gfx.eop_irq);
797 &adev->gfx.priv_reg_irq);
803 &adev->gfx.priv_inst_irq);
807 adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE;
809 r = adev->gfx.rlc.funcs->init(adev);
824 for (i = 0; i < adev->gfx.mec.num_mec; ++i) {
825 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) {
826 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec;
850 kiq = &adev->gfx.kiq[xcc_id];
882 num_xcc = NUM_XCC(adev->gfx.xcc_mask);
883 for (i = 0; i < adev->gfx.num_compute_rings * num_xcc; i++)
884 amdgpu_ring_fini(&adev->gfx.compute_ring[i]);
888 amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq[i].ring);
893 amdgpu_bo_unref(&adev->gfx.rlc.clear_state_obj);
952 * Initialize all compute and user-gfx VMIDs to have no GDS, GWS, or OA
1015 num_xcc = NUM_XCC(adev->gfx.xcc_mask);
1017 gfx_v9_4_3_get_cu_info(adev, &adev->gfx.cu_info);
1018 adev->gfx.config.db_debug2 =
1038 if (adev->gfx.rlc.is_rlc_v2_1)
1094 num_xcc = NUM_XCC(adev->gfx.xcc_mask);
1096 reg_access_ctrl = &adev->gfx.rlc.reg_access_ctrl[GET_INST(GC, xcc_id)];
1110 if (adev->gfx.rlc.funcs->update_spm_vmid)
1111 adev->gfx.rlc.funcs->update_spm_vmid(adev, 0xf);
1123 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
1124 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
1186 num_xcc = NUM_XCC(adev->gfx.xcc_mask);
1205 num_xcc = NUM_XCC(adev->gfx.xcc_mask);
1230 num_xcc = NUM_XCC(adev->gfx.xcc_mask);
1239 rlc_ucode_ver, adev->gfx.rlc_fw_version);
1259 if (!adev->gfx.rlc_fw)
1262 hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
1265 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
1278 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version);
1312 num_xcc = NUM_XCC(adev->gfx.xcc_mask);
1389 adev->gfx.kiq[xcc_id].ring.sched.ready = false;
1404 if (!adev->gfx.mec_fw)
1409 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
1413 (adev->gfx.mec_fw->data +
1421 adev->gfx.mec.mec_fw_gpu_addr & 0xFFFFF000);
1423 upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr));
1436 WREG32(mec_ucode_addr_offset, adev->gfx.mec_fw_version);
1765 tmp_mqd = (struct v9_mqd *)adev->gfx.kiq[xcc_id].mqd_backup;
1768 if (adev->gfx.kiq[xcc_id].mqd_backup)
1769 memcpy(mqd, adev->gfx.kiq[xcc_id].mqd_backup, sizeof(struct v9_mqd_allocation));
1792 if (adev->gfx.kiq[xcc_id].mqd_backup)
1793 memcpy(adev->gfx.kiq[xcc_id].mqd_backup, mqd, sizeof(struct v9_mqd_allocation));
1803 int mqd_idx = ring - &adev->gfx.compute_ring[0];
1809 tmp_mqd = (struct v9_mqd *)adev->gfx.mec.mqd_backup[mqd_idx];
1822 if (adev->gfx.mec.mqd_backup[mqd_idx])
1823 memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(struct v9_mqd_allocation));
1826 if (adev->gfx.mec.mqd_backup[mqd_idx])
1827 memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(struct v9_mqd_allocation));
1842 for (j = 0; j < adev->gfx.num_compute_rings; j++) {
1843 ring = &adev->gfx.compute_ring[j + xcc_id * adev->gfx.num_compute_rings];
1863 ring = &adev->gfx.kiq[xcc_id].ring;
1889 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
1890 ring = &adev->gfx.compute_ring[i + xcc_id * adev->gfx.num_compute_rings];
1934 for (j = 0; j < adev->gfx.num_compute_rings; j++) {
1935 ring = &adev->gfx.compute_ring
1936 [j + xcc_id * adev->gfx.num_compute_rings];
1960 num_xcc = NUM_XCC(adev->gfx.xcc_mask);
1996 soc15_grbm_select(adev, adev->gfx.kiq[xcc_id].ring.me,
1997 adev->gfx.kiq[xcc_id].ring.pipe,
1998 adev->gfx.kiq[xcc_id].ring.queue, 0,
2000 gfx_v9_4_3_xcc_q_fini_register(&adev->gfx.kiq[xcc_id].ring,
2020 r = adev->gfx.rlc.funcs->resume(adev);
2036 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0);
2037 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0);
2039 num_xcc = NUM_XCC(adev->gfx.xcc_mask);
2062 num_xcc = NUM_XCC(adev->gfx.xcc_mask);
2118 adev->gfx.rlc.funcs->stop(adev);
2176 adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev),
2195 r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0);
2199 r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0);
2203 if (adev->gfx.ras &&
2204 adev->gfx.ras->enable_watchdog_timer)
2205 adev->gfx.ras->enable_watchdog_timer(adev);
2432 num_xcc = NUM_XCC(adev->gfx.xcc_mask);
2764 num_xcc = NUM_XCC(adev->gfx.xcc_mask);
2787 num_xcc = NUM_XCC(adev->gfx.xcc_mask);
2810 num_xcc = NUM_XCC(adev->gfx.xcc_mask);
2875 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
2876 ring = &adev->gfx.compute_ring
2878 xcc_id * adev->gfx.num_compute_rings];
2911 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
2912 ring = &adev->gfx.compute_ring
2914 xcc_id * adev->gfx.num_compute_rings];
2998 * number of gfx waves. Setting 5 bit will make sure gfx only gets
3011 for (i = 0; i < adev->gfx.mec.num_pipe_per_mec; i++) {
3906 struct amdgpu_cu_info *cu_info = &adev->gfx.cu_info;
3952 for (se_idx = 0; se_idx < adev->gfx.config.max_shader_engines; se_idx++) {
3953 for (sh_idx = 0; sh_idx < adev->gfx.config.max_sh_per_se; sh_idx++) {
3954 for (cu_idx = 0; cu_idx < adev->gfx.config.max_cu_per_sh; cu_idx++) {
4021 for (se_idx = 0; se_idx < adev->gfx.config.max_shader_engines; se_idx++) {
4022 for (sh_idx = 0; sh_idx < adev->gfx.config.max_sh_per_se; sh_idx++) {
4023 for (cu_idx = 0; cu_idx < adev->gfx.config.max_cu_per_sh; cu_idx++) {
4064 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
4188 num_xcc = NUM_XCC(adev->gfx.xcc_mask);
4190 adev->gfx.kiq[i].ring.funcs = &gfx_v9_4_3_ring_funcs_kiq;
4192 for (j = 0; j < adev->gfx.num_compute_rings; j++)
4193 adev->gfx.compute_ring[j + i * adev->gfx.num_compute_rings].funcs
4215 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST;
4216 adev->gfx.eop_irq.funcs = &gfx_v9_4_3_eop_irq_funcs;
4218 adev->gfx.priv_reg_irq.num_types = 1;
4219 adev->gfx.priv_reg_irq.funcs = &gfx_v9_4_3_priv_reg_irq_funcs;
4221 adev->gfx.priv_inst_irq.num_types = 1;
4222 adev->gfx.priv_inst_irq.funcs = &gfx_v9_4_3_priv_inst_irq_funcs;
4227 adev->gfx.rlc.funcs = &gfx_v9_4_3_rlc_funcs;
4285 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh);
4303 if (adev->gfx.config.max_shader_engines *
4304 adev->gfx.config.max_sh_per_se > 16)
4308 adev->gfx.config.max_shader_engines,
4309 adev->gfx.config.max_sh_per_se);
4312 for (xcc_id = 0; xcc_id < NUM_XCC(adev->gfx.xcc_mask); xcc_id++) {
4313 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
4314 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
4321 disable_masks[i * adev->gfx.config.max_sh_per_se + j],
4327 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) {
4329 if (counter < adev->gfx.config.max_cu_per_sh)