Searched refs:UL (Results 1 - 25 of 427) sorted by relevance

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/freebsd-12-stable/sys/sparc64/include/
H A Dlsu.h36 #define LSU_IC (1UL << 0)
37 #define LSU_DC (1UL << 1)
38 #define LSU_IM (1UL << 2)
39 #define LSU_DM (1UL << 3)
44 #define LSU_FM_MASK (((1UL << LSU_FM_BITS) - 1) << LSU_FM_SHIFT)
48 #define LSU_VM_MASK (((1UL << LSU_VM_BITS) - 1) << LSU_VM_SHIFT)
52 #define LSU_PM_MASK (((1UL << LSU_PM_BITS) - 1) << LSU_PM_SHIFT)
54 #define LSU_VW (1UL << 21)
55 #define LSU_VR (1UL << 22)
56 #define LSU_PW (1UL << 2
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H A Ddcr.h37 #define DCR_MS (1UL << 0)
38 #define DCR_IFPOE (1UL << 1)
39 #define DCR_SI (1UL << 3)
40 #define DCR_RPE (1UL << 4)
41 #define DCR_BPE (1UL << 5)
46 (((1UL << DCR_OBSDATA_CT_BITS) - 1) << DCR_OBSDATA_SHIFT)
49 #define DCR_IPE (1UL << 2)
53 (((1UL << DCR_OBSDATA_CTP_BITS) - 1) << DCR_OBSDATA_SHIFT)
55 #define DCR_DPE (1UL << 12)
61 (((1UL << DCR_BPM_BIT
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H A Dccr.h34 #define ICC_MASK ((1UL << ICC_BITS) - 1)
35 #define ICC_C (1UL << 0)
36 #define ICC_V (1UL << 1)
37 #define ICC_Z (1UL << 2)
38 #define ICC_N (1UL << 3)
42 #define XCC_MASK (((1UL << XCC_BITS) - 1) << XCC_SHIFT)
43 #define XCC_C (1UL << 4)
44 #define XCC_V (1UL << 5)
45 #define XCC_Z (1UL << 6)
46 #define XCC_N (1UL <<
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H A Dmcntl.h37 #define MCNTL_JPS1_TSBP (1UL << 8)
42 (((1UL << MCNTL_RMD_BITS) - 1) << MCNTL_RMD_SHIFT)
43 #define MCNTL_RMD_FULL (0UL << MCNTL_RMD_SHIFT)
44 #define MCNTL_RMD_1024 (2UL << MCNTL_RMD_SHIFT)
45 #define MCNTL_RMD_512 (3UL << MCNTL_RMD_SHIFT)
47 #define MCNTL_FW_FDTLB (1UL << 14)
48 #define MCNTL_FW_FITLB (1UL << 15)
49 #define MCNTL_NC_CACHE (1UL << 16)
52 #define MCNTL_MPG_SDTLB (1UL << 6)
53 #define MCNTL_MPG_SITLB (1UL <<
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H A Drunq.h34 #define RQB_LEN (1UL) /* Number of priority status words. */
35 #define RQB_L2BPW (6UL) /* Log2(sizeof(rqb_word_t) * NBBY)). */
36 #define RQB_BPW (1UL<<RQB_L2BPW) /* Bits in an rqb_word_t. */
38 #define RQB_BIT(pri) (1UL << ((pri) & (RQB_BPW - 1)))
55 for (bit = 1; (mask & 1UL) == 0; bit++)
56 mask >>= 1UL;
H A Dtte.h66 #define TD_SIZE_MASK ((1UL << TD_SIZE_BITS) - 1)
67 #define TD_SOFT2_MASK ((1UL << TD_SOFT2_BITS) - 1)
68 #define TD_RSVD2_MASK ((1UL << TD_RSVD2_BITS) - 1)
69 #define TD_SIZE2_MASK ((1UL << TD_SIZE2_BITS) - 1)
70 #define TD_DIAG_SF_MASK ((1UL << TD_DIAG_SF_BITS) - 1)
71 #define TD_RSVD_CH_MASK ((1UL << TD_RSVD_CH_BITS) - 1)
72 #define TD_RSVD_OC_MASK ((1UL << TD_RSVD_OC_BITS) - 1)
73 #define TD_RSVD_PT_MASK ((1UL << TD_RSVD_PT_BITS) - 1)
74 #define TD_RSVD_VE_MASK ((1UL << TD_RSVD_VE_BITS) - 1)
75 #define TD_PA_CH_MASK ((1UL << TD_PA_CH_BIT
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H A Dtlb.h38 #define TLB_DIRECT_ADDRESS_MASK ((1UL << TLB_DIRECT_ADDRESS_BITS) - 1)
39 #define TLB_DIRECT_PAGE_MASK ((1UL << TLB_DIRECT_PAGE_BITS) - 1)
69 (((1UL << TLB_CXR_CTX_BITS) - 1) << TLB_CXR_CTX_SHIFT)
92 (((1UL << TLB_TAE_PGSZ_BITS) - 1) << TLB_TAE_PGSZ0_SHIFT)
94 (((1UL << TLB_TAE_PGSZ_BITS) - 1) << TLB_TAE_PGSZ1_SHIFT)
138 (((sfsr) >> MMU_SFSR_ASI_SHIFT) & ((1UL << MMU_SFSR_ASI_SIZE) - 1))
140 (((sfsr) >> MMU_SFSR_FT_SHIFT) & ((1UL << MMU_SFSR_FT_SIZE) - 1))
142 (((sfsr) >> MMU_SFSR_CT_SHIFT) & ((1UL << MMU_SFSR_CT_SIZE) - 1))
144 #define MMU_SFSR_E (1UL << MMU_SFSR_E_SHIFT)
145 #define MMU_SFSR_PR (1UL << MMU_SFSR_PR_SHIF
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/freebsd-12-stable/sys/arm/ti/
H A Dti_i2c.h45 #define I2C_IE_XDR (1UL << 14) /* Transmit draining interrupt */
46 #define I2C_IE_RDR (1UL << 13) /* Receive draining interrupt */
47 #define I2C_IE_AAS (1UL << 9) /* Addressed as Slave interrupt */
48 #define I2C_IE_BF (1UL << 8) /* Bus Free interrupt */
49 #define I2C_IE_AERR (1UL << 7) /* Access Error interrupt */
50 #define I2C_IE_STC (1UL << 6) /* Start Condition interrupt */
51 #define I2C_IE_GC (1UL << 5) /* General Call interrupt */
52 #define I2C_IE_XRDY (1UL << 4) /* Transmit Data Ready interrupt */
53 #define I2C_IE_RRDY (1UL << 3) /* Receive Data Ready interrupt */
54 #define I2C_IE_ARDY (1UL <<
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H A Dti_sdma.h66 #define TI_SDMA_STATUS_DROP (1UL << 1)
67 #define TI_SDMA_STATUS_HALF (1UL << 2)
68 #define TI_SDMA_STATUS_FRAME (1UL << 3)
69 #define TI_SDMA_STATUS_LAST (1UL << 4)
70 #define TI_SDMA_STATUS_BLOCK (1UL << 5)
71 #define TI_SDMA_STATUS_SYNC (1UL << 6)
72 #define TI_SDMA_STATUS_PKT (1UL << 7)
73 #define TI_SDMA_STATUS_TRANS_ERR (1UL << 8)
74 #define TI_SDMA_STATUS_SECURE_ERR (1UL << 9)
75 #define TI_SDMA_STATUS_SUPERVISOR_ERR (1UL << 1
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H A Dti_sdmareg.h102 #define DMA4_CSR_DROP (1UL << 1)
103 #define DMA4_CSR_HALF (1UL << 2)
104 #define DMA4_CSR_FRAME (1UL << 3)
105 #define DMA4_CSR_LAST (1UL << 4)
106 #define DMA4_CSR_BLOCK (1UL << 5)
107 #define DMA4_CSR_SYNC (1UL << 6)
108 #define DMA4_CSR_PKT (1UL << 7)
109 #define DMA4_CSR_TRANS_ERR (1UL << 8)
110 #define DMA4_CSR_SECURE_ERR (1UL << 9)
111 #define DMA4_CSR_SUPERVISOR_ERR (1UL << 1
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/freebsd-12-stable/sys/dev/virtio/
H A Dvirtio_config.h53 #define VIRTIO_F_NOTIFY_ON_EMPTY (1UL << 24)
56 #define VIRTIO_F_ANY_LAYOUT (1UL << 27)
59 #define VIRTIO_RING_F_INDIRECT_DESC (1UL << 28)
62 #define VIRTIO_RING_F_EVENT_IDX (1UL << 29)
68 #define VIRTIO_F_BAD_FEATURE (1UL << 30)
/freebsd-12-stable/sys/dev/isci/scil/
H A Dscu_viit_data.h73 #define SCU_VIIT_ENTRY_ID_SHIFT (30UL)
76 #define SCU_VIIT_ENTRY_FUNCTION_SHIFT (20UL)
79 #define SCU_VIIT_ENTRY_IPPTMODE_SHIFT (12UL)
82 #define SCU_VIIT_ENTRY_LPVIE_SHIFT (8UL)
85 #define SCU_VIIT_ENTRY_STATUS_SHIFT (0UL)
87 #define SCU_VIIT_ENTRY_ID_INVALID (0UL << SCU_VIIT_ENTRY_ID_SHIFT)
88 #define SCU_VIIT_ENTRY_ID_VIIT (1UL << SCU_VIIT_ENTRY_ID_SHIFT)
89 #define SCU_VIIT_ENTRY_ID_IIT (2UL << SCU_VIIT_ENTRY_ID_SHIFT)
90 #define SCU_VIIT_ENTRY_ID_VIRT_EXP (3UL << SCU_VIIT_ENTRY_ID_SHIFT)
147 #define SCU_IIT_ENTRY_ID_SHIFT (30UL)
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H A Dscu_registers.h93 #define SMU_POST_CONTEXT_PORT_CONTEXT_INDEX_SHIFT (0UL)
95 #define SMU_POST_CONTEXT_PORT_LOGICAL_PORT_INDEX_SHIFT (12UL)
97 #define SMU_POST_CONTEXT_PORT_PROTOCOL_ENGINE_SHIFT (16UL)
99 #define SMU_POST_CONTEXT_PORT_COMMAND_CONTEXT_SHIFT (18UL)
107 #define SMU_INTERRUPT_STATUS_COMPLETION_SHIFT (31UL)
109 #define SMU_INTERRUPT_STATUS_QUEUE_SUSPEND_SHIFT (1UL)
111 #define SMU_INTERRUPT_STATUS_QUEUE_ERROR_SHIFT (0UL)
123 #define SMU_INTERRUPT_MASK_COMPLETION_SHIFT (31UL)
125 #define SMU_INTERRUPT_MASK_QUEUE_SUSPEND_SHIFT (1UL)
127 #define SMU_INTERRUPT_MASK_QUEUE_ERROR_SHIFT (0UL)
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/freebsd-12-stable/sys/powerpc/include/
H A Drunq.h35 #define RQB_LEN (1UL) /* Number of priority status words. */
36 #define RQB_L2BPW (6UL) /* Log2(sizeof(rqb_word_t) * NBBY)). */
41 #define RQB_BPW (1UL<<RQB_L2BPW) /* Bits in an rqb_word_t. */
43 #define RQB_BIT(pri) (1UL << ((pri) & (RQB_BPW - 1)))
/freebsd-12-stable/sys/xen/interface/
H A Dnmi.h38 #define XEN_NMIREASON_io_error (1UL << _XEN_NMIREASON_io_error)
41 #define XEN_NMIREASON_pci_serr (1UL << _XEN_NMIREASON_pci_serr)
45 #define XEN_NMIREASON_parity_error (1UL << _XEN_NMIREASON_parity_error)
49 #define XEN_NMIREASON_unknown (1UL << _XEN_NMIREASON_unknown)
H A Dxencomm.h33 #define XENCOMM_INVALID (~0UL)
/freebsd-12-stable/sys/arm/ti/omap4/
H A Domap4_scm_padconf.h35 #define CONTROL_PADCONF_WAKEUP_EVENT (1UL << 15)
36 #define CONTROL_PADCONF_WAKEUP_ENABLE (1UL << 14)
37 #define CONTROL_PADCONF_OFF_PULL_UP (1UL << 13)
38 #define CONTROL_PADCONF_OFF_PULL_ENABLE (1UL << 12)
39 #define CONTROL_PADCONF_OFF_OUT_HIGH (1UL << 11)
40 #define CONTROL_PADCONF_OFF_OUT_ENABLE (1UL << 10)
41 #define CONTROL_PADCONF_OFF_ENABLE (1UL << 9)
42 #define CONTROL_PADCONF_INPUT_ENABLE (1UL << 8)
43 #define CONTROL_PADCONF_PULL_UP (1UL << 4)
44 #define CONTROL_PADCONF_PULL_ENABLE (1UL <<
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/freebsd-12-stable/sys/dev/pccbb/
H A Dpccbbreg.h205 #define CBB_STATE_CSTCHG (1UL << 0) /* Card Status Change */
206 #define CBB_STATE_CD1_CHANGE (1UL << 1) /* Card Detect 1 */
207 #define CBB_STATE_CD2_CHANGE (1UL << 2) /* Card Detect 2 */
208 #define CBB_STATE_CD (3UL << 1) /* Card Detect all */
209 #define CBB_STATE_POWER_CYCLE (1UL << 3) /* Power Cycle */
210 #define CBB_STATE_R2_CARD (1UL << 4) /* 16-bit Card */
211 #define CBB_STATE_CB_CARD (1UL << 5) /* Cardbus Card */
212 #define CBB_STATE_IREQ (1UL << 6) /* Ready */
213 #define CBB_STATE_NOT_A_CARD (1UL << 7) /* Unrecognized Card */
214 #define CBB_STATE_DATA_LOST (1UL <<
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/freebsd-12-stable/sys/arm64/include/
H A Darmreg.h46 #define UL(x) UINT64_C(x) macro
179 #define ID_AA64DFR0_MASK UL(0x0000000ff0f0ffff)
181 #define ID_AA64DFR0_DebugVer_MASK (UL(0xf) << ID_AA64DFR0_DebugVer_SHIFT)
183 #define ID_AA64DFR0_DebugVer_8 (UL(0x6) << ID_AA64DFR0_DebugVer_SHIFT)
184 #define ID_AA64DFR0_DebugVer_8_VHE (UL(0x7) << ID_AA64DFR0_DebugVer_SHIFT)
185 #define ID_AA64DFR0_DebugVer_8_2 (UL(0x8) << ID_AA64DFR0_DebugVer_SHIFT)
187 #define ID_AA64DFR0_TraceVer_MASK (UL(0xf) << ID_AA64DFR0_TraceVer_SHIFT)
189 #define ID_AA64DFR0_TraceVer_NONE (UL(0x0) << ID_AA64DFR0_TraceVer_SHIFT)
190 #define ID_AA64DFR0_TraceVer_IMPL (UL(0x1) << ID_AA64DFR0_TraceVer_SHIFT)
192 #define ID_AA64DFR0_PMUVer_MASK (UL(
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/freebsd-12-stable/sys/dev/random/
H A Duint128.h50 static const uint128_t very_long_zero = {0UL,0UL};
61 if (big_uintp->u128t_word0 == 0UL)
72 return (big_uint.u128t_word0 == 0UL && big_uint.u128t_word1 == 0UL);
/freebsd-12-stable/sys/dev/vnic/
H A Dthunder_bgx.h46 #define CMR_PKT_TX_EN (1UL << 13)
47 #define CMR_PKT_RX_EN (1UL << 14)
48 #define CMR_EN (1UL << 15)
50 #define CMR_GLOBAL_CFG_FCS_STRIP (1UL << 6)
66 #define RX_DMACX_CAM_EN (1UL << 48)
95 #define SPU_CTL_LOW_POWER (1UL << 11)
96 #define SPU_CTL_LOOPBACK (1UL << 14)
97 #define SPU_CTL_RESET (1UL << 15)
99 #define SPU_STATUS1_RCV_LNK (1UL << 2)
101 #define SPU_STATUS2_RCVFLT (1UL << 1
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H A Dnicvf_queues.h55 #define RBDR_SIZE0 0UL /* 8K entries */
56 #define RBDR_SIZE1 1UL /* 16K entries */
57 #define RBDR_SIZE2 2UL /* 32K entries */
58 #define RBDR_SIZE3 3UL /* 64K entries */
59 #define RBDR_SIZE4 4UL /* 126K entries */
60 #define RBDR_SIZE5 5UL /* 256K entries */
61 #define RBDR_SIZE6 6UL /* 512K entries */
63 #define SND_QUEUE_SIZE0 0UL /* 1K entries */
64 #define SND_QUEUE_SIZE1 1UL /* 2K entries */
65 #define SND_QUEUE_SIZE2 2UL /*
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/freebsd-12-stable/sys/sparc64/pci/
H A Dpsychoreg.h278 #define UEAFSR_BLK (1UL << 23) /* Error caused by block transaction */
279 #define UEAFSR_P_DTE (1UL << 56) /* Pri. DVMA translation error */
280 #define UEAFSR_S_DTE (1UL << 57) /* Sec. DVMA translation error */
281 #define UEAFSR_S_DWR (1UL << 58) /* Sec. error during DVMA write */
282 #define UEAFSR_S_DRD (1UL << 59) /* Sec. error during DVMA read */
283 #define UEAFSR_S_PIO (1UL << 60) /* Sec. error during PIO access */
284 #define UEAFSR_P_DWR (1UL << 61) /* Pri. error during DVMA write */
285 #define UEAFSR_P_DRD (1UL << 62) /* Pri. error during DVMA read */
286 #define UEAFSR_P_PIO (1UL << 63) /* Pri. error during PIO access */
289 #define CEAFSR_BLK (1UL << 2
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/freebsd-12-stable/contrib/elftoolchain/libelftc/
H A Dlibelftc_hash.c48 #if INT_MAX == 2147483647UL
49 #define FNV_PRIME 16777619UL
50 #define FNV_OFFSET 2166136261UL
/freebsd-12-stable/sys/arm/ti/usb/
H A Domap_host.c58 #define UHH_SYSCONFIG_MIDLEMODE_MASK (3UL << 12)
59 #define UHH_SYSCONFIG_MIDLEMODE_SMARTSTANDBY (2UL << 12)
60 #define UHH_SYSCONFIG_MIDLEMODE_NOSTANDBY (1UL << 12)
61 #define UHH_SYSCONFIG_MIDLEMODE_FORCESTANDBY (0UL << 12)
62 #define UHH_SYSCONFIG_CLOCKACTIVITY (1UL << 8)
63 #define UHH_SYSCONFIG_SIDLEMODE_MASK (3UL << 3)
64 #define UHH_SYSCONFIG_SIDLEMODE_SMARTIDLE (2UL << 3)
65 #define UHH_SYSCONFIG_SIDLEMODE_NOIDLE (1UL << 3)
66 #define UHH_SYSCONFIG_SIDLEMODE_FORCEIDLE (0UL << 3)
67 #define UHH_SYSCONFIG_ENAWAKEUP (1UL <<
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