1/*-
2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
3 *
4 * Copyright 2001 by Thomas Moestl <tmm@FreeBSD.org>.  All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 *    notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 *    notice, this list of conditions and the following disclaimer in the
13 *    documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
19 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
20 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
21 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
22 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
23 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
24 * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 *
26 * $FreeBSD$
27 */
28
29#ifndef	_MACHINE_LSU_H_
30#define	_MACHINE_LSU_H_
31
32/*
33 * Definitions for the Load-Store-Unit Control Register. This is called
34 * Data Cache Unit Control Register (DCUCR) for UltraSPARC-III and greater.
35 */
36#define	LSU_IC		(1UL << 0)
37#define	LSU_DC		(1UL << 1)
38#define	LSU_IM		(1UL << 2)
39#define	LSU_DM		(1UL << 3)
40
41/* Parity control mask, UltraSPARC-I and II series only. */
42#define	LSU_FM_SHIFT	4
43#define	LSU_FM_BITS	16
44#define	LSU_FM_MASK	(((1UL << LSU_FM_BITS) - 1) << LSU_FM_SHIFT)
45
46#define	LSU_VM_SHIFT	25
47#define	LSU_VM_BITS	8
48#define	LSU_VM_MASK	(((1UL << LSU_VM_BITS) - 1) << LSU_VM_SHIFT)
49
50#define	LSU_PM_SHIFT	33
51#define	LSU_PM_BITS	8
52#define	LSU_PM_MASK	(((1UL << LSU_PM_BITS) - 1) << LSU_PM_SHIFT)
53
54#define	LSU_VW		(1UL << 21)
55#define	LSU_VR		(1UL << 22)
56#define	LSU_PW		(1UL << 23)
57#define	LSU_PR		(1UL << 24)
58
59/* The following bits are valid for the UltraSPARC-III series only. */
60#define	LSU_WE		(1UL << 41)
61#define	LSU_SL		(1UL << 42)
62#define	LSU_SPE		(1UL << 43)
63#define	LSU_HPE		(1UL << 44)
64#define	LSU_PE		(1UL << 45)
65#define	LSU_RE		(1UL << 46)
66#define	LSU_ME		(1UL << 47)
67#define	LSU_CV		(1UL << 48)
68#define	LSU_CP		(1UL << 49)
69
70/* The following bit is valid for the UltraSPARC-IV only. */
71#define	LSU_WIH		(1UL << 4)
72
73/* The following bits are valid for the UltraSPARC-IV+ only. */
74#define	LSU_PPS_SHIFT	50
75#define	LSU_PPS_BITS	2
76#define	LSU_PPS_MASK	(((1UL << LSU_PPS_BITS) - 1) << LSU_PPS_SHIFT)
77
78#define	LSU_IPS_SHIFT	52
79#define	LSU_IPS_BITS	2
80#define	LSU_IPS_MASK	(((1UL << LSU_IPS_BITS) - 1) << LSU_IPS_SHIFT)
81
82#define	LSU_PCM		(1UL << 54)
83#define	LSU_WCE		(1UL << 55)
84
85/* The following bit is valid for the SPARC64 V, VI, VII and VIIIfx only. */
86#define	LSU_WEAK_SPCA	(1UL << 41)
87
88#endif	/* _MACHINE_LSU_H_ */
89