Lines Matching refs:UL
66 #define TD_SIZE_MASK ((1UL << TD_SIZE_BITS) - 1)
67 #define TD_SOFT2_MASK ((1UL << TD_SOFT2_BITS) - 1)
68 #define TD_RSVD2_MASK ((1UL << TD_RSVD2_BITS) - 1)
69 #define TD_SIZE2_MASK ((1UL << TD_SIZE2_BITS) - 1)
70 #define TD_DIAG_SF_MASK ((1UL << TD_DIAG_SF_BITS) - 1)
71 #define TD_RSVD_CH_MASK ((1UL << TD_RSVD_CH_BITS) - 1)
72 #define TD_RSVD_OC_MASK ((1UL << TD_RSVD_OC_BITS) - 1)
73 #define TD_RSVD_PT_MASK ((1UL << TD_RSVD_PT_BITS) - 1)
74 #define TD_RSVD_VE_MASK ((1UL << TD_RSVD_VE_BITS) - 1)
75 #define TD_PA_CH_MASK ((1UL << TD_PA_CH_BITS) - 1)
76 #define TD_PA_OC_MASK ((1UL << TD_PA_OC_BITS) - 1)
77 #define TD_PA_SF_MASK ((1UL << TD_PA_SF_BITS) - 1)
78 #define TD_PA_MASK ((1UL << TD_PA_BITS) - 1)
79 #define TD_SOFT_MASK ((1UL << TD_SOFT_BITS) - 1)
81 #define TS_8K (0UL)
82 #define TS_64K (1UL)
83 #define TS_512K (2UL)
84 #define TS_4M (3UL)
85 #define TS_32M (4UL) /* US-IV+, SPARC64 VI, VII only */
86 #define TS_256M (5UL) /* US-IV+, SPARC64 VI, VII only */
87 #define TS_2G (6UL) /* SPARC64 VIIIfx only */
92 #define TD_V (1UL << 63)
106 #define TD_NFO (1UL << 60)
107 #define TD_IE (1UL << 59)
110 #define TD_FAKE ((1UL << 5) << TD_SOFT_SHIFT)
111 #define TD_EXEC ((1UL << 4) << TD_SOFT_SHIFT)
112 #define TD_REF ((1UL << 3) << TD_SOFT_SHIFT)
113 #define TD_PV ((1UL << 2) << TD_SOFT_SHIFT)
114 #define TD_SW ((1UL << 1) << TD_SOFT_SHIFT)
115 #define TD_WIRED ((1UL << 0) << TD_SOFT_SHIFT)
116 #define TD_L (1UL << 6)
117 #define TD_CP (1UL << 5)
118 #define TD_CV (1UL << 4)
119 #define TD_E (1UL << 3)
120 #define TD_P (1UL << 2)
121 #define TD_W (1UL << 1)
122 #define TD_G (1UL << 0)