Lines Matching refs:UL
102 #define DMA4_CSR_DROP (1UL << 1)
103 #define DMA4_CSR_HALF (1UL << 2)
104 #define DMA4_CSR_FRAME (1UL << 3)
105 #define DMA4_CSR_LAST (1UL << 4)
106 #define DMA4_CSR_BLOCK (1UL << 5)
107 #define DMA4_CSR_SYNC (1UL << 6)
108 #define DMA4_CSR_PKT (1UL << 7)
109 #define DMA4_CSR_TRANS_ERR (1UL << 8)
110 #define DMA4_CSR_SECURE_ERR (1UL << 9)
111 #define DMA4_CSR_SUPERVISOR_ERR (1UL << 10)
112 #define DMA4_CSR_MISALIGNED_ADRS_ERR (1UL << 11)
113 #define DMA4_CSR_DRAIN_END (1UL << 12)
116 #define DMA4_CICR_DROP_IE (1UL << 1)
117 #define DMA4_CICR_HALF_IE (1UL << 2)
118 #define DMA4_CICR_FRAME_IE (1UL << 3)
119 #define DMA4_CICR_LAST_IE (1UL << 4)
120 #define DMA4_CICR_BLOCK_IE (1UL << 5)
121 #define DMA4_CICR_PKT_IE (1UL << 7)
122 #define DMA4_CICR_TRANS_ERR_IE (1UL << 8)
123 #define DMA4_CICR_SECURE_ERR_IE (1UL << 9)
124 #define DMA4_CICR_SUPERVISOR_ERR_IE (1UL << 10)
125 #define DMA4_CICR_MISALIGNED_ADRS_ERR_IE (1UL << 11)
126 #define DMA4_CICR_DRAIN_IE (1UL << 12)