Lines Matching refs:UL
46 #define CMR_PKT_TX_EN (1UL << 13)
47 #define CMR_PKT_RX_EN (1UL << 14)
48 #define CMR_EN (1UL << 15)
50 #define CMR_GLOBAL_CFG_FCS_STRIP (1UL << 6)
66 #define RX_DMACX_CAM_EN (1UL << 48)
95 #define SPU_CTL_LOW_POWER (1UL << 11)
96 #define SPU_CTL_LOOPBACK (1UL << 14)
97 #define SPU_CTL_RESET (1UL << 15)
99 #define SPU_STATUS1_RCV_LNK (1UL << 2)
101 #define SPU_STATUS2_RCVFLT (1UL << 10)
103 #define SPU_BX_STATUS_RX_ALIGN (1UL << 12)
105 #define SPU_BR_STATUS_BLK_LOCK (1UL << 0)
106 #define SPU_BR_STATUS_RCV_LNK (1UL << 12)
108 #define SPU_PMD_CRTL_TRAIN_EN (1UL << 1)
113 #define SPU_FEC_CTL_FEC_EN (1UL << 0)
114 #define SPU_FEC_CTL_ERR_EN (1UL << 1)
116 #define SPU_AN_CTL_AN_EN (1UL << 12)
117 #define SPU_AN_CTL_XNP_EN (1UL << 13)
120 #define SPU_MISC_CTL_INTLV_RDISP (1UL << 10)
121 #define SPU_MISC_CTL_RX_DIS (1UL << 12)
127 #define SPU_DBG_CTL_AN_ARB_LINK_CHK_EN (1UL << 18)
128 #define SPU_DBG_CTL_AN_NONCE_MCT_DIS (1UL << 29)
133 #define SMU_RX_CTL_STATUS (3UL << 0)
135 #define SMU_TX_APPEND_FCS_D (1UL << 2)
139 #define SMU_TX_CTL_DIC_EN (1UL << 0)
140 #define SMU_TX_CTL_UNI_EN (1UL << 1)
141 #define SMU_TX_CTL_LNK_STATUS (3UL << 4)
144 #define SMU_CTL_RX_IDLE (1UL << 0)
145 #define SMU_CTL_TX_IDLE (1UL << 1)
148 #define PCS_MRX_CTL_RST_AN (1UL << 9)
149 #define PCS_MRX_CTL_PWR_DN (1UL << 11)
150 #define PCS_MRX_CTL_AN_EN (1UL << 12)
151 #define PCS_MRX_CTL_LOOPBACK1 (1UL << 14)
152 #define PCS_MRX_CTL_RESET (1UL << 15)
154 #define PCS_MRX_STATUS_AN_CPT (1UL << 5)
158 #define PCS_MISC_CTL_GMX_ENO (1UL << 11)
161 #define GMI_PORT_CFG_SPEED (1UL << 1)
162 #define GMI_PORT_CFG_DUPLEX (1UL << 2)
163 #define GMI_PORT_CFG_SLOT_TIME (1UL << 3)
164 #define GMI_PORT_CFG_SPEED_MSB (1UL << 8)