1/*- 2 * SPDX-License-Identifier: BSD-2-Clause OR GPL-2.0 3 * 4 * This file is provided under a dual BSD/GPLv2 license. When using or 5 * redistributing this file, you may do so under either license. 6 * 7 * GPL LICENSE SUMMARY 8 * 9 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved. 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of version 2 of the GNU General Public License as 13 * published by the Free Software Foundation. 14 * 15 * This program is distributed in the hope that it will be useful, but 16 * WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 18 * General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License 21 * along with this program; if not, write to the Free Software 22 * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 23 * The full GNU General Public License is included in this distribution 24 * in the file called LICENSE.GPL. 25 * 26 * BSD LICENSE 27 * 28 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved. 29 * All rights reserved. 30 * 31 * Redistribution and use in source and binary forms, with or without 32 * modification, are permitted provided that the following conditions 33 * are met: 34 * 35 * * Redistributions of source code must retain the above copyright 36 * notice, this list of conditions and the following disclaimer. 37 * * Redistributions in binary form must reproduce the above copyright 38 * notice, this list of conditions and the following disclaimer in 39 * the documentation and/or other materials provided with the 40 * distribution. 41 * 42 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 43 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 44 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 45 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 46 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 47 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 48 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 49 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 50 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 51 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 52 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 53 * 54 * $FreeBSD$ 55 */ 56#ifndef _SCU_REGISTERS_H_ 57#define _SCU_REGISTERS_H_ 58 59/** 60 * @file 61 * 62 * @brief This file contains the constants and structures for the SCU memory 63 * mapped registers. 64 */ 65#ifdef __cplusplus 66extern "C" { 67#endif 68 69#include <dev/isci/scil/sci_types.h> 70#include <dev/isci/scil/scu_viit_data.h> 71 72 73 74// Generate a value for an SCU register 75#define SCU_GEN_VALUE(name, value) \ 76 (((U32)(value) << name ## _SHIFT) & (name ## _MASK)) 77 78// Generate a bit value for an SCU register 79// Make sure that the register MASK is just a single bit 80#define SCU_GEN_BIT(name) \ 81 SCU_GEN_VALUE(name, ((U32)1)) 82 83#define SCU_SET_BIT(name, reg_value) \ 84 ((reg_value) | SCU_GEN_BIT(name)) 85 86#define SCU_CLEAR_BIT(name, reg_value) \ 87 ((reg_value) $ ~(SCU_GEN_BIT(name))) 88 89//***************************************************************************** 90// Unions for bitfield definitions of SCU Registers 91// SMU Post Context Port 92//***************************************************************************** 93#define SMU_POST_CONTEXT_PORT_CONTEXT_INDEX_SHIFT (0UL) 94#define SMU_POST_CONTEXT_PORT_CONTEXT_INDEX_MASK (0x00000FFFUL) 95#define SMU_POST_CONTEXT_PORT_LOGICAL_PORT_INDEX_SHIFT (12UL) 96#define SMU_POST_CONTEXT_PORT_LOGICAL_PORT_INDEX_MASK (0x0000F000UL) 97#define SMU_POST_CONTEXT_PORT_PROTOCOL_ENGINE_SHIFT (16UL) 98#define SMU_POST_CONTEXT_PORT_PROTOCOL_ENGINE_MASK (0x00030000UL) 99#define SMU_POST_CONTEXT_PORT_COMMAND_CONTEXT_SHIFT (18UL) 100#define SMU_POST_CONTEXT_PORT_COMMAND_CONTEXT_MASK (0x00FC0000UL) 101#define SMU_POST_CONTEXT_PORT_RESERVED_MASK (0xFF000000UL) 102 103#define SMU_PCP_GEN_VAL(name, value) \ 104 SCU_GEN_VALUE(SMU_POST_CONTEXT_PORT_##name, value) 105 106//***************************************************************************** 107#define SMU_INTERRUPT_STATUS_COMPLETION_SHIFT (31UL) 108#define SMU_INTERRUPT_STATUS_COMPLETION_MASK (0x80000000UL) 109#define SMU_INTERRUPT_STATUS_QUEUE_SUSPEND_SHIFT (1UL) 110#define SMU_INTERRUPT_STATUS_QUEUE_SUSPEND_MASK (0x00000002UL) 111#define SMU_INTERRUPT_STATUS_QUEUE_ERROR_SHIFT (0UL) 112#define SMU_INTERRUPT_STATUS_QUEUE_ERROR_MASK (0x00000001UL) 113#define SMU_INTERRUPT_STATUS_RESERVED_MASK (0x7FFFFFFCUL) 114 115#define SMU_ISR_GEN_BIT(name) \ 116 SCU_GEN_BIT(SMU_INTERRUPT_STATUS_##name) 117 118#define SMU_ISR_QUEUE_ERROR SMU_ISR_GEN_BIT(QUEUE_ERROR) 119#define SMU_ISR_QUEUE_SUSPEND SMU_ISR_GEN_BIT(QUEUE_SUSPEND) 120#define SMU_ISR_COMPLETION SMU_ISR_GEN_BIT(COMPLETION) 121 122//***************************************************************************** 123#define SMU_INTERRUPT_MASK_COMPLETION_SHIFT (31UL) 124#define SMU_INTERRUPT_MASK_COMPLETION_MASK (0x80000000UL) 125#define SMU_INTERRUPT_MASK_QUEUE_SUSPEND_SHIFT (1UL) 126#define SMU_INTERRUPT_MASK_QUEUE_SUSPEND_MASK (0x00000002UL) 127#define SMU_INTERRUPT_MASK_QUEUE_ERROR_SHIFT (0UL) 128#define SMU_INTERRUPT_MASK_QUEUE_ERROR_MASK (0x00000001UL) 129#define SMU_INTERRUPT_MASK_RESERVED_MASK (0x7FFFFFFCUL) 130 131#define SMU_IMR_GEN_BIT(name) \ 132 SCU_GEN_BIT(SMU_INTERRUPT_MASK_##name) 133 134#define SMU_IMR_QUEUE_ERROR SMU_IMR_GEN_BIT(QUEUE_ERROR) 135#define SMU_IMR_QUEUE_SUSPEND SMU_IMR_GEN_BIT(QUEUE_SUSPEND) 136#define SMU_IMR_COMPLETION SMU_IMR_GEN_BIT(COMPLETION) 137 138//***************************************************************************** 139#define SMU_INTERRUPT_COALESCING_CONTROL_TIMER_SHIFT (0UL) 140#define SMU_INTERRUPT_COALESCING_CONTROL_TIMER_MASK (0x0000001FUL) 141#define SMU_INTERRUPT_COALESCING_CONTROL_NUMBER_SHIFT (8UL) 142#define SMU_INTERRUPT_COALESCING_CONTROL_NUMBER_MASK (0x0000FF00UL) 143#define SMU_INTERRUPT_COALESCING_CONTROL_RESERVED_MASK (0xFFFF00E0UL) 144 145#define SMU_ICC_GEN_VAL(name, value) \ 146 SCU_GEN_VALUE(SMU_INTERRUPT_COALESCING_CONTROL_##name, value) 147 148//***************************************************************************** 149#define SMU_TASK_CONTEXT_RANGE_START_SHIFT (0UL) 150#define SMU_TASK_CONTEXT_RANGE_START_MASK (0x00000FFFUL) 151#define SMU_TASK_CONTEXT_RANGE_ENDING_SHIFT (16UL) 152#define SMU_TASK_CONTEXT_RANGE_ENDING_MASK (0x0FFF0000UL) 153#define SMU_TASK_CONTEXT_RANGE_ENABLE_SHIFT (31UL) 154#define SMU_TASK_CONTEXT_RANGE_ENABLE_MASK (0x80000000UL) 155#define SMU_TASK_CONTEXT_RANGE_RESERVED_MASK (0x7000F000UL) 156 157#define SMU_TCR_GEN_VAL(name, value) \ 158 SCU_GEN_VALUE(SMU_TASK_CONTEXT_RANGE_##name, value) 159 160#define SMU_TCR_GEN_BIT(name, value) \ 161 SCU_GEN_BIT(SMU_TASK_CONTEXT_RANGE_##name) 162 163//***************************************************************************** 164 165#define SMU_COMPLETION_QUEUE_PUT_POINTER_SHIFT (0UL) 166#define SMU_COMPLETION_QUEUE_PUT_POINTER_MASK (0x00003FFFUL) 167#define SMU_COMPLETION_QUEUE_PUT_CYCLE_BIT_SHIFT (15UL) 168#define SMU_COMPLETION_QUEUE_PUT_CYCLE_BIT_MASK (0x00008000UL) 169#define SMU_COMPLETION_QUEUE_PUT_EVENT_POINTER_SHIFT (16UL) 170#define SMU_COMPLETION_QUEUE_PUT_EVENT_POINTER_MASK (0x03FF0000UL) 171#define SMU_COMPLETION_QUEUE_PUT_EVENT_CYCLE_BIT_SHIFT (26UL) 172#define SMU_COMPLETION_QUEUE_PUT_EVENT_CYCLE_BIT_MASK (0x04000000UL) 173#define SMU_COMPLETION_QUEUE_PUT_RESERVED_MASK (0xF8004000UL) 174 175#define SMU_CQPR_GEN_VAL(name, value) \ 176 SCU_GEN_VALUE(SMU_COMPLETION_QUEUE_PUT_##name, value) 177 178#define SMU_CQPR_GEN_BIT(name) \ 179 SCU_GEN_BIT(SMU_COMPLETION_QUEUE_PUT_##name) 180 181//***************************************************************************** 182 183#define SMU_COMPLETION_QUEUE_GET_POINTER_SHIFT (0UL) 184#define SMU_COMPLETION_QUEUE_GET_POINTER_MASK (0x00003FFFUL) 185#define SMU_COMPLETION_QUEUE_GET_CYCLE_BIT_SHIFT (15UL) 186#define SMU_COMPLETION_QUEUE_GET_CYCLE_BIT_MASK (0x00008000UL) 187#define SMU_COMPLETION_QUEUE_GET_EVENT_POINTER_SHIFT (16UL) 188#define SMU_COMPLETION_QUEUE_GET_EVENT_POINTER_MASK (0x03FF0000UL) 189#define SMU_COMPLETION_QUEUE_GET_EVENT_CYCLE_BIT_SHIFT (26UL) 190#define SMU_COMPLETION_QUEUE_GET_EVENT_CYCLE_BIT_MASK (0x04000000UL) 191#define SMU_COMPLETION_QUEUE_GET_ENABLE_SHIFT (30UL) 192#define SMU_COMPLETION_QUEUE_GET_ENABLE_MASK (0x40000000UL) 193#define SMU_COMPLETION_QUEUE_GET_EVENT_ENABLE_SHIFT (31UL) 194#define SMU_COMPLETION_QUEUE_GET_EVENT_ENABLE_MASK (0x80000000UL) 195#define SMU_COMPLETION_QUEUE_GET_RESERVED_MASK (0x38004000UL) 196 197#define SMU_CQGR_GEN_VAL(name, value) \ 198 SCU_GEN_VALUE(SMU_COMPLETION_QUEUE_GET_##name, value) 199 200#define SMU_CQGR_GEN_BIT(name) \ 201 SCU_GEN_BIT(SMU_COMPLETION_QUEUE_GET_##name) 202 203#define SMU_CQGR_CYCLE_BIT \ 204 SMU_CQGR_GEN_BIT(CYCLE_BIT) 205 206#define SMU_CQGR_EVENT_CYCLE_BIT \ 207 SMU_CQGR_GEN_BIT(EVENT_CYCLE_BIT) 208 209#define SMU_CQGR_GET_POINTER_SET(value) \ 210 SMU_CQGR_GEN_VAL(POINTER, value) 211 212 213//***************************************************************************** 214#define SMU_COMPLETION_QUEUE_CONTROL_QUEUE_LIMIT_SHIFT (0UL) 215#define SMU_COMPLETION_QUEUE_CONTROL_QUEUE_LIMIT_MASK (0x00003FFFUL) 216#define SMU_COMPLETION_QUEUE_CONTROL_EVENT_LIMIT_SHIFT (16UL) 217#define SMU_COMPLETION_QUEUE_CONTROL_EVENT_LIMIT_MASK (0x03FF0000UL) 218#define SMU_COMPLETION_QUEUE_CONTROL_RESERVED_MASK (0xFC00C000UL) 219 220#define SMU_CQC_GEN_VAL(name, value) \ 221 SCU_GEN_VALUE(SMU_COMPLETION_QUEUE_CONTROL_##name, value) 222 223#define SMU_CQC_QUEUE_LIMIT_SET(value) \ 224 SMU_CQC_GEN_VAL(QUEUE_LIMIT, value) 225 226#define SMU_CQC_EVENT_LIMIT_SET(value) \ 227 SMU_CQC_GEN_VAL(EVENT_LIMIT, value) 228 229 230//***************************************************************************** 231#define SMU_DEVICE_CONTEXT_CAPACITY_MAX_TC_SHIFT (0UL) 232#define SMU_DEVICE_CONTEXT_CAPACITY_MAX_TC_MASK (0x00000FFFUL) 233#define SMU_DEVICE_CONTEXT_CAPACITY_MAX_LP_SHIFT (12UL) 234#define SMU_DEVICE_CONTEXT_CAPACITY_MAX_LP_MASK (0x00007000UL) 235#define SMU_DEVICE_CONTEXT_CAPACITY_MAX_RNC_SHIFT (15UL) 236#define SMU_DEVICE_CONTEXT_CAPACITY_MAX_RNC_MASK (0x07FF8000UL) 237#define SMU_DEVICE_CONTEXT_CAPACITY_MAX_PEG_SHIFT (27UL) 238#define SMU_DEVICE_CONTEXT_CAPACITY_MAX_PEG_MASK (0x08000000UL) 239#define SMU_DEVICE_CONTEXT_CAPACITY_RESERVED_MASK (0xF0000000UL) 240 241#define SMU_DCC_GEN_VAL(name, value) \ 242 SCU_GEN_VALUE(SMU_DEVICE_CONTEXT_CAPACITY_##name, value) 243 244#define SMU_DCC_GET_MAX_PEG(value) \ 245 ( \ 246 ((U32)((value) & SMU_DEVICE_CONTEXT_CAPACITY_MAX_PEG_MASK)) \ 247 >> SMU_DEVICE_CONTEXT_CAPACITY_MAX_LP_SHIFT \ 248 ) 249 250#define SMU_DCC_GET_MAX_LP(value) \ 251 ( \ 252 ((U32)((value) & SMU_DEVICE_CONTEXT_CAPACITY_MAX_LP_MASK)) \ 253 >> SMU_DEVICE_CONTEXT_CAPACITY_MAX_LP_SHIFT \ 254 ) 255 256#define SMU_DCC_GET_MAX_TC(value) \ 257 ( \ 258 ((U32)((value) & SMU_DEVICE_CONTEXT_CAPACITY_MAX_TC_MASK)) \ 259 >> SMU_DEVICE_CONTEXT_CAPACITY_MAX_TC_SHIFT \ 260 ) 261 262#define SMU_DCC_GET_MAX_RNC(value) \ 263 ( \ 264 ((U32)((value) & SMU_DEVICE_CONTEXT_CAPACITY_MAX_RNC_MASK)) \ 265 >> SMU_DEVICE_CONTEXT_CAPACITY_MAX_RNC_SHIFT \ 266 ) 267 268//***************************************************************************** 269#define SMU_CLOCK_GATING_CONTROL_IDLE_ENABLE_SHIFT (0UL) 270#define SMU_CLOCK_GATING_CONTROL_IDLE_ENABLE_MASK (0x00000001UL) 271#define SMU_CLOCK_GATING_CONTROL_XCLK_ENABLE_SHIFT (1UL) 272#define SMU_CLOCK_GATING_CONTROL_XCLK_ENABLE_MASK (0x00000002UL) 273#define SMU_CLOCK_GATING_CONTROL_TXCLK_ENABLE_SHIFT (2UL) 274#define SMU_CLOCK_GATING_CONTROL_TXCLK_ENABLE_MASK (0x00000004UL) 275#define SMU_CLOCK_GATING_CONTROL_REGCLK_ENABLE_SHIFT (3UL) 276#define SMU_CLOCK_GATING_CONTROL_REGCLK_ENABLE_MASK (0x00000008UL) 277#define SMU_CLOCK_GATING_CONTROL_IDLE_TIMEOUT_SHIFT (16UL) 278#define SMU_CLOCK_GATING_CONTROL_IDLE_TIMEOUT_MASK (0x000F0000UL) 279#define SMU_CLOCK_GATING_CONTROL_FORCE_IDLE_SHIFT (31UL) 280#define SMU_CLOCK_GATING_CONTROL_FORCE_IDLE_MASK (0x80000000UL) 281#define SMU_CLOCK_GATING_CONTROL_RESERVED_MASK (0x7FF0FFF0UL) 282 283#define SMU_CGUCR_GEN_VAL(name, value) \ 284 SCU_GEN_VALUE(SMU_CLOCK_GATING_CONTROL_##name, value) 285 286#define SMU_CGUCR_GEN_BIT(name) \ 287 SCU_GEN_BIT(SMU_CLOCK_GATING_CONTROL_##name) 288 289// -------------------------------------------------------------------------- 290 291#define SMU_CONTROL_STATUS_TASK_CONTEXT_RANGE_ENABLE_SHIFT (0UL) 292#define SMU_CONTROL_STATUS_TASK_CONTEXT_RANGE_ENABLE_MASK (0x00000001UL) 293#define SMU_CONTROL_STATUS_COMPLETION_BYTE_SWAP_ENABLE_SHIFT (1UL) 294#define SMU_CONTROL_STATUS_COMPLETION_BYTE_SWAP_ENABLE_MASK (0x00000002UL) 295#define SMU_CONTROL_STATUS_CONTEXT_RAM_INIT_COMPLETED_SHIFT (16UL) 296#define SMU_CONTROL_STATUS_CONTEXT_RAM_INIT_COMPLETED_MASK (0x00010000UL) 297#define SMU_CONTROL_STATUS_SCHEDULER_RAM_INIT_COMPLETED_SHIFT (17UL) 298#define SMU_CONTROL_STATUS_SCHEDULER_RAM_INIT_COMPLETED_MASK (0x00020000UL) 299#define SMU_CONTROL_STATUS_RESERVED_MASK (0xFFFCFFFCUL) 300 301#define SMU_SMUCSR_GEN_BIT(name) \ 302 SCU_GEN_BIT(SMU_CONTROL_STATUS_##name) 303 304#define SMU_SMUCSR_SCHEDULER_RAM_INIT_COMPLETED \ 305 (SMU_SMUCSR_GEN_BIT(SCHEDULER_RAM_INIT_COMPLETED)) 306 307#define SMU_SMUCSR_CONTEXT_RAM_INIT_COMPLETED \ 308 (SMU_SMUCSR_GEN_BIT(CONTEXT_RAM_INIT_COMPLETED)) 309 310#define SCU_RAM_INIT_COMPLETED \ 311 ( \ 312 SMU_SMUCSR_CONTEXT_RAM_INIT_COMPLETED \ 313 | SMU_SMUCSR_SCHEDULER_RAM_INIT_COMPLETED \ 314 ) 315 316// -------------------------------------------------------------------------- 317 318#define SMU_SOFTRESET_CONTROL_RESET_PEG0_PE0_SHIFT (0UL) 319#define SMU_SOFTRESET_CONTROL_RESET_PEG0_PE0_MASK (0x00000001UL) 320#define SMU_SOFTRESET_CONTROL_RESET_PEG0_PE1_SHIFT (1UL) 321#define SMU_SOFTRESET_CONTROL_RESET_PEG0_PE1_MASK (0x00000002UL) 322#define SMU_SOFTRESET_CONTROL_RESET_PEG0_PE2_SHIFT (2UL) 323#define SMU_SOFTRESET_CONTROL_RESET_PEG0_PE2_MASK (0x00000004UL) 324#define SMU_SOFTRESET_CONTROL_RESET_PEG0_PE3_SHIFT (3UL) 325#define SMU_SOFTRESET_CONTROL_RESET_PEG0_PE3_MASK (0x00000008UL) 326#define SMU_SOFTRESET_CONTROL_RESET_PEG1_PE0_SHIFT (8UL) 327#define SMU_SOFTRESET_CONTROL_RESET_PEG1_PE0_MASK (0x00000100UL) 328#define SMU_SOFTRESET_CONTROL_RESET_PEG1_PE1_SHIFT (9UL) 329#define SMU_SOFTRESET_CONTROL_RESET_PEG1_PE1_MASK (0x00000200UL) 330#define SMU_SOFTRESET_CONTROL_RESET_PEG1_PE2_SHIFT (10UL) 331#define SMU_SOFTRESET_CONTROL_RESET_PEG1_PE2_MASK (0x00000400UL) 332#define SMU_SOFTRESET_CONTROL_RESET_PEG1_PE3_SHIFT (11UL) 333#define SMU_SOFTRESET_CONTROL_RESET_PEG1_PE3_MASK (0x00000800UL) 334 335#define SMU_RESET_PROTOCOL_ENGINE(peg, pe) \ 336 ((1UL << (pe)) << ((peg) * 8UL)) 337 338#define SMU_RESET_PEG_PROTOCOL_ENGINES(peg) \ 339 ( \ 340 SMU_RESET_PROTOCOL_ENGINE(peg, 0) \ 341 | SMU_RESET_PROTOCOL_ENGINE(peg, 1) \ 342 | SMU_RESET_PROTOCOL_ENGINE(peg, 2) \ 343 | SMU_RESET_PROTOCOL_ENGINE(peg, 3) \ 344 ) 345 346#define SMU_RESET_ALL_PROTOCOL_ENGINES() \ 347 ( \ 348 SMU_RESET_PEG_PROTOCOL_ENGINES(0) \ 349 | SMU_RESET_PEG_PROTOCOL_ENGINES(1) \ 350 ) 351 352#define SMU_SOFTRESET_CONTROL_RESET_WIDE_PORT_PEG0_LP0_SHIFT (16UL) 353#define SMU_SOFTRESET_CONTROL_RESET_WIDE_PORT_PEG0_LP0_MASK (0x00010000UL) 354#define SMU_SOFTRESET_CONTROL_RESET_WIDE_PORT_PEG0_LP2_SHIFT (17UL) 355#define SMU_SOFTRESET_CONTROL_RESET_WIDE_PORT_PEG0_LP2_MASK (0x00020000UL) 356#define SMU_SOFTRESET_CONTROL_RESET_WIDE_PORT_PEG1_LP0_SHIFT (18UL) 357#define SMU_SOFTRESET_CONTROL_RESET_WIDE_PORT_PEG1_LP0_MASK (0x00040000UL) 358#define SMU_SOFTRESET_CONTROL_RESET_WIDE_PORT_PEG1_LP2_SHIFT (19UL) 359#define SMU_SOFTRESET_CONTROL_RESET_WIDE_PORT_PEG1_LP2_MASK (0x00080000UL) 360 361#define SMU_RESET_WIDE_PORT_QUEUE(peg, wide_port) \ 362 ((1UL << ((wide_port) / 2)) << ((peg) * 2UL) << 16UL) 363 364#define SMU_SOFTRESET_CONTROL_RESET_PEG0_SHIFT (20UL) 365#define SMU_SOFTRESET_CONTROL_RESET_PEG0_MASK (0x00100000UL) 366#define SMU_SOFTRESET_CONTROL_RESET_PEG1_SHIFT (21UL) 367#define SMU_SOFTRESET_CONTROL_RESET_PEG1_MASK (0x00200000UL) 368#define SMU_SOFTRESET_CONTROL_RESET_SCU_SHIFT (22UL) 369#define SMU_SOFTRESET_CONTROL_RESET_SCU_MASK (0x00400000UL) 370 371// It seems to make sense that if you are going to reset the protocol 372// engine group that you would also reset all of the protocol engines 373#define SMU_RESET_PROTOCOL_ENGINE_GROUP(peg) \ 374 ( \ 375 (1UL << ((peg) + 20)) \ 376 | SMU_RESET_WIDE_PORT_QUEUE(peg, 0) \ 377 | SMU_RESET_WIDE_PORT_QUEUE(peg, 1) \ 378 | SMU_RESET_PEG_PROTOCOL_ENGINES(peg) \ 379 ) 380 381#define SMU_RESET_ALL_PROTOCOL_ENGINE_GROUPS() \ 382 ( \ 383 SMU_RESET_PROTOCOL_ENGINE_GROUP(0) \ 384 | SMU_RESET_PROTOCOL_ENGINE_GROUP(1) \ 385 ) 386 387#define SMU_RESET_SCU() (0xFFFFFFFF) 388 389 390 391//***************************************************************************** 392#define SMU_TASK_CONTEXT_ASSIGNMENT_STARTING_SHIFT (0UL) 393#define SMU_TASK_CONTEXT_ASSIGNMENT_STARTING_MASK (0x00000FFFUL) 394#define SMU_TASK_CONTEXT_ASSIGNMENT_ENDING_SHIFT (16UL) 395#define SMU_TASK_CONTEXT_ASSIGNMENT_ENDING_MASK (0x0FFF0000UL) 396#define SMU_TASK_CONTEXT_ASSIGNMENT_RANGE_CHECK_ENABLE_SHIFT (31UL) 397#define SMU_TASK_CONTEXT_ASSIGNMENT_RANGE_CHECK_ENABLE_MASK (0x80000000UL) 398#define SMU_TASK_CONTEXT_ASSIGNMENT_RESERVED_MASK (0x7000F000UL) 399 400#define SMU_TCA_GEN_VAL(name, value) \ 401 SCU_GEN_VALUE(SMU_TASK_CONTEXT_ASSIGNMENT_##name, value) 402 403#define SMU_TCA_GEN_BIT(name) \ 404 SCU_GEN_BIT(SMU_TASK_CONTEXT_ASSIGNMENT_##name) 405 406//***************************************************************************** 407#define SCU_SDMA_UNSOLICITED_FRAME_QUEUE_CONTROL_QUEUE_SIZE_SHIFT (0UL) 408#define SCU_SDMA_UNSOLICITED_FRAME_QUEUE_CONTROL_QUEUE_SIZE_MASK (0x00000FFFUL) 409#define SCU_SDMA_UNSOLICITED_FRAME_QUEUE_CONTROL_RESERVED_MASK (0xFFFFF000UL) 410 411#define SCU_UFQC_GEN_VAL(name, value) \ 412 SCU_GEN_VALUE(SCU_SDMA_UNSOLICITED_FRAME_QUEUE_CONTROL_##name, value) 413 414#define SCU_UFQC_QUEUE_SIZE_SET(value) \ 415 SCU_UFQC_GEN_VAL(QUEUE_SIZE, value) 416 417//***************************************************************************** 418#define SCU_SDMA_UNSOLICITED_FRAME_QUEUE_PUT_POINTER_SHIFT (0UL) 419#define SCU_SDMA_UNSOLICITED_FRAME_QUEUE_PUT_POINTER_MASK (0x00000FFFUL) 420#define SCU_SDMA_UNSOLICITED_FRAME_QUEUE_PUT_CYCLE_BIT_SHIFT (12UL) 421#define SCU_SDMA_UNSOLICITED_FRAME_QUEUE_PUT_CYCLE_BIT_MASK (0x00001000UL) 422#define SCU_SDMA_UNSOLICITED_FRAME_QUEUE_PUT_RESERVED_MASK (0xFFFFE000UL) 423 424#define SCU_UFQPP_GEN_VAL(name, value) \ 425 SCU_GEN_VALUE(SCU_SDMA_UNSOLICITED_FRAME_QUEUE_PUT_##name, value) 426 427#define SCU_UFQPP_GEN_BIT(name) \ 428 SCU_GEN_BIT(SCU_SDMA_UNSOLICITED_FRAME_QUEUE_PUT_##name) 429 430//***************************************************************************** 431//* SDMA Registers 432//***************************************************************************** 433#define SCU_SDMA_UNSOLICITED_FRAME_QUEUE_GET_POINTER_SHIFT (0UL) 434#define SCU_SDMA_UNSOLICITED_FRAME_QUEUE_GET_POINTER_MASK (0x00000FFFUL) 435#define SCU_SDMA_UNSOLICITED_FRAME_QUEUE_GET_CYCLE_BIT_SHIFT (12UL) 436#define SCU_SDMA_UNSOLICITED_FRAME_QUEUE_GET_CYCLE_BIT_MASK (12UL) 437#define SCU_SDMA_UNSOLICITED_FRAME_QUEUE_GET_ENABLE_BIT_SHIFT (31UL) 438#define SCU_SDMA_UNSOLICITED_FRAME_QUEUE_GET_ENABLE_BIT_MASK (0x80000000UL) 439#define SCU_SDMA_UNSOLICITED_FRAME_QUEUE_GET_RESERVED_MASK (0x7FFFE000UL) 440 441#define SCU_UFQGP_GEN_VAL(name, value) \ 442 SCU_GEN_VALUE(SCU_SDMA_UNSOLICITED_FRAME_QUEUE_GET_##name, value) 443 444#define SCU_UFQGP_GEN_BIT(name) \ 445 SCU_GEN_BIT(SCU_SDMA_UNSOLICITED_FRAME_QUEUE_GET_##name) 446 447#define SCU_UFQGP_CYCLE_BIT(value) \ 448 SCU_UFQGP_GEN_BIT(CYCLE_BIT, value) 449 450#define SCU_UFQGP_GET_POINTER(value) \ 451 SCU_UFQGP_GEN_VALUE(POINTER, value) 452 453#define SCU_UFQGP_ENABLE(value) \ 454 (SCU_UFQGP_GEN_BIT(ENABLE) | value) 455 456#define SCU_UFQGP_DISABLE(value) \ 457 (~SCU_UFQGP_GEN_BIT(ENABLE) & value) 458 459#define SCU_UFQGP_VALUE(bit, value) \ 460 (SCU_UFQGP_CYCLE_BIT(bit) | SCU_UFQGP_GET_POINTER(value)) 461 462//***************************************************************************** 463#define SCU_PDMA_CONFIGURATION_ADDRESS_MODIFIER_SHIFT (0UL) 464#define SCU_PDMA_CONFIGURATION_ADDRESS_MODIFIER_MASK (0x0000FFFFUL) 465#define SCU_PDMA_CONFIGURATION_PCI_RELAXED_ORDERING_ENABLE_SHIFT (16UL) 466#define SCU_PDMA_CONFIGURATION_PCI_RELAXED_ORDERING_ENABLE_MASK (0x00010000UL) 467#define SCU_PDMA_CONFIGURATION_PCI_NO_SNOOP_ENABLE_SHIFT (17UL) 468#define SCU_PDMA_CONFIGURATION_PCI_NO_SNOOP_ENABLE_MASK (0x00020000UL) 469#define SCU_PDMA_CONFIGURATION_BIG_ENDIAN_CONTROL_BYTE_SWAP_SHIFT (18UL) 470#define SCU_PDMA_CONFIGURATION_BIG_ENDIAN_CONTROL_BYTE_SWAP_MASK (0x00040000UL) 471#define SCU_PDMA_CONFIGURATION_BIG_ENDIAN_CONTROL_XPI_SGL_FETCH_SHIFT (19UL) 472#define SCU_PDMA_CONFIGURATION_BIG_ENDIAN_CONTROL_XPI_SGL_FETCH_MASK (0x00080000UL) 473#define SCU_PDMA_CONFIGURATION_BIG_ENDIAN_CONTROL_XPI_RX_HEADER_RAM_WRITE_SHIFT (20UL) 474#define SCU_PDMA_CONFIGURATION_BIG_ENDIAN_CONTROL_XPI_RX_HEADER_RAM_WRITE_MASK (0x00100000UL) 475#define SCU_PDMA_CONFIGURATION_BIG_ENDIAN_CONTROL_XPI_UF_ADDRESS_FETCH_SHIFT (21UL) 476#define SCU_PDMA_CONFIGURATION_BIG_ENDIAN_CONTROL_XPI_UF_ADDRESS_FETCH_MASK (0x00200000UL) 477#define SCU_PDMA_CONFIGURATION_ADDRESS_MODIFIER_SELECT_SHIFT (22UL) 478#define SCU_PDMA_CONFIGURATION_ADDRESS_MODIFIER_SELECT_MASK (0x00400000UL) 479#define SCU_PDMA_CONFIGURATION_RESERVED_MASK (0xFF800000UL) 480 481#define SCU_PDMACR_GEN_VALUE(name, value) \ 482 SCU_GEN_VALUE(SCU_PDMA_CONFIGURATION_##name, value) 483 484#define SCU_PDMACR_GEN_BIT(name) \ 485 SCU_GEN_BIT(SCU_PDMA_CONFIGURATION_##name) 486 487#define SCU_PDMACR_BE_GEN_BIT(name) \ 488 SCU_PCMACR_GEN_BIT(BIG_ENDIAN_CONTROL_##name) 489 490//***************************************************************************** 491#define SCU_CDMA_CONFIGURATION_PCI_RELAXED_ORDERING_ENABLE_SHIFT (8UL) 492#define SCU_CDMA_CONFIGURATION_PCI_RELAXED_ORDERING_ENABLE_MASK (0x00000100UL) 493 494#define SCU_CDMACR_GEN_BIT(name) \ 495 SCU_GEN_BIT(SCU_CDMA_CONFIGURATION_##name) 496 497//***************************************************************************** 498//* SCU Link Layer Registers 499//***************************************************************************** 500#define SCU_LINK_LAYER_SPEED_NEGOTIATION_TIMER_VALUES_TIMEOUT_SHIFT (0UL) 501#define SCU_LINK_LAYER_SPEED_NEGOTIATION_TIMER_VALUES_TIMEOUT_MASK (0x000000FFUL) 502#define SCU_LINK_LAYER_SPEED_NEGOTIATION_TIMER_VALUES_LOCK_TIME_SHIFT (8UL) 503#define SCU_LINK_LAYER_SPEED_NEGOTIATION_TIMER_VALUES_LOCK_TIME_MASK (0x0000FF00UL) 504#define SCU_LINK_LAYER_SPEED_NEGOTIATION_TIMER_VALUES_RATE_CHANGE_DELAY_SHIFT (16UL) 505#define SCU_LINK_LAYER_SPEED_NEGOTIATION_TIMER_VALUES_RATE_CHANGE_DELAY_MASK (0x00FF0000UL) 506#define SCU_LINK_LAYER_SPEED_NEGOTIATION_TIMER_VALUES_DWORD_SYNC_TIMEOUT_SHIFT (24UL) 507#define SCU_LINK_LAYER_SPEED_NEGOTIATION_TIMER_VALUES_DWORD_SYNC_TIMEOUT_MASK (0xFF000000UL) 508#define SCU_LINK_LAYER_SPEED_NECGOIATION_TIMER_VALUES_REQUIRED_MASK (0x00000000UL) 509#define SCU_LINK_LAYER_SPEED_NECGOIATION_TIMER_VALUES_DEFAULT_MASK (0x7D00676FUL) 510#define SCU_LINK_LAYER_SPEED_NECGOIATION_TIMER_VALUES_RESERVED_MASK (0x00FF0000UL) 511 512#define SCU_SAS_SPDTOV_GEN_VALUE(name, value) \ 513 SCU_GEN_VALUE(SCU_LINK_LAYER_SPEED_NEGOTIATION_TIMER_VALUES_##name, value) 514 515 516#define SCU_LINK_STATUS_DWORD_SYNC_AQUIRED_SHIFT (2UL) 517#define SCU_LINK_STATUS_DWORD_SYNC_AQUIRED_MASK (0x00000004UL) 518#define SCU_LINK_STATUS_TRANSMIT_PORT_SELECTION_DONE_SHIFT (4UL) 519#define SCU_LINK_STATUS_TRANSMIT_PORT_SELECTION_DONE_MASK (0x00000010UL) 520#define SCU_LINK_STATUS_RECEIVER_CREDIT_EXHAUSTED_SHIFT (5UL) 521#define SCU_LINK_STATUS_RECEIVER_CREDIT_EXHAUSTED_MASK (0x00000020UL) 522#define SCU_LINK_STATUS_RESERVED_MASK (0xFFFFFFCDUL) 523 524#define SCU_SAS_LLSTA_GEN_BIT(name) \ 525 SCU_GEN_BIT(SCU_LINK_STATUS_##name) 526 527 528// TODO: Where is the SATA_PSELTOV register? 529 530//***************************************************************************** 531//* SCU SAS Maximum Arbitration Wait Time Timeout Register 532//***************************************************************************** 533#define SCU_SAS_MAX_ARBITRATION_WAIT_TIME_TIMEOUT_VALUE_SHIFT (0UL) 534#define SCU_SAS_MAX_ARBITRATION_WAIT_TIME_TIMEOUT_VALUE_MASK (0x00007FFFUL) 535#define SCU_SAS_MAX_ARBITRATION_WAIT_TIME_TIMEOUT_SCALE_SHIFT (15UL) 536#define SCU_SAS_MAX_ARBITRATION_WAIT_TIME_TIMEOUT_SCALE_MASK (0x00008000UL) 537 538#define SCU_SAS_MAWTTOV_GEN_VALUE(name, value) \ 539 SCU_GEN_VALUE(SCU_SAS_MAX_ARBITRATION_WAIT_TIME_TIMEOUT_##name, value) 540 541#define SCU_SAS_MAWTTOV_GEN_BIT(name) \ 542 SCU_GEN_BIT(SCU_SAS_MAX_ARBITRATION_WAIT_TIME_TIMEOUT_##name) 543 544 545// TODO: Where is the SAS_LNKTOV regsiter? 546// TODO: Where is the SAS_PHYTOV register? 547 548#define SCU_SAS_TRANSMIT_IDENTIFICATION_SMP_TARGET_SHIFT (1UL) 549#define SCU_SAS_TRANSMIT_IDENTIFICATION_SMP_TARGET_MASK (0x00000002UL) 550#define SCU_SAS_TRANSMIT_IDENTIFICATION_STP_TARGET_SHIFT (2UL) 551#define SCU_SAS_TRANSMIT_IDENTIFICATION_STP_TARGET_MASK (0x00000004UL) 552#define SCU_SAS_TRANSMIT_IDENTIFICATION_SSP_TARGET_SHIFT (3UL) 553#define SCU_SAS_TRANSMIT_IDENTIFICATION_SSP_TARGET_MASK (0x00000008UL) 554#define SCU_SAS_TRANSMIT_IDENTIFICATION_DA_SATA_HOST_SHIFT (8UL) 555#define SCU_SAS_TRANSMIT_IDENTIFICATION_DA_SATA_HOST_MASK (0x00000100UL) 556#define SCU_SAS_TRANSMIT_IDENTIFICATION_SMP_INITIATOR_SHIFT (9UL) 557#define SCU_SAS_TRANSMIT_IDENTIFICATION_SMP_INITIATOR_MASK (0x00000200UL) 558#define SCU_SAS_TRANSMIT_IDENTIFICATION_STP_INITIATOR_SHIFT (10UL) 559#define SCU_SAS_TRANSMIT_IDENTIFICATION_STP_INITIATOR_MASK (0x00000400UL) 560#define SCU_SAS_TRANSMIT_IDENTIFICATION_SSP_INITIATOR_SHIFT (11UL) 561#define SCU_SAS_TRANSMIT_IDENTIFICATION_SSP_INITIATOR_MASK (0x00000800UL) 562#define SCU_SAS_TRANSMIT_IDENTIFICATION_REASON_CODE_SHIFT (16UL) 563#define SCU_SAS_TRANSMIT_IDENTIFICATION_REASON_CODE_MASK (0x000F0000UL) 564#define SCU_SAS_TRANSMIT_IDENTIFICATION_ADDRESS_FRAME_TYPE_SHIFT (24UL) 565#define SCU_SAS_TRANSMIT_IDENTIFICATION_ADDRESS_FRAME_TYPE_MASK (0x0F000000UL) 566#define SCU_SAS_TRANSMIT_IDENTIFICATION_DEVICE_TYPE_SHIFT (28UL) 567#define SCU_SAS_TRANSMIT_IDENTIFICATION_DEVICE_TYPE_MASK (0x70000000UL) 568#define SCU_SAS_TRANSMIT_IDENTIFICATION_RESERVED_MASK (0x80F0F1F1UL) 569 570#define SCU_SAS_TIID_GEN_VAL(name, value) \ 571 SCU_GEN_VALUE(SCU_SAS_TRANSMIT_IDENTIFICATION_##name, value) 572 573#define SCU_SAS_TIID_GEN_BIT(name) \ 574 SCU_GEN_BIT(SCU_SAS_TRANSMIT_IDENTIFICATION_##name) 575 576// SAS Identify Frame PHY Identifier Register 577#define SCU_LINK_LAYER_IDENTIFY_FRAME_PHY_IDENTIFIER_BREAK_REPLY_CAPABLE_SHIFT (16UL) 578#define SCU_LINK_LAYER_IDENTIFY_FRAME_PHY_IDENTIFIER_BREAK_REPLY_CAPABLE_MASK (0x00010000UL) 579#define SCU_LINK_LAYER_IDENTIFY_FRAME_PHY_IDENTIFIER_REQUESTED_INSIDE_ZPSDS_SHIFT (17UL) 580#define SCU_LINK_LAYER_IDENTIFY_FRAME_PHY_IDENTIFIER_REQUESTED_INSIDE_ZPSDS_MASK (0x00020000UL) 581#define SCU_LINK_LAYER_IDENTIFY_FRAME_PHY_IDENTIFIER_INSIDE_ZPSDS_PERSISTENT_SHIFT (18UL) 582#define SCU_LINK_LAYER_IDENTIFY_FRAME_PHY_IDENTIFIER_INSIDE_ZPSDS_PERSISTENT_MASK (0x00040000UL) 583#define SCU_LINK_LAYER_IDENTIFY_FRAME_PHY_IDENTIFIER_ID_SHIFT (24UL) 584#define SCU_LINK_LAYER_IDENTIFY_FRAME_PHY_IDENTIFIER_ID_MASK (0xFF000000UL) 585#define SCU_LINK_LAYER_IDENTIFY_FRAME_PHY_IDENTIFIER_RESERVED_MASK (0x00F800FFUL) 586 587#define SCU_SAS_TIPID_GEN_VALUE(name, value) \ 588 SCU_GEN_VALUE(SCU_LINK_LAYER_IDENTIFY_FRAME_PHY_IDENTIFIER_##name, value) 589 590#define SCU_SAS_TIPID_GEN_BIT(name) \ 591 SCU_GEN_BIT(SCU_LINK_LAYER_IDENTIFY_FRAME_PHY_IDENTIFIER_##name) 592 593 594#define SCU_SAS_PHY_CONFIGURATION_TX_PARITY_CHECK_SHIFT (4UL) 595#define SCU_SAS_PHY_CONFIGURATION_TX_PARITY_CHECK_MASK (0x00000010UL) 596#define SCU_SAS_PHY_CONFIGURATION_TX_BAD_CRC_SHIFT (6UL) 597#define SCU_SAS_PHY_CONFIGURATION_TX_BAD_CRC_MASK (0x00000040UL) 598#define SCU_SAS_PHY_CONFIGURATION_DISABLE_SCRAMBLER_SHIFT (7UL) 599#define SCU_SAS_PHY_CONFIGURATION_DISABLE_SCRAMBLER_MASK (0x00000080UL) 600#define SCU_SAS_PHY_CONFIGURATION_DISABLE_DESCRAMBLER_SHIFT (8UL) 601#define SCU_SAS_PHY_CONFIGURATION_DISABLE_DESCRAMBLER_MASK (0x00000100UL) 602#define SCU_SAS_PHY_CONFIGURATION_DISABLE_CREDIT_INSERTION_SHIFT (9UL) 603#define SCU_SAS_PHY_CONFIGURATION_DISABLE_CREDIT_INSERTION_MASK (0x00000200UL) 604#define SCU_SAS_PHY_CONFIGURATION_SUSPEND_PROTOCOL_ENGINE_SHIFT (11UL) 605#define SCU_SAS_PHY_CONFIGURATION_SUSPEND_PROTOCOL_ENGINE_MASK (0x00000800UL) 606#define SCU_SAS_PHY_CONFIGURATION_SATA_SPINUP_HOLD_SHIFT (12UL) 607#define SCU_SAS_PHY_CONFIGURATION_SATA_SPINUP_HOLD_MASK (0x00001000UL) 608#define SCU_SAS_PHY_CONFIGURATION_TRANSMIT_PORT_SELECTION_SIGNAL_SHIFT (13UL) 609#define SCU_SAS_PHY_CONFIGURATION_TRANSMIT_PORT_SELECTION_SIGNAL_MASK (0x00002000UL) 610#define SCU_SAS_PHY_CONFIGURATION_HARD_RESET_SHIFT (14UL) 611#define SCU_SAS_PHY_CONFIGURATION_HARD_RESET_MASK (0x00004000UL) 612#define SCU_SAS_PHY_CONFIGURATION_OOB_ENABLE_SHIFT (15UL) 613#define SCU_SAS_PHY_CONFIGURATION_OOB_ENABLE_MASK (0x00008000UL) 614#define SCU_SAS_PHY_CONFIGURATION_ENABLE_FRAME_TX_INSERT_ALIGN_SHIFT (23UL) 615#define SCU_SAS_PHY_CONFIGURATION_ENABLE_FRAME_TX_INSERT_ALIGN_MASK (0x00800000UL) 616#define SCU_SAS_PHY_CONFIGURATION_FORWARD_IDENTIFY_FRAME_SHIFT (27UL) 617#define SCU_SAS_PHY_CONFIGURATION_FORWARD_IDENTIFY_FRAME_MASK (0x08000000UL) 618#define SCU_SAS_PHY_CONFIGURATION_DISABLE_BYTE_TRANSPOSE_STP_FRAME_SHIFT (28UL) 619#define SCU_SAS_PHY_CONFIGURATION_DISABLE_BYTE_TRANSPOSE_STP_FRAME_MASK (0x10000000UL) 620#define SCU_SAS_PHY_CONFIGURATION_OOB_RESET_SHIFT (29UL) 621#define SCU_SAS_PHY_CONFIGURATION_OOB_RESET_MASK (0x20000000UL) 622#define SCU_SAS_PHY_CONFIGURATION_THREE_IAF_ENABLE_SHIFT (30UL) 623#define SCU_SAS_PHY_CONFIGURATION_THREE_IAF_ENABLE_MASK (0x40000000UL) 624#define SCU_SAS_PHY_CONFIGURATION_OOB_ALIGN0_ENABLE_SHIFT (31UL) 625#define SCU_SAS_PHY_CONFIGURATION_OOB_ALIGN0_ENABLE_MASK (0x80000000UL) 626#define SCU_SAS_PHY_CONFIGURATION_REQUIRED_MASK (0x0100000FUL) 627#define SCU_SAS_PHY_CONFIGURATION_DEFAULT_MASK (0x4180100FUL) 628#define SCU_SAS_PHY_CONFIGURATION_RESERVED_MASK (0x00000000UL) 629 630#define SCU_SAS_PCFG_GEN_BIT(name) \ 631 SCU_GEN_BIT(SCU_SAS_PHY_CONFIGURATION_##name) 632 633#define SCU_LINK_LAYER_ALIGN_INSERTION_FREQUENCY_GENERAL_SHIFT (0UL) 634#define SCU_LINK_LAYER_ALIGN_INSERTION_FREQUENCY_GENERAL_MASK (0x000007FFUL) 635#define SCU_LINK_LAYER_ALIGN_INSERTION_FREQUENCY_CONNECTED_SHIFT (16UL) 636#define SCU_LINK_LAYER_ALIGN_INSERTION_FREQUENCY_CONNECTED_MASK (0x00ff0000UL) 637 638#define SCU_ALIGN_INSERTION_FREQUENCY_GEN_VAL(name, value) \ 639 SCU_GEN_VALUE(SCU_LINK_LAYER_ALIGN_INSERTION_FREQUENCY_##name, value) 640 641#define SCU_LINK_LAYER_ENABLE_SPINUP_CONTROL_COUNT_SHIFT (0UL) 642#define SCU_LINK_LAYER_ENABLE_SPINUP_CONTROL_COUNT_MASK (0x0003FFFFUL) 643#define SCU_LINK_LAYER_ENABLE_SPINUP_CONTROL_ENABLE_SHIFT (31UL) 644#define SCU_LINK_LAYER_ENABLE_SPINUP_CONTROL_ENABLE_MASK (0x80000000UL) 645#define SCU_LINK_LAYER_ENABLE_SPINUP_CONTROL_RESERVED_MASK (0x7FFC0000UL) 646 647#define SCU_ENSPINUP_GEN_VAL(name, value) \ 648 SCU_GEN_VALUE(SCU_LINK_LAYER_ENABLE_SPINUP_CONTROL_##name, value) 649 650#define SCU_ENSPINUP_GEN_BIT(name) \ 651 SCU_GEN_BIT(SCU_LINK_LAYER_ENABLE_SPINUP_CONTROL_##name) 652 653 654#define SCU_LINK_LAYER_PHY_CAPABILITIES_TXSSCTYPE_SHIFT (1UL) 655#define SCU_LINK_LAYER_PHY_CAPABILITIES_TXSSCTYPE_MASK (0x00000002UL) 656#define SCU_LINK_LAYER_PHY_CAPABILITIES_RLLRATE_SHIFT (4UL) 657#define SCU_LINK_LAYER_PHY_CAPABILITIES_RLLRATE_MASK (0x000000F0UL) 658#define SCU_LINK_LAYER_PHY_CAPABILITIES_SWO15GBPS_SHIFT (8UL) 659#define SCU_LINK_LAYER_PHY_CAPABILITIES_SWO15GBPS_MASK (0x00000100UL) 660#define SCU_LINK_LAYER_PHY_CAPABILITIES_SW15GBPS_SHIFT (9UL) 661#define SCU_LINK_LAYER_PHY_CAPABILITIES_SW15GBPS_MASK (0x00000201UL) 662#define SCU_LINK_LAYER_PHY_CAPABILITIES_SWO30GBPS_SHIFT (10UL) 663#define SCU_LINK_LAYER_PHY_CAPABILITIES_SWO30GBPS_MASK (0x00000401UL) 664#define SCU_LINK_LAYER_PHY_CAPABILITIES_SW30GBPS_SHIFT (11UL) 665#define SCU_LINK_LAYER_PHY_CAPABILITIES_SW30GBPS_MASK (0x00000801UL) 666#define SCU_LINK_LAYER_PHY_CAPABILITIES_SWO60GBPS_SHIFT (12UL) 667#define SCU_LINK_LAYER_PHY_CAPABILITIES_SWO60GBPS_MASK (0x00001001UL) 668#define SCU_LINK_LAYER_PHY_CAPABILITIES_SW60GBPS_SHIFT (13UL) 669#define SCU_LINK_LAYER_PHY_CAPABILITIES_SW60GBPS_MASK (0x00002001UL) 670#define SCU_LINK_LAYER_PHY_CAPABILITIES_EVEN_PARITY_SHIFT (31UL) 671#define SCU_LINK_LAYER_PHY_CAPABILITIES_EVEN_PARITY_MASK (0x80000000UL) 672#define SCU_LINK_LAYER_PHY_CAPABILITIES_DEFAULT_MASK (0x00003F01UL) 673#define SCU_LINK_LAYER_PHY_CAPABILITIES_REQUIRED_MASK (0x00000001UL) 674#define SCU_LINK_LAYER_PHY_CAPABILITIES_RESERVED_MASK (0x7FFFC00DUL) 675 676#define SCU_SAS_PHYCAP_GEN_VAL(name, value) \ 677 SCU_GEN_VALUE(SCU_LINK_LAYER_PHY_CAPABILITIES_##name, value) 678 679#define SCU_SAS_PHYCAP_GEN_BIT(name) \ 680 SCU_GEN_BIT(SCU_LINK_LAYER_PHY_CAPABILITIES_##name) 681 682 683#define SCU_LINK_LAYER_PHY_SOURCE_ZONE_GROUP_CONTROL_VIRTUAL_EXPANDER_PHY_ZONE_GROUP_SHIFT (0UL) 684#define SCU_LINK_LAYER_PHY_SOURCE_ZONE_GROUP_CONTROL_VIRTUAL_EXPANDER_PHY_ZONE_GROUP_MASK (0x000000FFUL) 685#define SCU_LINK_LAYER_PHY_SOURCE_ZONE_GROUP_CONTROL_INSIDE_SOURCE_ZONE_GROUP_SHIFT (31UL) 686#define SCU_LINK_LAYER_PHY_SOURCE_ZONE_GROUP_CONTROL_INSIDE_SOURCE_ZONE_GROUP_MASK (0x80000000UL) 687#define SCU_LINK_LAYER_PHY_SOURCE_ZONE_GROUP_CONTROL_RESERVED_MASK (0x7FFFFF00UL) 688 689#define SCU_PSZGCR_GEN_VAL(name, value) \ 690 SCU_GEN_VALUE(SCU_LINK_LAYER_PHY_SOURCE_ZONE_GROUP_CONTROL_##name, value) 691 692#define SCU_PSZGCR_GEN_BIT(name) \ 693 SCU_GEN_BIT(SCU_LINK_LAYER_PHY_SOURCE_ZONE_GROUP_CONTROL_##name) 694 695#define SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_ZONE0_LOCKED_SHIFT (1UL) 696#define SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_ZONE0_LOCKED_MASK (0x00000002UL) 697#define SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_ZONE0_UPDATING_SHIFT (2UL) 698#define SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_ZONE0_UPDATING_MASK (0x00000004UL) 699#define SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_ZONE1_LOCKED_SHIFT (4UL) 700#define SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_ZONE1_LOCKED_MASK (0x00000010UL) 701#define SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_ZONE1_UPDATING_SHIFT (5UL) 702#define SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_ZONE1_UPDATING_MASK (0x00000020UL) 703#define SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_ZPT_ASSOCIATION_PE0_SHIFT (16UL) 704#define SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_ZPT_ASSOCIATION_PE0_MASK (0x00030000UL) 705#define SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_AIP_ENABLE_PE0_SHIFT (19UL) 706#define SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_AIP_ENABLE_PE0_MASK (0x00080000UL) 707#define SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_ZPT_ASSOCIATION_PE1_SHIFT (20UL) 708#define SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_ZPT_ASSOCIATION_PE1_MASK (0x00300000UL) 709#define SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_AIP_ENABLE_PE1_SHIFT (23UL) 710#define SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_AIP_ENABLE_PE1_MASK (0x00800000UL) 711#define SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_ZPT_ASSOCIATION_PE2_SHIFT (24UL) 712#define SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_ZPT_ASSOCIATION_PE2_MASK (0x03000000UL) 713#define SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_AIP_ENABLE_PE2_SHIFT (27UL) 714#define SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_AIP_ENABLE_PE2_MASK (0x08000000UL) 715#define SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_ZPT_ASSOCIATION_PE3_SHIFT (28UL) 716#define SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_ZPT_ASSOCIATION_PE3_MASK (0x30000000UL) 717#define SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_AIP_ENABLE_PE3_SHIFT (31UL) 718#define SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_AIP_ENABLE_PE3_MASK (0x80000000UL) 719#define SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_RESERVED_MASK (0x4444FFC9UL) 720 721#define SCU_PEG_SCUVZECR_GEN_VAL(name, val) \ 722 SCU_GEN_VALUE(SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_##name, val) 723 724#define SCU_PEG_SCUVZECR_GEN_BIT(name) \ 725 SCU_GEN_BIT(SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_##name) 726 727 728//***************************************************************************** 729//* Port Task Scheduler registers shift and mask values 730//***************************************************************************** 731#define SCU_PTSG_CONTROL_IT_NEXUS_TIMEOUT_SHIFT (0UL) 732#define SCU_PTSG_CONTROL_IT_NEXUS_TIMEOUT_MASK (0x0000FFFFUL) 733#define SCU_PTSG_CONTROL_TASK_TIMEOUT_SHIFT (16UL) 734#define SCU_PTSG_CONTROL_TASK_TIMEOUT_MASK (0x00FF0000UL) 735#define SCU_PTSG_CONTROL_PTSG_ENABLE_SHIFT (24UL) 736#define SCU_PTSG_CONTROL_PTSG_ENABLE_MASK (0x01000000UL) 737#define SCU_PTSG_CONTROL_ETM_ENABLE_SHIFT (25UL) 738#define SCU_PTSG_CONTROL_ETM_ENABLE_MASK (0x02000000UL) 739#define SCU_PTSG_CONTROL_DEFAULT_MASK (0x00020002UL) 740#define SCU_PTSG_CONTROL_REQUIRED_MASK (0x00000000UL) 741#define SCU_PTSG_CONTROL_RESERVED_MASK (0xFC000000UL) 742 743#define SCU_PTSGCR_GEN_VAL(name, val) \ 744 SCU_GEN_VALUE(SCU_PTSG_CONTROL_##name, val) 745 746#define SCU_PTSGCR_GEN_BIT(name) \ 747 SCU_GEN_BIT(SCU_PTSG_CONTROL_##name) 748 749 750//***************************************************************************** 751#define SCU_PTSG_REAL_TIME_CLOCK_SHIFT (0UL) 752#define SCU_PTSG_REAL_TIME_CLOCK_MASK (0x0000FFFFUL) 753#define SCU_PTSG_REAL_TIME_CLOCK_RESERVED_MASK (0xFFFF0000UL) 754 755#define SCU_RTCR_GEN_VAL(name, val) \ 756 SCU_GEN_VALUE(SCU_PTSG_##name, val) 757 758 759#define SCU_PTSG_REAL_TIME_CLOCK_CONTROL_PRESCALER_VALUE_SHIFT (0UL) 760#define SCU_PTSG_REAL_TIME_CLOCK_CONTROL_PRESCALER_VALUE_MASK (0x00FFFFFFUL) 761#define SCU_PTSG_REAL_TIME_CLOCK_CONTROL_RESERVED_MASK (0xFF000000UL) 762 763#define SCU_RTCCR_GEN_VAL(name, val) \ 764 SCU_GEN_VALUE(SCU_PTSG_REAL_TIME_CLOCK_CONTROL_##name, val) 765 766 767#define SCU_PTSG_PORT_TASK_SCHEDULER_CONTROL_SUSPEND_SHIFT (0UL) 768#define SCU_PTSG_PORT_TASK_SCHEDULER_CONTROL_SUSPEND_MASK (0x00000001UL) 769#define SCU_PTSG_PORT_TASK_SCHEDULER_CONTROL_ENABLE_SHIFT (1UL) 770#define SCU_PTSG_PORT_TASK_SCHEDULER_CONTROL_ENABLE_MASK (0x00000002UL) 771#define SCU_PTSG_PORT_TASK_SCHEDULER_CONTROL_RESERVED_MASK (0xFFFFFFFCUL) 772 773#define SCU_PTSxCR_GEN_BIT(name) \ 774 SCU_GEN_BIT(SCU_PTSG_PORT_TASK_SCHEDULER_CONTROL_##name) 775 776 777#define SCU_PTSG_PORT_TASK_SCHEDULER_STATUS_NEXT_RN_VALID_SHIFT (0UL) 778#define SCU_PTSG_PORT_TASK_SCHEDULER_STATUS_NEXT_RN_VALID_MASK (0x00000001UL) 779#define SCU_PTSG_PORT_TASK_SCHEDULER_STATUS_ACTIVE_RNSC_LIST_VALID_SHIFT (1UL) 780#define SCU_PTSG_PORT_TASK_SCHEDULER_STATUS_ACTIVE_RNSC_LIST_VALID_MASK (0x00000002UL) 781#define SCU_PTSG_PORT_TASK_SCHEDULER_STATUS_PTS_SUSPENDED_SHIFT (2UL) 782#define SCU_PTSG_PORT_TASK_SCHEDULER_STATUS_PTS_SUSPENDED_MASK (0x00000004UL) 783#define SCU_PTSG_PORT_TASK_SCHEDULER_STATUS_RESERVED_MASK (0xFFFFFFF8UL) 784 785#define SCU_PTSxSR_GEN_BIT(name) \ 786 SCU_GEN_BIT(SCU_PTSG_PORT_TASK_SCHEDULER_STATUS_##name) 787 788 789//***************************************************************************** 790//* SGPIO Register shift and mask values 791//***************************************************************************** 792#define SCU_SGPIO_CONTROL_SGPIO_ENABLE_SHIFT (0UL) 793#define SCU_SGPIO_CONTROL_SGPIO_ENABLE_MASK (0x00000001UL) 794#define SCU_SGPIO_CONTROL_SGPIO_SERIAL_CLOCK_SELECT_SHIFT (1UL) 795#define SCU_SGPIO_CONTROL_SGPIO_SERIAL_CLOCK_SELECT_MASK (0x00000002UL) 796#define SCU_SGPIO_CONTROL_SGPIO_SERIAL_SHIFT_WIDTH_SELECT_SHIFT (2UL) 797#define SCU_SGPIO_CONTROL_SGPIO_SERIAL_SHIFT_WIDTH_SELECT_MASK (0x00000004UL) 798#define SCU_SGPIO_CONTROL_SGPIO_TEST_BIT_SHIFT (15UL) 799#define SCU_SGPIO_CONTROL_SGPIO_TEST_BIT_MASK (0x00008000UL) 800#define SCU_SGPIO_CONTROL_SGPIO_RESERVED_MASK (0xFFFF7FF8UL) 801 802#define SCU_SGICRx_GEN_BIT(name) \ 803 SCU_GEN_BIT(SCU_SGPIO_CONTROL_SGPIO_##name) 804 805#define SCU_SGPIO_PROGRAMMABLE_BLINK_REGISTER_R0_SHIFT (0UL) 806#define SCU_SGPIO_PROGRAMMABLE_BLINK_REGISTER_R0_MASK (0x0000000FUL) 807#define SCU_SGPIO_PROGRAMMABLE_BLINK_REGISTER_R1_SHIFT (4UL) 808#define SCU_SGPIO_PROGRAMMABLE_BLINK_REGISTER_R1_MASK (0x000000F0UL) 809#define SCU_SGPIO_PROGRAMMABLE_BLINK_REGISTER_R2_SHIFT (8UL) 810#define SCU_SGPIO_PROGRAMMABLE_BLINK_REGISTER_R2_MASK (0x00000F00UL) 811#define SCU_SGPIO_PROGRAMMABLE_BLINK_REGISTER_R3_SHIFT (12UL) 812#define SCU_SGPIO_PROGRAMMABLE_BLINK_REGISTER_R3_MASK (0x0000F000UL) 813#define SCU_SGPIO_PROGRAMMABLE_BLINK_REGISTER_RESERVED_MASK (0xFFFF0000UL) 814 815#define SCU_SGPBRx_GEN_VAL(name, valueUL) \ 816 SCU_GEN_VALUE(SCU_SGPIO_PROGRAMMABLE_BLINK_REGISTER_##name, value) 817 818#define SCU_SGPIO_START_DRIVE_LOWER_R0_SHIFT (0UL) 819#define SCU_SGPIO_START_DRIVE_LOWER_R0_MASK (0x00000003UL) 820#define SCU_SGPIO_START_DRIVE_LOWER_R1_SHIFT (4UL) 821#define SCU_SGPIO_START_DRIVE_LOWER_R1_MASK (0x00000030UL) 822#define SCU_SGPIO_START_DRIVE_LOWER_R2_SHIFT (8UL) 823#define SCU_SGPIO_START_DRIVE_LOWER_R2_MASK (0x00000300UL) 824#define SCU_SGPIO_START_DRIVE_LOWER_R3_SHIFT (12UL) 825#define SCU_SGPIO_START_DRIVE_LOWER_R3_MASK (0x00003000UL) 826#define SCU_SGPIO_START_DRIVE_LOWER_RESERVED_MASK (0xFFFF8888UL) 827 828#define SCU_SGSDLRx_GEN_VAL(name, value) \ 829 SCU_GEN_VALUE(SCU_SGPIO_START_DRIVE_LOWER_##name, value) 830 831#define SCU_SGPIO_START_DRIVE_UPPER_R0_SHIFT (0UL) 832#define SCU_SGPIO_START_DRIVE_UPPER_R0_MASK (0x00000003UL) 833#define SCU_SGPIO_START_DRIVE_UPPER_R1_SHIFT (4UL) 834#define SCU_SGPIO_START_DRIVE_UPPER_R1_MASK (0x00000030UL) 835#define SCU_SGPIO_START_DRIVE_UPPER_R2_SHIFT (8UL) 836#define SCU_SGPIO_START_DRIVE_UPPER_R2_MASK (0x00000300UL) 837#define SCU_SGPIO_START_DRIVE_UPPER_R3_SHIFT (12UL) 838#define SCU_SGPIO_START_DRIVE_UPPER_R3_MASK (0x00003000UL) 839#define SCU_SGPIO_START_DRIVE_UPPER_RESERVED_MASK (0xFFFF8888UL) 840 841#define SCU_SGSDURx_GEN_VAL(name, value) \ 842 SCU_GEN_VALUE(SCU_SGPIO_START_DRIVE_LOWER_##name, value) 843 844#define SCU_SGPIO_SERIAL_INPUT_DATA_LOWER_D0_SHIFT (0UL) 845#define SCU_SGPIO_SERIAL_INPUT_DATA_LOWER_D0_MASK (0x00000003UL) 846#define SCU_SGPIO_SERIAL_INPUT_DATA_LOWER_D1_SHIFT (4UL) 847#define SCU_SGPIO_SERIAL_INPUT_DATA_LOWER_D1_MASK (0x00000030UL) 848#define SCU_SGPIO_SERIAL_INPUT_DATA_LOWER_D2_SHIFT (8UL) 849#define SCU_SGPIO_SERIAL_INPUT_DATA_LOWER_D2_MASK (0x00000300UL) 850#define SCU_SGPIO_SERIAL_INPUT_DATA_LOWER_D3_SHIFT (12UL) 851#define SCU_SGPIO_SERIAL_INPUT_DATA_LOWER_D3_MASK (0x00003000UL) 852#define SCU_SGPIO_SERIAL_INPUT_DATA_LOWER_RESERVED_MASK (0xFFFF8888UL) 853 854#define SCU_SGSIDLRx_GEN_VAL(name, valueUL) \ 855 SCU_GEN_VALUE(SCU_SGPIO_SERIAL_INPUT_DATA_LOWER_##name, value) 856 857#define SCU_SGPIO_SERIAL_INPUT_DATA_UPPER_D0_SHIFT (0UL) 858#define SCU_SGPIO_SERIAL_INPUT_DATA_UPPER_D0_MASK (0x00000003UL) 859#define SCU_SGPIO_SERIAL_INPUT_DATA_UPPER_D1_SHIFT (4UL) 860#define SCU_SGPIO_SERIAL_INPUT_DATA_UPPER_D1_MASK (0x00000030UL) 861#define SCU_SGPIO_SERIAL_INPUT_DATA_UPPER_D2_SHIFT (8UL) 862#define SCU_SGPIO_SERIAL_INPUT_DATA_UPPER_D2_MASK (0x00000300UL) 863#define SCU_SGPIO_SERIAL_INPUT_DATA_UPPER_D3_SHIFT (12UL) 864#define SCU_SGPIO_SERIAL_INPUT_DATA_UPPER_D3_MASK (0x00003000UL) 865#define SCU_SGPIO_SERIAL_INPUT_DATA_UPPER_RESERVED_MASK (0xFFFF8888UL) 866 867#define SCU_SGSIDURx_GEN_VAL(name, value) \ 868 SCU_GEN_VALUE(SCU_SGPIO_SERIAL_INPUT_DATA_LOWER_##name, value) 869 870#define SCU_SGPIO_VENDOR_SPECIFIC_CODE_SHIFT (0UL) 871#define SCU_SGPIO_VENDOR_SPECIFIC_CODE_MASK (0x0000000FUL) 872#define SCU_SGPIO_VENDOR_SPECIFIC_CODE_RESERVED_MASK (0xFFFFFFF0UL) 873 874#define SCU_SGVSCR_GEN_VAL(value) \ 875 SCU_GEN_VALUE(SCU_SGPIO_VENDOR_SPECIFIC_CODE##name, value) 876 877#define SCU_SGPIO_OUPUT_DATA_SELECT_INPUT_DATA0_SHIFT (0UL) 878#define SCU_SGPIO_OUPUT_DATA_SELECT_INPUT_DATA0_MASK (0x00000003UL) 879#define SCU_SGPIO_OUPUT_DATA_SELECT_INVERT_INPUT_DATA0_SHIFT (2UL) 880#define SCU_SGPIO_OUPUT_DATA_SELECT_INVERT_INPUT_DATA0_MASK (0x00000004UL) 881#define SCU_SGPIO_OUPUT_DATA_SELECT_JOG_ENABLE_DATA0_SHIFT (3UL) 882#define SCU_SGPIO_OUPUT_DATA_SELECT_JOG_ENABLE_DATA0_MASK (0x00000008UL) 883#define SCU_SGPIO_OUPUT_DATA_SELECT_INPUT_DATA1_SHIFT (4UL) 884#define SCU_SGPIO_OUPUT_DATA_SELECT_INPUT_DATA1_MASK (0x00000030UL) 885#define SCU_SGPIO_OUPUT_DATA_SELECT_INVERT_INPUT_DATA1_SHIFT (6UL) 886#define SCU_SGPIO_OUPUT_DATA_SELECT_INVERT_INPUT_DATA1_MASK (0x00000040UL) 887#define SCU_SGPIO_OUPUT_DATA_SELECT_JOG_ENABLE_DATA1_SHIFT (7UL) 888#define SCU_SGPIO_OUPUT_DATA_SELECT_JOG_ENABLE_DATA1_MASK (0x00000080UL) 889#define SCU_SGPIO_OUPUT_DATA_SELECT_INPUT_DATA2_SHIFT (8UL) 890#define SCU_SGPIO_OUPUT_DATA_SELECT_INPUT_DATA2_MASK (0x00000300UL) 891#define SCU_SGPIO_OUPUT_DATA_SELECT_INVERT_INPUT_DATA2_SHIFT (10UL) 892#define SCU_SGPIO_OUPUT_DATA_SELECT_INVERT_INPUT_DATA2_MASK (0x00000400UL) 893#define SCU_SGPIO_OUPUT_DATA_SELECT_JOG_ENABLE_DATA2_SHIFT (11UL) 894#define SCU_SGPIO_OUPUT_DATA_SELECT_JOG_ENABLE_DATA2_MASK (0x00000800UL) 895#define SCU_SGPIO_OUPUT_DATA_SELECT_RESERVED_MASK (0xFFFFF000UL) 896 897#define SCU_SGODSR_GEN_VAL(name, value) \ 898 SCU_GEN_VALUE(SCU_SGPIO_OUPUT_DATA_SELECT_##name, value) 899 900#define SCU_SGODSR_GEN_BIT(name) \ 901 SCU_GEN_BIT(SCU_SGPIO_OUPUT_DATA_SELECT_##name) 902 903#ifdef ARLINGTON_BUILD 904typedef char LEX_REGISTERS_T; 905#endif 906 907//***************************************************************************** 908//* SMU Registers 909//***************************************************************************** 910 911// ---------------------------------------------------------------------------- 912// SMU Registers 913// These registers are based off of BAR0 914// 915// To calculate the offset for other functions use 916// BAR0 + FN# * SystemPageSize * 2 917// 918// The TCA is only accessible from FN#0 (Physical Function) and each 919// is programmed by (BAR0 + SCU_SMU_TCA_OFFSET + (FN# * 0x04)) or 920// TCA0 for FN#0 is at BAR0 + 0x0400 921// TCA1 for FN#1 is at BAR0 + 0x0404 922// etc. 923// ---------------------------------------------------------------------------- 924// Accessible to all FN#s 925#define SCU_SMU_PCP_OFFSET 0x0000 926#define SCU_SMU_AMR_OFFSET 0x0004 927#define SCU_SMU_ISR_OFFSET 0x0010 928#define SCU_SMU_IMR_OFFSET 0x0014 929#define SCU_SMU_ICC_OFFSET 0x0018 930#define SCU_SMU_HTTLBAR_OFFSET 0x0020 931#define SCU_SMU_HTTUBAR_OFFSET 0x0024 932#define SCU_SMU_TCR_OFFSET 0x0028 933#define SCU_SMU_CQLBAR_OFFSET 0x0030 934#define SCU_SMU_CQUBAR_OFFSET 0x0034 935#define SCU_SMU_CQPR_OFFSET 0x0040 936#define SCU_SMU_CQGR_OFFSET 0x0044 937#define SCU_SMU_CQC_OFFSET 0x0048 938// Accessible to FN#0 only 939#define SCU_SMU_RNCLBAR_OFFSET 0x0080 940#define SCU_SMU_RNCUBAR_OFFSET 0x0084 941#define SCU_SMU_DCC_OFFSET 0x0090 942#define SCU_SMU_DFC_OFFSET 0x0094 943#define SCU_SMU_SMUCSR_OFFSET 0x0098 944#define SCU_SMU_SCUSRCR_OFFSET 0x009C 945#define SCU_SMU_SMAW_OFFSET 0x00A0 946#define SCU_SMU_SMDW_OFFSET 0x00A4 947// Accessible to FN#0 only 948#define SCU_SMU_TCA_OFFSET 0x0400 949// Accessible to all FN#s 950#define SCU_SMU_MT_MLAR0_OFFSET 0x2000 951#define SCU_SMU_MT_MUAR0_OFFSET 0x2004 952#define SCU_SMU_MT_MDR0_OFFSET 0x2008 953#define SCU_SMU_MT_VCR0_OFFSET 0x200C 954#define SCU_SMU_MT_MLAR1_OFFSET 0x2010 955#define SCU_SMU_MT_MUAR1_OFFSET 0x2014 956#define SCU_SMU_MT_MDR1_OFFSET 0x2018 957#define SCU_SMU_MT_VCR1_OFFSET 0x201C 958#define SCU_SMU_MPBA_OFFSET 0x3000 959 960/** 961 * @struct SMU_REGISTERS 962 * 963 * @brief These are the SMU registers 964 * See SCU SMU Specification on how this register space is used. 965 */ 966typedef struct SMU_REGISTERS 967{ 968// 0x0000 PCP 969 U32 post_context_port; 970// 0x0004 AMR 971 U32 address_modifier; 972 U32 reserved_08; 973 U32 reserved_0C; 974// 0x0010 ISR 975 U32 interrupt_status; 976// 0x0014 IMR 977 U32 interrupt_mask; 978// 0x0018 ICC 979 U32 interrupt_coalesce_control; 980 U32 reserved_1C; 981// 0x0020 HTTLBAR 982 U32 host_task_table_lower; 983// 0x0024 HTTUBAR 984 U32 host_task_table_upper; 985// 0x0028 TCR 986 U32 task_context_range; 987 U32 reserved_2C; 988// 0x0030 CQLBAR 989 U32 completion_queue_lower; 990// 0x0034 CQUBAR 991 U32 completion_queue_upper; 992 U32 reserved_38; 993 U32 reserved_3C; 994// 0x0040 CQPR 995 U32 completion_queue_put; 996// 0x0044 CQGR 997 U32 completion_queue_get; 998// 0x0048 CQC 999 U32 completion_queue_control; 1000 U32 reserved_4C; 1001 U32 reserved_5x[4]; 1002 U32 reserved_6x[4]; 1003 U32 reserved_7x[4]; 1004// Accessible to FN#0 only 1005// 0x0080 RNCLBAR 1006 U32 remote_node_context_lower; 1007// 0x0084 RNCUBAR 1008 U32 remote_node_context_upper; 1009 U32 reserved_88; 1010 U32 reserved_8C; 1011// 0x0090 DCC 1012 U32 device_context_capacity; 1013// 0x0094 DFC 1014 U32 device_function_capacity; 1015// 0x0098 SMUCSR 1016 U32 control_status; 1017// 0x009C SCUSRCR 1018 U32 soft_reset_control; 1019// 0x00A0 SMAW 1020 U32 mmr_address_window; 1021// 0x00A4 SMDW 1022 U32 mmr_data_window; 1023// 0x00A8 CGUCR 1024 U32 clock_gating_control; 1025// 0x00AC CGUPC 1026 U32 clock_gating_performance; 1027// A whole bunch of reserved space 1028 U32 reserved_Bx[4]; 1029 U32 reserved_Cx[4]; 1030 U32 reserved_Dx[4]; 1031 U32 reserved_Ex[4]; 1032 U32 reserved_Fx[4]; 1033 U32 reserved_1xx[64]; 1034 U32 reserved_2xx[64]; 1035 U32 reserved_3xx[64]; 1036// Accessible to FN#0 only 1037// 0x0400 TCA 1038 U32 task_context_assignment[256]; 1039// MSI-X registers not included 1040} SMU_REGISTERS_T; 1041 1042//***************************************************************************** 1043// SDMA Registers 1044//***************************************************************************** 1045#define SCU_SDMA_BASE 0x6000 1046#define SCU_SDMA_PUFATLHAR_OFFSET 0x0000 1047#define SCU_SDMA_PUFATUHAR_OFFSET 0x0004 1048#define SCU_SDMA_UFLHBAR_OFFSET 0x0008 1049#define SCU_SDMA_UFUHBAR_OFFSET 0x000C 1050#define SCU_SDMA_UFQC_OFFSET 0x0010 1051#define SCU_SDMA_UFQPP_OFFSET 0x0014 1052#define SCU_SDMA_UFQGP_OFFSET 0x0018 1053#define SCU_SDMA_PDMACR_OFFSET 0x001C 1054#define SCU_SDMA_CDMACR_OFFSET 0x0080 1055 1056/** 1057 * @struct SCU_SDMA_REGISTERS 1058 * 1059 * @brief These are the SCU SDMA Registers 1060 * See SCU SDMA specification on how these registers are used. 1061 */ 1062typedef struct SCU_SDMA_REGISTERS 1063{ 1064// 0x0000 PUFATLHAR 1065 U32 uf_address_table_lower; 1066// 0x0004 PUFATUHAR 1067 U32 uf_address_table_upper; 1068// 0x0008 UFLHBAR 1069 U32 uf_header_base_address_lower; 1070// 0x000C UFUHBAR 1071 U32 uf_header_base_address_upper; 1072// 0x0010 UFQC 1073 U32 unsolicited_frame_queue_control; 1074// 0x0014 UFQPP 1075 U32 unsolicited_frame_put_pointer; 1076// 0x0018 UFQGP 1077 U32 unsolicited_frame_get_pointer; 1078// 0x001C PDMACR 1079 U32 pdma_configuration; 1080// Reserved until offset 0x80 1081 U32 reserved_0020_007C[0x18]; 1082// 0x0080 CDMACR 1083 U32 cdma_configuration; 1084// Remainder SDMA register space 1085 U32 reserved_0084_0400[0xDF]; 1086 1087} SCU_SDMA_REGISTERS_T; 1088 1089//***************************************************************************** 1090//* SCU Link Registers 1091//***************************************************************************** 1092#define SCU_PEG0_OFFSET 0x0000 1093#define SCU_PEG1_OFFSET 0x8000 1094 1095#define SCU_TL0_OFFSET 0x0000 1096#define SCU_TL1_OFFSET 0x0400 1097#define SCU_TL2_OFFSET 0x0800 1098#define SCU_TL3_OFFSET 0x0C00 1099 1100#define SCU_LL_OFFSET 0x0080 1101#define SCU_LL0_OFFSET (SCU_TL0_OFFSET + SCU_LL_OFFSET) 1102#define SCU_LL1_OFFSET (SCU_TL1_OFFSET + SCU_LL_OFFSET) 1103#define SCU_LL2_OFFSET (SCU_TL2_OFFSET + SCU_LL_OFFSET) 1104#define SCU_LL3_OFFSET (SCU_TL3_OFFSET + SCU_LL_OFFSET) 1105 1106// Transport Layer Offsets (PEG + TL) 1107#define SCU_TLCR_OFFSET 0x0000 1108#define SCU_TLADTR_OFFSET 0x0004 1109#define SCU_TLTTMR_OFFSET 0x0008 1110#define SCU_TLEECR0_OFFSET 0x000C 1111#define SCU_STPTLDARNI_OFFSET 0x0010 1112 1113 1114#define SCU_TLCR_HASH_SAS_CHECKING_ENABLE_SHIFT (0UL) 1115#define SCU_TLCR_HASH_SAS_CHECKING_ENABLE_MASK (0x00000001UL) 1116#define SCU_TLCR_CLEAR_TCI_NCQ_MAPPING_TABLE_SHIFT (1UL) 1117#define SCU_TLCR_CLEAR_TCI_NCQ_MAPPING_TABLE_MASK (0x00000002UL) 1118#define SCU_TLCR_STP_WRITE_DATA_PREFETCH_SHIFT (3UL) 1119#define SCU_TLCR_STP_WRITE_DATA_PREFETCH_MASK (0x00000008UL) 1120#define SCU_TLCR_CMD_NAK_STATUS_CODE_SHIFT (4UL) 1121#define SCU_TLCR_CMD_NAK_STATUS_CODE_MASK (0x00000010UL) 1122#define SCU_TLCR_RESERVED_MASK (0xFFFFFFEBUL) 1123 1124#define SCU_TLCR_GEN_BIT(name) \ 1125 SCU_GEN_BIT(SCU_TLCR_##name) 1126 1127/** 1128 * @struct SCU_TRANSPORT_LAYER_REGISTERS 1129 * 1130 * @brief These are the SCU Transport Layer registers see SSPTL spec for how 1131 * they are used. 1132 */ 1133typedef struct SCU_TRANSPORT_LAYER_REGISTERS 1134{ 1135 // 0x0000 TLCR 1136 U32 control; 1137 // 0x0004 TLADTR 1138 U32 arbitration_delay_timer; 1139 // 0x0008 TLTTMR 1140 U32 timer_test_mode; 1141 // 0x000C reserved 1142 U32 reserved_0C; 1143 // 0x0010 STPTLDARNI 1144 U32 stp_rni; 1145 // 0x0014 TLFEWPORCTRL 1146 U32 tlfe_wpo_read_control; 1147 // 0x0018 TLFEWPORDATA 1148 U32 tlfe_wpo_read_data; 1149 // 0x001C RXTLSSCSR1 1150 U32 rxtl_single_step_control_status_1; 1151 // 0x0020 RXTLSSCSR2 1152 U32 rxtl_single_step_control_status_2; 1153 // 0x0024 AWTRDDCR 1154 U32 tlfe_awt_retry_delay_debug_control; 1155 // Remainder of TL memory space 1156 U32 reserved_0028_007F[0x16]; 1157 1158} SCU_TRANSPORT_LAYER_REGISTERS_T; 1159 1160// Protocol Engine Group Registers 1161#define SCU_SCUVZECRx_OFFSET 0x1080 1162 1163// Link Layer Offsets (PEG + TL + LL) 1164#define SCU_SAS_SPDTOV_OFFSET 0x0000 1165#define SCU_SAS_LLSTA_OFFSET 0x0004 1166#define SCU_SATA_PSELTOV_OFFSET 0x0008 1167#define SCU_SAS_TIMETOV_OFFSET 0x0010 1168#define SCU_SAS_LOSTOT_OFFSET 0x0014 1169#define SCU_SAS_LNKTOV_OFFSET 0x0018 1170#define SCU_SAS_PHYTOV_OFFSET 0x001C 1171#define SCU_SAS_AFERCNT_OFFSET 0x0020 1172#define SCU_SAS_WERCNT_OFFSET 0x0024 1173#define SCU_SAS_TIID_OFFSET 0x0028 1174#define SCU_SAS_TIDNH_OFFSET 0x002C 1175#define SCU_SAS_TIDNL_OFFSET 0x0030 1176#define SCU_SAS_TISSAH_OFFSET 0x0034 1177#define SCU_SAS_TISSAL_OFFSET 0x0038 1178#define SCU_SAS_TIPID_OFFSET 0x003C 1179#define SCU_SAS_TIRES2_OFFSET 0x0040 1180#define SCU_SAS_ADRSTA_OFFSET 0x0044 1181#define SCU_SAS_MAWTTOV_OFFSET 0x0048 1182#define SCU_SAS_ECENCR_OFFSET 0x0050 1183#define SCU_SAS_FRPLDFIL_OFFSET 0x0054 1184#define SCU_SAS_RFCNT_OFFSET 0x0060 1185#define SCU_SAS_TFCNT_OFFSET 0x0064 1186#define SCU_SAS_RFDCNT_OFFSET 0x0068 1187#define SCU_SAS_TFDCNT_OFFSET 0x006C 1188#define SCU_SAS_LERCNT_OFFSET 0x0070 1189#define SCU_SAS_RDISERRCNT_OFFSET 0x0074 1190#define SCU_SAS_CRERCNT_OFFSET 0x0078 1191#define SCU_STPCTL_OFFSET 0x007C 1192#define SCU_SAS_PCFG_OFFSET 0x0080 1193#define SCU_SAS_CLKSM_OFFSET 0x0084 1194#define SCU_SAS_TXCOMWAKE_OFFSET 0x0088 1195#define SCU_SAS_TXCOMINIT_OFFSET 0x008C 1196#define SCU_SAS_TXCOMSAS_OFFSET 0x0090 1197#define SCU_SAS_COMINIT_OFFSET 0x0094 1198#define SCU_SAS_COMWAKE_OFFSET 0x0098 1199#define SCU_SAS_COMSAS_OFFSET 0x009C 1200#define SCU_SAS_SFERCNT_OFFSET 0x00A0 1201#define SCU_SAS_CDFERCNT_OFFSET 0x00A4 1202#define SCU_SAS_DNFERCNT_OFFSET 0x00A8 1203#define SCU_SAS_PRSTERCNT_OFFSET 0x00AC 1204#define SCU_SAS_CNTCTL_OFFSET 0x00B0 1205#define SCU_SAS_SSPTOV_OFFSET 0x00B4 1206#define SCU_FTCTL_OFFSET 0x00B8 1207#define SCU_FRCTL_OFFSET 0x00BC 1208#define SCU_FTWMRK_OFFSET 0x00C0 1209#define SCU_ENSPINUP_OFFSET 0x00C4 1210#define SCU_SAS_TRNTOV_OFFSET 0x00C8 1211#define SCU_SAS_PHYCAP_OFFSET 0x00CC 1212#define SCU_SAS_PHYCTL_OFFSET 0x00D0 1213#define SCU_SAS_LLCTL_OFFSET 0x00D8 1214#define SCU_AFE_XCVRCR_OFFSET 0x00DC 1215#define SCU_AFE_LUTCR_OFFSET 0x00E0 1216 1217#define SCU_SAS_PHY_TIMER_TIMEOUT_VALUES_ALIGN_DETECTION_SHIFT (0UL) 1218#define SCU_SAS_PHY_TIMER_TIMEOUT_VALUES_ALIGN_DETECTION_MASK (0x000000FFUL) 1219#define SCU_SAS_PHY_TIMER_TIMEOUT_VALUES_HOT_PLUG_SHIFT (8UL) 1220#define SCU_SAS_PHY_TIMER_TIMEOUT_VALUES_HOT_PLUG_MASK (0x0000FF00UL) 1221#define SCU_SAS_PHY_TIMER_TIMEOUT_VALUES_COMSAS_DETECTION_SHIFT (16UL) 1222#define SCU_SAS_PHY_TIMER_TIMEOUT_VALUES_COMSAS_DETECTION_MASK (0x00FF0000UL) 1223#define SCU_SAS_PHY_TIMER_TIMEOUT_VALUES_RATE_CHANGE_SHIFT (24UL) 1224#define SCU_SAS_PHY_TIMER_TIMEOUT_VALUES_RATE_CHANGE_MASK (0xFF000000UL) 1225 1226#define SCU_SAS_PHYTOV_GEN_VAL(name, value) \ 1227 SCU_GEN_VALUE(SCU_SAS_PHY_TIMER_TIMEOUT_VALUES_##name, value) 1228 1229#define SCU_SAS_LINK_LAYER_CONTROL_MAX_LINK_RATE_SHIFT (0UL) 1230#define SCU_SAS_LINK_LAYER_CONTROL_MAX_LINK_RATE_MASK (0x00000003UL) 1231#define SCU_SAS_LINK_LAYER_CONTROL_MAX_LINK_RATE_GEN1 (0UL) 1232#define SCU_SAS_LINK_LAYER_CONTROL_MAX_LINK_RATE_GEN2 (1UL) 1233#define SCU_SAS_LINK_LAYER_CONTROL_MAX_LINK_RATE_GEN3 (2UL) 1234#define SCU_SAS_LINK_LAYER_CONTROL_BROADCAST_PRIMITIVE_SHIFT (2UL) 1235#define SCU_SAS_LINK_LAYER_CONTROL_BROADCAST_PRIMITIVE_MASK (0x000003FCUL) 1236#define SCU_SAS_LINK_LAYER_CONTROL_CLOSE_NO_ACTIVE_TASK_DISABLE_SHIFT (16UL) 1237#define SCU_SAS_LINK_LAYER_CONTROL_CLOSE_NO_ACTIVE_TASK_DISABLE_MASK (0x00010000UL) 1238#define SCU_SAS_LINK_LAYER_CONTROL_CLOSE_NO_OUTBOUND_TASK_DISABLE_SHIFT (17UL) 1239#define SCU_SAS_LINK_LAYER_CONTROL_CLOSE_NO_OUTBOUND_TASK_DISABLE_MASK (0x00020000UL) 1240#define SCU_SAS_LINK_LAYER_CONTROL_NO_OUTBOUND_TASK_TIMEOUT_SHIFT (24UL) 1241#define SCU_SAS_LINK_LAYER_CONTROL_NO_OUTBOUND_TASK_TIMEOUT_MASK (0xFF000000UL) 1242#define SCU_SAS_LINK_LAYER_CONTROL_RESERVED (0x00FCFC00UL) 1243 1244#define SCU_SAS_LLCTL_GEN_VAL(name, value) \ 1245 SCU_GEN_VALUE(SCU_SAS_LINK_LAYER_CONTROL_##name, value) 1246 1247#define SCU_SAS_LLCTL_GEN_BIT(name) \ 1248 SCU_GEN_BIT(SCU_SAS_LINK_LAYER_CONTROL_##name) 1249 1250//#define SCU_FRXHECR_DCNT_OFFSET 0x00B0 1251#define SCU_PSZGCR_OFFSET 0x00E4 1252#define SCU_SAS_RECPHYCAP_OFFSET 0x00E8 1253//#define SCU_TX_LUTSEL_OFFSET 0x00B8 1254 1255#define SCU_SAS_PTxC_OFFSET 0x00D4 // Same offset as SAS_TCTSTM 1256 1257// This macro define the DWORD SYNC ACQUIRED bit in link layer status register. 1258#define SCU_SAS_LLSTA_DWORD_SYNCA_BIT 0x4 1259 1260/** 1261 * @struct SCU_LINK_LAYER_REGISTERS 1262 * 1263 * @brief SCU Link Layer Registers 1264 * See the SCU SSLL Specification on how these registers are used. 1265 */ 1266typedef struct SCU_LINK_LAYER_REGISTERS 1267{ 1268// 0x0000 SAS_SPDTOV 1269 U32 speed_negotiation_timers; 1270// 0x0004 SAS_LLSTA 1271 U32 link_layer_status; 1272// 0x0008 SATA_PSELTOV 1273 U32 port_selector_timeout; 1274 U32 reserved0C; 1275// 0x0010 SAS_TIMETOV 1276 U32 timeout_unit_value; 1277// 0x0014 SAS_RCDTOV 1278 U32 rcd_timeout; 1279// 0x0018 SAS_LNKTOV 1280 U32 link_timer_timeouts; 1281// 0x001C SAS_PHYTOV 1282 U32 phy_timer_timeout_values; 1283// 0x0020 SAS_AFERCNT 1284 U32 received_address_frame_error_counter; 1285// 0x0024 SAS_WERCNT 1286 U32 invalid_dword_counter; 1287// 0x0028 SAS_TIID 1288 U32 transmit_identification; 1289// 0x002C SAS_TIDNH 1290 U32 sas_device_name_high; 1291// 0x0030 SAS_TIDNL 1292 U32 sas_device_name_low; 1293// 0x0034 SAS_TISSAH 1294 U32 source_sas_address_high; 1295// 0x0038 SAS_TISSAL 1296 U32 source_sas_address_low; 1297// 0x003C SAS_TIPID 1298 U32 identify_frame_phy_id; 1299// 0x0040 SAS_TIRES2 1300 U32 identify_frame_reserved; 1301// 0x0044 SAS_ADRSTA 1302 U32 received_address_frame; 1303// 0x0048 SAS_MAWTTOV 1304 U32 maximum_arbitration_wait_timer_timeout; 1305// 0x004C SAS_PTxC 1306 U32 transmit_primitive; 1307// 0x0050 SAS_ECENCR 1308 U32 error_counter_event_notification_control; 1309// 0x0054 SAS_FRPLDFIL 1310 U32 frxq_payload_fill_threshold; 1311// 0x0058 SAS_LLHANG_TOT 1312 U32 link_layer_hang_detection_timeout; 1313 U32 reserved_5C; 1314// 0x0060 SAS_RFCNT 1315 U32 received_frame_count; 1316// 0x0064 SAS_TFCNT 1317 U32 transmit_frame_count; 1318// 0x0068 SAS_RFDCNT 1319 U32 received_dword_count; 1320// 0x006C SAS_TFDCNT 1321 U32 transmit_dword_count; 1322// 0x0070 SAS_LERCNT 1323 U32 loss_of_sync_error_count; 1324// 0x0074 SAS_RDISERRCNT 1325 U32 running_disparity_error_count; 1326// 0x0078 SAS_CRERCNT 1327 U32 received_frame_crc_error_count; 1328// 0x007C STPCTL 1329 U32 stp_control; 1330// 0x0080 SAS_PCFG 1331 U32 phy_configuration; 1332// 0x0084 SAS_CLKSM 1333 U32 clock_skew_management; 1334// 0x0088 SAS_TXCOMWAKE 1335 U32 transmit_comwake_signal; 1336// 0x008C SAS_TXCOMINIT 1337 U32 transmit_cominit_signal; 1338// 0x0090 SAS_TXCOMSAS 1339 U32 transmit_comsas_signal; 1340// 0x0094 SAS_COMINIT 1341 U32 cominit_control; 1342// 0x0098 SAS_COMWAKE 1343 U32 comwake_control; 1344// 0x009C SAS_COMSAS 1345 U32 comsas_control; 1346// 0x00A0 SAS_SFERCNT 1347 U32 received_short_frame_count; 1348// 0x00A4 SAS_CDFERCNT 1349 U32 received_frame_without_credit_count; 1350// 0x00A8 SAS_DNFERCNT 1351 U32 received_frame_after_done_count; 1352// 0x00AC SAS_PRSTERCNT 1353 U32 phy_reset_problem_count; 1354// 0x00B0 SAS_CNTCTL 1355 U32 counter_control; 1356// 0x00B4 SAS_SSPTOV 1357 U32 ssp_timer_timeout_values; 1358// 0x00B8 FTCTL 1359 U32 ftx_control; 1360// 0x00BC FRCTL 1361 U32 frx_control; 1362// 0x00C0 FTWMRK 1363 U32 ftx_watermark; 1364// 0x00C4 ENSPINUP 1365 U32 notify_enable_spinup_control; 1366// 0x00C8 SAS_TRNTOV 1367 U32 sas_training_sequence_timer_values; 1368// 0x00CC SAS_PHYCAP 1369 U32 phy_capabilities; 1370// 0x00D0 SAS_PHYCTL 1371 U32 phy_control; 1372 U32 reserved_d4; 1373// 0x00D8 LLCTL 1374 U32 link_layer_control; 1375// 0x00DC AFE_XCVRCR 1376 U32 afe_xcvr_control; 1377// 0x00E0 AFE_LUTCR 1378 U32 afe_lookup_table_control; 1379// 0x00E4 PSZGCR 1380 U32 phy_source_zone_group_control; 1381// 0x00E8 SAS_RECPHYCAP 1382 U32 receive_phycap; 1383 U32 reserved_ec; 1384// 0x00F0 SNAFERXRSTCTL 1385 U32 speed_negotiation_afe_rx_reset_control; 1386// 0x00F4 SAS_SSIPMCTL 1387 U32 power_management_control; 1388// 0x00F8 SAS_PSPREQ_PRIM 1389 U32 sas_pm_partial_request_primitive; 1390// 0x00FC SAS_PSSREQ_PRIM 1391 U32 sas_pm_slumber_request_primitive; 1392// 0x0100 SAS_PPSACK_PRIM 1393 U32 sas_pm_ack_primitive_register; 1394// 0x0104 SAS_PSNAK_PRIM 1395 U32 sas_pm_nak_primitive_register; 1396// 0x0108 SAS_SSIPMTOV 1397 U32 sas_primitive_timeout; 1398 U32 reserved_10c; 1399// 0x0110 - 0x011C PLAPRDCTRLxREG 1400 U32 pla_product_control[4]; 1401// 0x0120 PLAPRDSUMREG 1402 U32 pla_product_sum; 1403// 0x0124 PLACONTROLREG 1404 U32 pla_control; 1405// Remainder of memory space 896 bytes 1406 U32 reserved_0128_037f[0x96]; 1407 1408} SCU_LINK_LAYER_REGISTERS_T; 1409 1410// 0x00D4 // Same offset as SAS_TCTSTM SAS_PTxC 1411// U32 primitive_transmit_control; 1412 1413// ---------------------------------------------------------------------------- 1414// SGPIO 1415// ---------------------------------------------------------------------------- 1416#define SCU_SGPIO_OFFSET 0x1400 1417 1418//#define SCU_SGPIO_OFFSET 0x6000 // later moves to 0x1400 see HSD 652625 1419#define SCU_SGPIO_SGICR_OFFSET 0x0000 1420#define SCU_SGPIO_SGPBR_OFFSET 0x0004 1421#define SCU_SGPIO_SGSDLR_OFFSET 0x0008 1422#define SCU_SGPIO_SGSDUR_OFFSET 0x000C 1423#define SCU_SGPIO_SGSIDLR_OFFSET 0x0010 1424#define SCU_SGPIO_SGSIDUR_OFFSET 0x0014 1425#define SCU_SGPIO_SGVSCR_OFFSET 0x0018 1426// Address from 0x0820 to 0x083C 1427#define SCU_SGPIO_SGODSR_OFFSET 0x0020 1428 1429/** 1430 * @struct SCU_SGPIO_REGISTERS 1431 * 1432 * @brief SCU SGPIO Registers 1433 * See the SCU SGPIO Specification on how these registers are used. 1434 */ 1435typedef struct SCU_SGPIO_REGISTERS 1436{ 1437// 0x0000 SGPIO_SGICR 1438 U32 interface_control; 1439// 0x0004 SGPIO_SGPBR 1440 U32 blink_rate; 1441// 0x0008 SGPIO_SGSDLR 1442 U32 start_drive_lower; 1443// 0x000C SGPIO_SGSDUR 1444 U32 start_drive_upper; 1445// 0x0010 SGPIO_SGSIDLR 1446 U32 serial_input_lower; 1447// 0x0014 SGPIO_SGSIDUR 1448 U32 serial_input_upper; 1449// 0x0018 SGPIO_SGVSCR 1450 U32 vendor_specific_code; 1451// 0x001C Reserved 1452 U32 reserved_001C; 1453// 0x0020 SGPIO_SGODSR 1454 U32 output_data_select[8]; 1455// Remainder of memory space 256 bytes 1456 U32 reserved_1444_14ff[0x30]; 1457 1458} SCU_SGPIO_REGISTERS_T; 1459 1460//***************************************************************************** 1461//* Defines for VIIT entry offsets 1462//* Access additional entries by SCU_VIIT_BASE + index * 0x10 1463//***************************************************************************** 1464#define SCU_VIIT_BASE 0x1c00 1465 1466struct SCU_VIIT_REGISTERS 1467{ 1468 U32 registers[256]; 1469}; 1470 1471//***************************************************************************** 1472//* SCU PORT TASK SCHEDULER REGISTERS 1473//***************************************************************************** 1474 1475#define SCU_PTSG_BASE 0x1000 1476 1477#define SCU_PTSG_PTSGCR_OFFSET 0x0000 1478#define SCU_PTSG_RTCR_OFFSET 0x0004 1479#define SCU_PTSG_RTCCR_OFFSET 0x0008 1480#define SCU_PTSG_PTS0CR_OFFSET 0x0010 1481#define SCU_PTSG_PTS0SR_OFFSET 0x0014 1482#define SCU_PTSG_PTS1CR_OFFSET 0x0018 1483#define SCU_PTSG_PTS1SR_OFFSET 0x001C 1484#define SCU_PTSG_PTS2CR_OFFSET 0x0020 1485#define SCU_PTSG_PTS2SR_OFFSET 0x0024 1486#define SCU_PTSG_PTS3CR_OFFSET 0x0028 1487#define SCU_PTSG_PTS3SR_OFFSET 0x002C 1488#define SCU_PTSG_PCSPE0CR_OFFSET 0x0030 1489#define SCU_PTSG_PCSPE1CR_OFFSET 0x0034 1490#define SCU_PTSG_PCSPE2CR_OFFSET 0x0038 1491#define SCU_PTSG_PCSPE3CR_OFFSET 0x003C 1492#define SCU_PTSG_ETMTSCCR_OFFSET 0x0040 1493#define SCU_PTSG_ETMRNSCCR_OFFSET 0x0044 1494 1495/** 1496 * @struct SCU_PORT_TASK_SCHEDULER_REGISTERS 1497 * 1498 * @brief These are the control/stats pairs for each Port Task Scheduler. 1499 * See the SCU SCHED Specification on how these registers are used. 1500 */ 1501typedef struct SCU_PORT_TASK_SCHEDULER_REGISTERS 1502{ 1503 U32 control; 1504 U32 status; 1505} SCU_PORT_TASK_SCHEDULER_REGISTERS_T; 1506 1507typedef U32 SCU_PORT_PE_CONFIGURATION_REGISTER_T; 1508 1509/** 1510 * @struct SCU_PORT_TASK_SCHEDULER_GROUP_REGISTERS 1511 * 1512 * @brief These are the PORT Task Scheduler registers 1513 * See the SCU SCHED Specification on how these registers are used. 1514 */ 1515typedef struct SCU_PORT_TASK_SCHEDULER_GROUP_REGISTERS 1516{ 1517// 0x0000 PTSGCR 1518 U32 control; 1519// 0x0004 RTCR 1520 U32 real_time_clock; 1521// 0x0008 RTCCR 1522 U32 real_time_clock_control; 1523// 0x000C 1524 U32 reserved_0C; 1525// 0x0010 PTS0CR 1526// 0x0014 PTS0SR 1527// 0x0018 PTS1CR 1528// 0x001C PTS1SR 1529// 0x0020 PTS2CR 1530// 0x0024 PTS2SR 1531// 0x0028 PTS3CR 1532// 0x002C PTS3SR 1533 SCU_PORT_TASK_SCHEDULER_REGISTERS_T port[4]; 1534// 0x0030 PCSPE0CR 1535// 0x0034 PCSPE1CR 1536// 0x0038 PCSPE2CR 1537// 0x003C PCSPE3CR 1538 SCU_PORT_PE_CONFIGURATION_REGISTER_T protocol_engine[4]; 1539// 0x0040 ETMTSCCR 1540 U32 tc_scanning_interval_control; 1541// 0x0044 ETMRNSCCR 1542 U32 rnc_scanning_interval_control; 1543// Remainder of memory space 128 bytes 1544 U32 reserved_1048_107f[0x0E]; 1545 1546} SCU_PORT_TASK_SCHEDULER_GROUP_REGISTERS_T; 1547 1548#define SCU_PTSG_SCUVZECR_OFFSET 0x003C 1549 1550//***************************************************************************** 1551//* AFE REGISTERS 1552//***************************************************************************** 1553#define SCU_AFE_MMR_BASE 0xE000 1554 1555#if defined(ARLINGTON_BUILD) 1556#define SCU_AFE_PLL_CTL_OFFSET 0x0000 1557#define SCU_AFE_RXPI_CTL_OFFSET 0x0004 1558#define SCU_AFE_MBIAS_CTL0_OFFSET 0x000C 1559#define SCU_AFE_MBIAS_CTL1_OFFSET 0x0010 1560#define SCU_AFE_COMM_STA_OFFSET 0x0020 1561#define SCU_AFE_RXPI_STA_OFFSET 0x0024 1562#define SCU_AFE_XCVR0_CTL0_OFFSET 0x0040 1563#define SCU_AFE_XCVR1_CTL0_OFFSET 0x0044 1564#define SCU_AFE_XCVR2_CTL0_OFFSET 0x0048 1565#define SCU_AFE_XCVR3_CTL0_OFFSET 0x004C 1566#define SCU_AFE_XCVR0_CTL1_OFFSET 0x0050 1567#define SCU_AFE_XCVR1_CTL1_OFFSET 0x0054 1568#define SCU_AFE_XCVR2_CTL1_OFFSET 0x0058 1569#define SCU_AFE_XCVR3_CTL1_OFFSET 0x005C 1570#define SCU_AFE_XCVR0_RXEQ_CTL_OFFSET 0x0060 1571#define SCU_AFE_XCVR1_RXEQ_CTL_OFFSET 0x0064 1572#define SCU_AFE_XCVR2_RXEQ_CTL_OFFSET 0x0068 1573#define SCU_AFE_XCVR3_RXEQ_CTL_OFFSET 0x006C 1574#define SCU_AFE_XCVR0_CDR_STA_OFFSET 0x0080 1575#define SCU_AFE_XCVR1_CDR_STA_OFFSET 0x0084 1576#define SCU_AFE_XCVR2_CDR_STA_OFFSET 0x0088 1577#define SCU_AFE_XCVR3_CDR_STA_OFFSET 0x008C 1578#define SCU_AFE_XCVR0_RXEQ_STA0_OFFSET 0x0090 1579#define SCU_AFE_XCVR1_RXEQ_STA0_OFFSET 0x0094 1580#define SCU_AFE_XCVR2_RXEQ_STA0_OFFSET 0x0098 1581#define SCU_AFE_XCVR3_RXEQ_STA0_OFFSET 0x009C 1582#define SCU_AFE_XCVR0_RXEQ_STA1_OFFSET 0x00A0 1583#define SCU_AFE_XCVR1_RXEQ_STA1_OFFSET 0x00A4 1584#define SCU_AFE_XCVR2_RXEQ_STA1_OFFSET 0x00A8 1585#define SCU_AFE_XCVR3_RXEQ_STA1_OFFSET 0x00AC 1586#define SCU_AFE_DFX_MSTR_CTL_OFFSET 0x0104 1587#define SCU_AFE_NTL_CTL_OFFSET 0x010C 1588#define SCU_AFE_DFX_XCVR_STA_CLR_OFFSET 0x0120 1589#define SCU_AFE_NTL_STA_OFFSET 0x0124 1590#define SCU_AFE_DFX_XCVR0_STA0_OFFSET 0x0130 1591#define SCU_AFE_DFX_XCVR1_STA0_OFFSET 0x0134 1592#define SCU_AFE_DFX_XCVR2_STA0_OFFSET 0x0138 1593#define SCU_AFE_DFX_XCVR3_STA0_OFFSET 0x013C 1594#define SCU_AFE_DFX_XCVR0_STA1_OFFSET 0x0140 1595#define SCU_AFE_DFX_XCVR1_STA1_OFFSET 0x0144 1596#define SCU_AFE_DFX_XCVR2_STA1_OFFSET 0x0148 1597#define SCU_AFE_DFX_XCVR3_STA1_OFFSET 0x014C 1598#define SCU_AFE_DFX_MON_CTL_OFFSET 0x0150 1599 1600#define SCU_AFE_DFX_RX_CTL0_AFE0_XCVR0_OFFSET 0x0180 1601#define SCU_AFE_DFX_RX_CTL0_AFE0_XCVR1_OFFSET 0x0184 1602#define SCU_AFE_DFX_RX_CTL0_AFE0_XCVR2_OFFSET 0x0188 1603#define SCU_AFE_DFX_RX_CTL0_AFE0_XCVR3_OFFSET 0x018C 1604#define SCU_AFE_DFX_RX_CTL0_AFE1_XCVR0_OFFSET 0x0980 1605#define SCU_AFE_DFX_RX_CTL0_AFE1_XCVR1_OFFSET 0x0984 1606#define SCU_AFE_DFX_RX_CTL0_AFE1_XCVR2_OFFSET 0x0988 1607#define SCU_AFE_DFX_RX_CTL0_AFE1_XCVR3_OFFSET 0x098C 1608 1609#define SCU_AFE_DFX_RX_CTL1_AFE0_XCVR0_OFFSET 0x0190 1610#define SCU_AFE_DFX_RX_CTL1_AFE0_XCVR1_OFFSET 0x0194 1611#define SCU_AFE_DFX_RX_CTL1_AFE0_XCVR2_OFFSET 0x0198 1612#define SCU_AFE_DFX_RX_CTL1_AFE0_XCVR3_OFFSET 0x019C 1613#define SCU_AFE_DFX_RX_CTL1_AFE1_XCVR0_OFFSET 0x0990 1614#define SCU_AFE_DFX_RX_CTL1_AFE1_XCVR1_OFFSET 0x0994 1615#define SCU_AFE_DFX_RX_CTL1_AFE1_XCVR2_OFFSET 0x0998 1616#define SCU_AFE_DFX_RX_CTL1_AFE1_XCVR3_OFFSET 0x099C 1617 1618#define SCU_AFE_PLL_DFX_CTL_OFFSET 0x01C0 1619 1620#define SCU_AFE_XCVR0_DFX_DATA_OFFSET 0x0200 // [0:0F] 1621#define SCU_AFE_XCVR0_CC_OFFSET 0x0240 1622#define SCU_AFE_XCVR0_DFX_IR_OFFSET 0x0250 // [0:1F] 1623 1624#define SCU_AFE_XCVR1_DFX_DATA_OFFSET 0x0300 // [0:0F] 1625#define SCU_AFE_XCVR1_CC_OFFSET 0x0340 1626#define SCU_AFE_XCVR1_DFX_IR_OFFSET 0x0350 // [0:1F] 1627 1628#define SCU_AFE_XCVR2_DFX_DATA_OFFSET 0x0400 // [0:0F] 1629#define SCU_AFE_XCVR2_CC_OFFSET 0x0440 1630#define SCU_AFE_XCVR2_DFX_IR_OFFSET 0x0450 // [0:1F] 1631 1632#define SCU_AFE_XCVR3_DFX_DATA_OFFSET 0x0500 // [0:0F] 1633#define SCU_AFE_XCVR3_CC_OFFSET 0x0540 1634#define SCU_AFE_XCVR3_DFX_IR_OFFSET 0x0550 // [0:1F] 1635#else // defined(ARLINGTON_BUILD) 1636 1637#endif // defined(ARLINGTON_BUILD) 1638 1639/** 1640 * @struct SCU_AFE_TRANSCEIVER 1641 * 1642 * @brief AFE Transceiver Registers 1643 * See SCU AFE Specification for use of these registers. 1644 * 1645 * @note For ARLINGTON_BUILD see the SCU AFE specification. 1646 * @note For PLEASANT_RIDGE_BUILD build see the Uaoa AFE specification. 1647 */ 1648#if defined(ARLINGTON_BUILD) 1649 struct SCU_AFE_TRANSCEIVER 1650 { 1651 // 0x00 1652 U32 afe_transceiver_dfx_data[0x10]; 1653 // 0x40 1654 U32 afe_transceiver_dpg_cycle_control; 1655 // 0x44 - 0x4c 1656 U32 reserved_0044_004c[3]; 1657 // 0x50 1658 U32 afe_transceiver_dfx_instruction[0x20]; 1659 // 0xd0 - 0xfc 1660 U32 reserved_00d0_00fc[0x0C]; 1661 }; 1662 1663#elif defined(PLEASANT_RIDGE_BUILD) \ 1664 || defined(PBG_HBA_A0_BUILD) \ 1665 || defined(PBG_HBA_A2_BUILD) \ 1666 || defined(PBG_HBA_BETA_BUILD) \ 1667 || defined(PBG_BUILD) 1668 1669 // AFE 0 is at offset 0x0800 1670 // AFE 1 is at offset 0x0900 1671 // AFE 2 is at offset 0x0a00 1672 // AFE 3 is at offset 0x0b00 1673 struct SCU_AFE_TRANSCEIVER 1674 { 1675 // 0x0000 AFE_XCVR_CTRL0 1676 U32 afe_xcvr_control0; 1677 // 0x0004 AFE_XCVR_CTRL1 1678 U32 afe_xcvr_control1; 1679 // 0x0008 1680 U32 reserved_0008; 1681 // 0x000c afe_dfx_rx_control0 1682 U32 afe_dfx_rx_control0; 1683 // 0x0010 AFE_DFX_RX_CTRL1 1684 U32 afe_dfx_rx_control1; 1685 // 0x0014 1686 U32 reserved_0014; 1687 // 0x0018 AFE_DFX_RX_STS0 1688 U32 afe_dfx_rx_status0; 1689 // 0x001c AFE_DFX_RX_STS1 1690 U32 afe_dfx_rx_status1; 1691 // 0x0020 1692 U32 reserved_0020; 1693 // 0x0024 AFE_TX_CTRL 1694 U32 afe_tx_control; 1695 // 0x0028 AFE_TX_AMP_CTRL0 1696 U32 afe_tx_amp_control0; 1697 // 0x002c AFE_TX_AMP_CTRL1 1698 U32 afe_tx_amp_control1; 1699 // 0x0030 AFE_TX_AMP_CTRL2 1700 U32 afe_tx_amp_control2; 1701 // 0x0034 AFE_TX_AMP_CTRL3 1702 U32 afe_tx_amp_control3; 1703 // 0x0038 afe_tx_ssc_control 1704 U32 afe_tx_ssc_control; 1705 // 0x003c 1706 U32 reserved_003c; 1707 // 0x0040 AFE_RX_SSC_CTRL0 1708 U32 afe_rx_ssc_control0; 1709 // 0x0044 AFE_RX_SSC_CTRL1 1710 U32 afe_rx_ssc_control1; 1711 // 0x0048 AFE_RX_SSC_CTRL2 1712 U32 afe_rx_ssc_control2; 1713 // 0x004c AFE_RX_EQ_STS0 1714 U32 afe_rx_eq_status0; 1715 // 0x0050 AFE_RX_EQ_STS1 1716 U32 afe_rx_eq_status1; 1717 // 0x0054 AFE_RX_CDR_STS 1718 U32 afe_rx_cdr_status; 1719 // 0x0058 1720 U32 reserved_0058; 1721 // 0x005c AFE_CHAN_CTRL 1722 U32 afe_channel_control; 1723 // 0x0060-0x006c 1724 U32 reserved_0060_006c[0x04]; 1725 // 0x0070 AFE_XCVR_EC_STS0 1726 U32 afe_xcvr_error_capture_status0; 1727 // 0x0074 AFE_XCVR_EC_STS1 1728 U32 afe_xcvr_error_capture_status1; 1729 // 0x0078 AFE_XCVR_EC_STS2 1730 U32 afe_xcvr_error_capture_status2; 1731 // 0x007c afe_xcvr_ec_status3 1732 U32 afe_xcvr_error_capture_status3; 1733 // 0x0080 AFE_XCVR_EC_STS4 1734 U32 afe_xcvr_error_capture_status4; 1735 // 0x0084 AFE_XCVR_EC_STS5 1736 U32 afe_xcvr_error_capture_status5; 1737 // 0x0088-0x00fc 1738 U32 reserved_008c_00fc[0x1e]; 1739 }; 1740#else // !defined(PLEASANT_RIDGE_BUILD) && !defined(ARLINGTON_BUILD) 1741 #error "Target platform not defined." 1742#endif // defined(PLEASANT_RIDGE_BUILD) || defined(ARLINGTON_BUILD) 1743 1744/** 1745 * @struct SCU_AFE_REGISTERS 1746 * 1747 * @brief AFE Regsiters 1748 * See SCU AFE Specification for use of these registers. 1749 */ 1750#if defined(ARLINGTON_BUILD) 1751 typedef struct SCU_AFE_REGISTERS 1752 { 1753 // 0x0000 1754 U32 afe_pll_control; 1755 // 0x0004 1756 U32 afe_phase_interplator_control; 1757 // 0x0008 1758 U32 reservd_0008; 1759 // 0x000C 1760 U32 afe_bias_control[2]; 1761 // 0x0014 - 0x001c 1762 U32 reserved_0014_001c[3]; 1763 // 0x0020 1764 U32 afe_common_status; 1765 // 0x0024 1766 U32 afe_phase_interpolator_status; 1767 // 0x0028 - 0x003C 1768 U32 reserved_0028_003c[6]; 1769 // 0x0040 1770 U32 afe_transceiver_control0[4]; 1771 // 0x0050 1772 U32 afe_transceiver_control1[4]; 1773 // 0x0060 1774 U32 afe_transceiver_equalization_control[4]; 1775 // 0x0070 - 0x007c 1776 U32 reserved_0070_007c[4]; 1777 // 0x0080 1778 U32 afe_transceiver_cdr_status[4]; 1779 // 0x0090 1780 U32 afe_transceiver_rx_equaliation_status_register0[4]; 1781 // 0x00A0 1782 U32 afe_transceiver_rx_equaliation_status_register1[4]; 1783 // 0x00B0 - 0x0100 1784 U32 reserved_00b0_0100[0x15]; 1785 // 0x0104 1786 U32 afe_dfx_master_control; 1787 // 0x0108 1788 U32 reserved_0108; 1789 // 0x010c 1790 U32 afe_no_touch_leakage_control; 1791 // 0x0110 - 0x011C 1792 U32 reserved_0110_011c[4]; 1793 // 0x0120 1794 U32 afe_dfx_transceiver_status_clear; 1795 // 0x0124 1796 U32 afe_no_touch_leakage_status; 1797 // 0x0128 - 0x012c 1798 U32 reserved_0128_012c[2]; 1799 // 0x0130 1800 U32 afe_dfx_transceiver_status_register0[4]; 1801 // 0x0140 1802 U32 afe_dfx_transceiver_status_register1[4]; 1803 // 0x0150 1804 U32 afe_dfx_transmit_monitor_control; 1805 // 0x0154 - 0x017c 1806 U32 reserved_0154_017C[0x0B]; 1807 // 0x0180 1808 U32 afe_dfx_receive_control_register0[4]; 1809 // 0x0190 1810 U32 afe_dfx_receive_control_register1[4]; 1811 // 0x1A0 1812 U32 afe_dfx_transmit_control_register[4]; 1813 // 0x01B0 - 0x01BC 1814 U32 reserved_01b0_01bc[4]; 1815 // 0x01C0 1816 U32 afe_pll_dfx_control; 1817 // 0x01c4 - 0x01fc 1818 U32 reserved_01c4_01fc[0x0F]; 1819 // 0x0200 - 0x05fc 1820 struct SCU_AFE_TRANSCEIVER afe_transceiver[4]; 1821 1822 // 0x0600 - 0x06FC 1823 U32 reserved_0600_06FC[0x40]; 1824 1825 // 0x0700 1826 struct SCU_AFE_TRANSCEIVER afe_all_transceiver; 1827 1828 U32 reserved_0800_2000[0x600]; 1829 1830 } SCU_AFE_REGISTERS_T; 1831 1832#elif defined(PLEASANT_RIDGE_BUILD) \ 1833 || defined(PBG_HBA_A0_BUILD) \ 1834 || defined(PBG_HBA_A2_BUILD) \ 1835 || defined(PBG_HBA_BETA_BUILD) \ 1836 || defined(PBG_BUILD) 1837 1838 /* Uaoa AFE registers */ 1839 typedef struct SCU_AFE_REGISTERS 1840 { 1841 // 0Xe000 AFE_BIAS_CTRL 1842 U32 afe_bias_control; 1843 U32 reserved_0004; 1844 // 0x0008 AFE_PLL_CTRL0 1845 U32 afe_pll_control0; 1846 // 0x000c AFE_PLL_CTRL1 1847 U32 afe_pll_control1; 1848 // 0x0010 AFE_PLL_CTRL2 1849 U32 afe_pll_control2; 1850 // 0x0014 AFE_CB_STS 1851 U32 afe_common_block_status; 1852 // 0x0018-0x007c 1853 U32 reserved_18_7c[0x1a]; 1854 // 0x0080 AFE_PMSN_MCTRL0 1855 U32 afe_pmsn_master_control0; 1856 // 0x0084 AFE_PMSN_MCTRL1 1857 U32 afe_pmsn_master_control1; 1858 // 0x0088 AFE_PMSN_MCTRL2 1859 U32 afe_pmsn_master_control2; 1860 // 0x008C-0x00fc 1861 U32 reserved_008c_00fc[0x1D]; 1862 // 0x0100 AFE_DFX_MST_CTRL0 1863 U32 afe_dfx_master_control0; 1864 // 0x0104 AFE_DFX_MST_CTRL1 1865 U32 afe_dfx_master_control1; 1866 // 0x0108 AFE_DFX_DCL_CTRL 1867 U32 afe_dfx_dcl_control; 1868 // 0x010c AFE_DFX_DMON_CTRL 1869 U32 afe_dfx_digital_monitor_control; 1870 // 0x0110 AFE_DFX_AMONP_CTRL 1871 U32 afe_dfx_analog_p_monitor_control; 1872 // 0x0114 AFE_DFX_AMONN_CTRL 1873 U32 afe_dfx_analog_n_monitor_control; 1874 // 0x0118 AFE_DFX_NTL_STS 1875 U32 afe_dfx_ntl_status; 1876 // 0x011c AFE_DFX_FIFO_STS0 1877 U32 afe_dfx_fifo_status0; 1878 // 0x0120 AFE_DFX_FIFO_STS1 1879 U32 afe_dfx_fifo_status1; 1880 // 0x0124 AFE_DFX_MPAT_CTRL 1881 U32 afe_dfx_master_pattern_control; 1882 // 0x0128 AFE_DFX_P0_CTRL 1883 U32 afe_dfx_p0_control; 1884 // 0x012c-0x01a8 AFE_DFX_P0_DRx 1885 U32 afe_dfx_p0_data[32]; 1886 // 0x01ac 1887 U32 reserved_01ac; 1888 // 0x01b0-0x020c AFE_DFX_P0_IRx 1889 U32 afe_dfx_p0_instruction[24]; 1890 // 0x0210 1891 U32 reserved_0210; 1892 // 0x0214 AFE_DFX_P1_CTRL 1893 U32 afe_dfx_p1_control; 1894 // 0x0218-0x245 AFE_DFX_P1_DRx 1895 U32 afe_dfx_p1_data[16]; 1896 // 0x0258-0x029c 1897 U32 reserved_0258_029c[0x12]; 1898 // 0x02a0-0x02bc AFE_DFX_P1_IRx 1899 U32 afe_dfx_p1_instruction[8]; 1900 // 0x02c0-0x2fc 1901 U32 reserved_02c0_02fc[0x10]; 1902 // 0x0300 AFE_DFX_TX_PMSN_CTRL 1903 U32 afe_dfx_tx_pmsn_control; 1904 // 0x0304 AFE_DFX_RX_PMSN_CTRL 1905 U32 afe_dfx_rx_pmsn_control; 1906 U32 reserved_0308; 1907 // 0x030c AFE_DFX_NOA_CTRL0 1908 U32 afe_dfx_noa_control0; 1909 // 0x0310 AFE_DFX_NOA_CTRL1 1910 U32 afe_dfx_noa_control1; 1911 // 0x0314 AFE_DFX_NOA_CTRL2 1912 U32 afe_dfx_noa_control2; 1913 // 0x0318 AFE_DFX_NOA_CTRL3 1914 U32 afe_dfx_noa_control3; 1915 // 0x031c AFE_DFX_NOA_CTRL4 1916 U32 afe_dfx_noa_control4; 1917 // 0x0320 AFE_DFX_NOA_CTRL5 1918 U32 afe_dfx_noa_control5; 1919 // 0x0324 AFE_DFX_NOA_CTRL6 1920 U32 afe_dfx_noa_control6; 1921 // 0x0328 AFE_DFX_NOA_CTRL7 1922 U32 afe_dfx_noa_control7; 1923 // 0x032c-0x07fc 1924 U32 reserved_032c_07fc[0x135]; 1925 1926 // 0x0800-0x0bfc 1927 struct SCU_AFE_TRANSCEIVER scu_afe_xcvr[4]; 1928 1929 // 0x0c00-0x0ffc 1930 U32 reserved_0c00_0ffc[0x0100]; 1931 } SCU_AFE_REGISTERS_T; 1932#else // !defined(PBG_HBA_BUILD) && defined(PLEASANT_RIDGE_BUILD) && !defined(ARLINGTON_BUILD) 1933 #error "Target platform not defined." 1934#endif // defined(PBG_HBA_BUILD) || defined(PLEASANT_RIDGE_BUILD) || defined(ARLINGTON_BUILD) 1935 1936 1937struct SCU_PROTOCOL_ENGINE_GROUP_REGISTERS 1938{ 1939 U32 table[0xE0]; 1940}; 1941 1942 1943struct SCU_VIIT_IIT 1944{ 1945 U32 table[256]; 1946}; 1947 1948/** 1949 * @brief Placeholder for the ZONE Partition Table information 1950 * ZONING will not be included in the 1.1 release. 1951 * 1952 */ 1953struct SCU_ZONE_PARTITION_TABLE 1954{ 1955 U32 table[2048]; 1956}; 1957 1958/** 1959 * @brief CRAM register. MMR base address for CRAMC is 0x6400 1960 * relative to SCUBAR. 1961 * 1962 */ 1963struct SCU_COMPLETION_RAM 1964{ 1965 U32 sram_base_address_0; //0x0000 1966 U32 sram_upper_base_address_0; //0x0004 1967 U32 sram_ecc_control_0; //0x0008 1968 U32 sram_ecc_log_0; //0x000c 1969 U32 sram_ecc_addrress_0; //0x0010 1970 U32 sram_ecc_context_address_0; //0x0014 1971 U32 sram_ecc_test_0; //0x0018 1972 U32 sram_parity_control_and_status_0; //0x001C 1973 U32 sram_parity_address_0; //0x0020 1974 U32 sram_parity_upper_address_0; //0x0024 1975 U32 sram_parity_context_0; //0x0028 1976 U32 sram_memory_controller_interrupt_status_0; //0x002C 1977 U32 sram_mcu_read_arbiter_control_0; //0x0030 1978 U32 sram_mcu_write_arbiter_control_0; //0x0034 1979 U32 smcu_error_event_counter_0_0; //0x0038 1980 1981 //Remainder CRAM register space 1982 U32 reserved_003C_0200[113]; 1983}; 1984 1985/** 1986 * @brief FBRAM registers. MMR base address for FBRAM is 1987 * 0x6600 relative to SCUBAR. 1988 */ 1989struct SCU_FRAME_BUFFER_RAM 1990{ 1991 U32 sram_base_address_1; //0x0000 1992 U32 sram_upper_base_address_1; //0x0004 1993 U32 sram_ecc_control_1; //0x0008 1994 U32 sram_ecc_log_1; //0x000c 1995 U32 sram_ecc_addrress_1; //0x0010 1996 U32 sram_ecc_context_address_1; //0x0014 1997 U32 sram_ecc_test_1; //0x0018 1998 U32 sram_parity_control_and_status_1; //0x001C 1999 U32 sram_parity_address_1; //0x0020 2000 U32 sram_parity_upper_address_1; //0x0024 2001 U32 sram_parity_context_1; //0x0028 2002 U32 sram_memory_controller_interrupt_status_1; //0x002C 2003 U32 sram_mcu_read_arbiter_control_1; //0x0030 2004 U32 sram_mcu_write_arbiter_control_1; //0x0034 2005 U32 smcu_error_event_counter_0_1; //0x0038 2006 2007 //Remainder of FBRAM register space 2008 U32 reserved_003C_0200[113]; 2009}; 2010 2011#define SCU_SCRATCH_RAM_SIZE_IN_DWORDS 256 2012 2013/** 2014* @brief Placeholder for the scratch RAM registers. 2015* 2016*/ 2017struct SCU_SCRATCH_RAM 2018{ 2019 U32 ram[SCU_SCRATCH_RAM_SIZE_IN_DWORDS]; 2020}; 2021 2022/** 2023 * @brief Placeholder since I am not yet sure what these registers are here 2024 * for. 2025 * 2026 */ 2027struct NOA_PROTOCOL_ENGINE_PARTITION 2028{ 2029 U32 reserved[64]; 2030}; 2031 2032/** 2033 * @brief Placeholder since I am not yet sure what these registers are here 2034 * for. 2035 * 2036 */ 2037struct NOA_HUB_PARTITION 2038{ 2039 U32 reserved[64]; 2040}; 2041 2042/** 2043 * @brief Placeholder since I am not yet sure what these registers are here 2044 * for. 2045 * 2046 */ 2047struct NOA_HOST_INTERFACE_PARTITION 2048{ 2049 U32 reserved[64]; 2050}; 2051 2052/** 2053 * @struct TRANSPORT_LINK_LAYER_PAIR 2054 * 2055 * @brief The SCU Hardware pairs up the TL registers with the LL registers 2056 * so we must place them adjcent to make the array of registers in 2057 * the PEG. 2058 * 2059 */ 2060struct TRANSPORT_LINK_LAYER_PAIR 2061{ 2062 struct SCU_TRANSPORT_LAYER_REGISTERS tl; 2063 struct SCU_LINK_LAYER_REGISTERS ll; 2064}; 2065 2066/** 2067 * @struct SCU_PEG_REGISTERS 2068 * 2069 * @brief SCU Protocol Engine Memory mapped register space. These 2070 * registers are unique to each protocol engine group. There can be 2071 * at most two PEG for a single SCU part. 2072 * 2073 */ 2074struct SCU_PEG_REGISTERS 2075{ 2076 struct TRANSPORT_LINK_LAYER_PAIR pe[4]; 2077 struct SCU_PORT_TASK_SCHEDULER_GROUP_REGISTERS ptsg; 2078 struct SCU_PROTOCOL_ENGINE_GROUP_REGISTERS peg; 2079 struct SCU_SGPIO_REGISTERS sgpio; 2080 U32 reserved_01500_1BFF[0x1C0]; 2081 struct SCU_VIIT_ENTRY viit[64]; 2082 struct SCU_ZONE_PARTITION_TABLE zpt0; 2083 struct SCU_ZONE_PARTITION_TABLE zpt1; 2084}; 2085 2086/** 2087 * @struct SCU_REGISTERS 2088 * 2089 * @brief SCU regsiters including both PEG registers if we turn on that 2090 * compile option. 2091 * All of these registers are in the memory mapped space returned 2092 * from BAR1. 2093 * See SCU SMU Specification for how these registers are mapped. 2094 * 2095 */ 2096typedef struct SCU_REGISTERS 2097{ 2098 // 0x0000 - PEG 0 2099 struct SCU_PEG_REGISTERS peg0; 2100 2101 // 0x6000 - SDMA and Miscellaneous 2102 struct SCU_SDMA_REGISTERS sdma; 2103 struct SCU_COMPLETION_RAM cram; 2104 struct SCU_FRAME_BUFFER_RAM fbram; 2105 U32 reserved_6800_69FF[0x80]; 2106 struct NOA_PROTOCOL_ENGINE_PARTITION noa_pe; 2107 struct NOA_HUB_PARTITION noa_hub; 2108 struct NOA_HOST_INTERFACE_PARTITION noa_if; 2109 U32 reserved_6d00_7fff[0x4c0]; 2110 2111 // 0x8000 - PEG 1 2112 struct SCU_PEG_REGISTERS peg1; 2113 2114 // 0xE000 - AFE Registers 2115 struct SCU_AFE_REGISTERS afe; 2116 2117} SCU_REGISTERS_T; 2118 2119#ifdef __cplusplus 2120} 2121#endif 2122 2123#endif // _SCU_REGISTERS_HEADER_ 2124