Lines Matching refs:UL
278 #define UEAFSR_BLK (1UL << 23) /* Error caused by block transaction */
279 #define UEAFSR_P_DTE (1UL << 56) /* Pri. DVMA translation error */
280 #define UEAFSR_S_DTE (1UL << 57) /* Sec. DVMA translation error */
281 #define UEAFSR_S_DWR (1UL << 58) /* Sec. error during DVMA write */
282 #define UEAFSR_S_DRD (1UL << 59) /* Sec. error during DVMA read */
283 #define UEAFSR_S_PIO (1UL << 60) /* Sec. error during PIO access */
284 #define UEAFSR_P_DWR (1UL << 61) /* Pri. error during DVMA write */
285 #define UEAFSR_P_DRD (1UL << 62) /* Pri. error during DVMA read */
286 #define UEAFSR_P_PIO (1UL << 63) /* Pri. error during PIO access */
289 #define CEAFSR_BLK (1UL << 23) /* Error caused by block transaction */
290 #define CEAFSR_S_DWR (1UL << 58) /* Sec. error caused by DVMA write */
291 #define CEAFSR_S_DRD (1UL << 59) /* Sec. error caused by DVMA read */
292 #define CEAFSR_S_PIO (1UL << 60) /* Sec. error caused by PIO access */
293 #define CEAFSR_P_DWR (1UL << 61) /* Pri. error caused by DVMA write */
294 #define CEAFSR_P_DRD (1UL << 62) /* Pri. error caused by DVMA read */
295 #define CEAFSR_P_PIO (1UL << 63) /* Pri. error caused by PIO access */
298 #define PCIAFSR_P_MA (1UL << 63) /* Pri. master abort */
299 #define PCIAFSR_P_TA (1UL << 62) /* Pri. target abort */
300 #define PCIAFSR_P_RTRY (1UL << 61) /* Pri. excessive retries */
301 #define PCIAFSR_P_RERR (1UL << 60) /* Pri. parity error */
302 #define PCIAFSR_S_MA (1UL << 59) /* Sec. master abort */
303 #define PCIAFSR_S_TA (1UL << 58) /* Sec. target abort */
304 #define PCIAFSR_S_RTRY (1UL << 57) /* Sec. excessive retries */
305 #define PCIAFSR_S_RERR (1UL << 56) /* Sec. parity error */
307 #define PCIAFSR_BLK (1UL << 31) /* failed pri. transfer was block r/w */