Lines Matching refs:UL
38 #define TLB_DIRECT_ADDRESS_MASK ((1UL << TLB_DIRECT_ADDRESS_BITS) - 1)
39 #define TLB_DIRECT_PAGE_MASK ((1UL << TLB_DIRECT_PAGE_BITS) - 1)
69 (((1UL << TLB_CXR_CTX_BITS) - 1) << TLB_CXR_CTX_SHIFT)
92 (((1UL << TLB_TAE_PGSZ_BITS) - 1) << TLB_TAE_PGSZ0_SHIFT)
94 (((1UL << TLB_TAE_PGSZ_BITS) - 1) << TLB_TAE_PGSZ1_SHIFT)
138 (((sfsr) >> MMU_SFSR_ASI_SHIFT) & ((1UL << MMU_SFSR_ASI_SIZE) - 1))
140 (((sfsr) >> MMU_SFSR_FT_SHIFT) & ((1UL << MMU_SFSR_FT_SIZE) - 1))
142 (((sfsr) >> MMU_SFSR_CT_SHIFT) & ((1UL << MMU_SFSR_CT_SIZE) - 1))
144 #define MMU_SFSR_E (1UL << MMU_SFSR_E_SHIFT)
145 #define MMU_SFSR_PR (1UL << MMU_SFSR_PR_SHIFT)
146 #define MMU_SFSR_W (1UL << MMU_SFSR_W_SHIFT)
147 #define MMU_SFSR_OW (1UL << MMU_SFSR_OW_SHIFT)
148 #define MMU_SFSR_FV (1UL << MMU_SFSR_FV_SHIFT)