/freebsd-11-stable/sys/arm/xscale/ixp425/ |
H A D | ixp425_wdog.c | 58 WR4(struct ixpwdog_softc *sc, bus_size_t off, uint32_t val) function 69 WR4(sc, IXP425_OST_WDOG_KEY, OST_WDOG_KEY_MAJICK); 71 WR4(sc, IXP425_OST_WDOG_ENAB, 0); 73 WR4(sc, IXP425_OST_WDOG, 2<<(u - 4)); 75 WR4(sc, IXP425_OST_WDOG_ENAB, 80 WR4(sc, IXP425_OST_WDOG_ENAB, 0); 82 WR4(sc, IXP425_OST_WDOG_KEY, 0);
|
/freebsd-11-stable/sys/arm/at91/ |
H A D | at91_spi.c | 84 WR4(struct at91_spi_softc *sc, bus_size_t off, uint32_t val) function 147 WR4(sc, SPI_CR, SPI_CR_SWRST); 149 WR4(sc, SPI_CR, SPI_CR_SWRST); 150 WR4(sc, SPI_IDR, 0xffffffff); 152 WR4(sc, SPI_MR, (0xf << 24) | SPI_MR_MSTR | SPI_MR_MODFDIS | 172 WR4(sc, SPI_CSR0, csr); 173 WR4(sc, SPI_CSR1, csr); 174 WR4(sc, SPI_CSR2, csr); 175 WR4(sc, SPI_CSR3, csr); 177 WR4(s [all...] |
H A D | at91_aic.c | 68 WR4(struct aic_softc *sc, bus_size_t off, uint32_t val) function 78 WR4(sc, IC_IDCR, 1 << nb); 90 WR4(sc, IC_EOICR, 1); 100 WR4(sc, IC_IECR, 1 << nb); 101 WR4(sc, IC_EOICR, 0); 138 WR4(sc, IC_SVR + i * 4, i); 140 WR4(sc, IC_SMR + i * 4, soc_info.soc_data->soc_irq_prio[i]); 142 WR4(sc, IC_EOICR, 1); 145 WR4(sc, IC_SPU, 32); 147 WR4(s [all...] |
H A D | at91_mci.c | 190 WR4(struct at91_mci_softc *sc, bus_size_t off, uint32_t val) function 243 WR4(sc, PDC_PTCR, PDC_PTCR_TXTDIS | PDC_PTCR_RXTDIS); 244 WR4(sc, PDC_RPR, 0); 245 WR4(sc, PDC_RCR, 0); 246 WR4(sc, PDC_RNPR, 0); 247 WR4(sc, PDC_RNCR, 0); 248 WR4(sc, PDC_TPR, 0); 249 WR4(sc, PDC_TCR, 0); 250 WR4(sc, PDC_TNPR, 0); 251 WR4(s [all...] |
H A D | at91_rtc.c | 87 WR4(struct at91_rtc_softc *sc, bus_size_t off, uint32_t val) function 123 WR4(sc, RTC_SCCR, status); 159 WR4(sc, RTC_IDR, 0xffffffff); 160 WR4(sc, RTC_SCCR, 0x1f); 161 WR4(sc, RTC_MR, 0); 179 WR4(sc, RTC_CALR, 0); 232 WR4(sc, RTC_IDR, 0xffffffff); 318 WR4(sc, RTC_CR, RTC_CR_UPDCAL | RTC_CR_UPDTIM); 321 WR4(sc, RTC_SCCR, RTC_SR_ACKUPD); 327 WR4(s [all...] |
H A D | uart_dev_at91usart.c | 86 #define WR4(bas, reg, value) \ macro 199 WR4(bas, USART_MR, mr); 205 WR4(bas, USART_BRGR, BAUD2DIVISOR(baudrate)); 216 WR4(bas, USART_RTOR, 20); 218 WR4(bas, USART_RTOR, baudrate / 2000); 219 WR4(bas, USART_CR, USART_CR_STTTO); 290 WR4(bas, USART_CR, USART_CR_RSTSTA | USART_CR_RSTRX | USART_CR_RSTTX); 291 WR4(bas, USART_CR, USART_CR_RXEN | USART_CR_TXEN); 292 WR4(bas, USART_IDR, 0xffffffff); 316 WR4(ba [all...] |
H A D | at91_pio.c | 84 WR4(struct at91_pio_softc *sc, bus_size_t off, uint32_t val) function 185 WR4(sc, PIO_IDR, 0xffffffff); 368 WR4(sc, PIO_SODR, datapin); 370 WR4(sc, PIO_CODR, datapin); 372 WR4(sc, PIO_CODR, clockpin); 373 WR4(sc, PIO_SODR, clockpin); 385 WR4(sc, PIO_SODR, datapin); 387 WR4(sc, PIO_CODR, datapin); 389 WR4(sc, PIO_CODR, clockpin); 390 WR4(s [all...] |
H A D | at91_st.c | 70 WR4(bus_size_t off, uint32_t val) function 148 WR4(ST_WDMR, ST_WDMR_RSTEN | 2); 149 WR4(ST_CR, ST_CR_WDRST); 196 WR4(ST_IDR, 0xffffffff); 281 WR4(ST_WDMR, wdog); 282 WR4(ST_CR, ST_CR_WDRST); 294 WR4(ST_RTMR, 1); 296 WR4(ST_WDMR, 0); 307 WR4(ST_PIMR, rel_value); 310 WR4(ST_IE [all...] |
H A D | at91_twi.c | 83 WR4(struct at91_twi_softc *sc, bus_size_t off, uint32_t val) function 158 WR4(sc, TWI_CR, TWI_CR_SWRST); 159 WR4(sc, TWI_CR, TWI_CR_MSEN | TWI_CR_SVDIS); 160 WR4(sc, TWI_CWGR, sc->cwgr); 249 WR4(sc, TWI_IDR, status); 305 WR4(sc, TWI_CR, TWI_CR_SWRST); 306 WR4(sc, TWI_CR, TWI_CR_MSEN | TWI_CR_SVDIS); 307 WR4(sc, TWI_CWGR, sc->cwgr); 355 WR4(sc, TWI_MMR, TWI_MMR_DADR(msgs[i].slave) | rdwr); 364 WR4(s [all...] |
H A D | if_ate.c | 174 WR4(struct ate_softc *sc, bus_size_t off, uint32_t val) function 528 WR4(sc, ETH_HSL, 0xffffffff); 529 WR4(sc, ETH_HSH, 0xffffffff); 553 WR4(sc, ETH_HSL, mcaf[0]); 554 WR4(sc, ETH_HSH, mcaf[1]); 633 WR4(sc, ETH_RBQP, sc->rx_desc_phys); 671 WR4(sc, ETHB_TBQP, sc->tx_desc_phys); 674 WR4(sc, ETHB_UIO, RD4(sc, ETHB_UIO) | ETHB_UIO_CLKE); 740 WR4(sc, ETHB_UIO, RD4(sc, ETHB_UIO) & ~ETHB_UIO_CLKE); 791 WR4(s [all...] |
H A D | at91_ssc.c | 61 WR4(struct at91_ssc_softc *sc, bus_size_t off, uint32_t val) function 142 WR4(sc, SSC_CR, SSC_CR_SWRST); 143 WR4(sc, SSC_CMR, 0); // clock divider unused 144 WR4(sc, SSC_RCMR, 146 WR4(sc, SSC_RFMR, 148 WR4(sc, SSC_TCMR, 150 WR4(sc, SSC_TFMR,
|
H A D | at91_rst.c | 75 WR4(struct at91_rst_softc *sc, bus_size_t off, uint32_t val) function 91 WR4(at91_rst_sc, RST_MR, 94 WR4(at91_rst_sc, RST_CR, 154 WR4(at91_rst_sc, RST_MR, RST_MR_ERSTL(0xd) | RST_MR_URSIEN | RST_MR_KEY);
|
/freebsd-11-stable/sys/arm/freescale/imx/ |
H A D | imx6_ccm.c | 73 WR4(struct ccm_softc *sc, bus_size_t off, uint32_t val) function 95 WR4(sc, CCM_CCGR0, reg); 100 WR4(sc, CCM_CCGR1, reg); 107 WR4(sc, CCM_CCGR2, reg); 112 WR4(sc, CCM_CCGR3, reg); 117 WR4(sc, CCM_CCGR4, reg); 122 WR4(sc, CCM_CCGR5, reg); 127 WR4(sc, CCM_CCGR6, reg); 179 WR4(sc, CCM_CGPR, reg); 182 WR4(s [all...] |
H A D | imx_epit.c | 147 WR4(struct epit_softc *sc, bus_size_t offset, uint32_t value) function 208 WR4(sc, EPIT_LR, 0xffffffff); 209 WR4(sc, EPIT_CR, sc->ctlreg | EPIT_CR_EN); 242 WR4(sc, EPIT_CR, sc->ctlreg); 243 WR4(sc, EPIT_SR, EPIT_SR_OCIF); 255 WR4(sc, EPIT_LR, ticks); 269 WR4(sc, EPIT_CR, sc->ctlreg); 294 WR4(sc, EPIT_CR, sc->ctlreg); 458 WR4(sc, EPIT_CR, 0);
|
/freebsd-11-stable/sys/arm/nvidia/drm2/ |
H A D | tegra_dc.c | 58 #define WR4(_sc, _r, _v) bus_write_4((_sc)->mem_res, 4 * (_r), (_v)) macro 429 WR4(sc, DC_CMD_DISPLAY_WINDOW_HEADER, val); 432 WR4(sc, DC_WIN_POSITION, WIN_POSITION(win->dst_x, win->dst_y)); 433 WR4(sc, DC_WIN_SIZE, WIN_SIZE(win->dst_w, win->dst_h)); 434 WR4(sc, DC_WIN_PRESCALED_SIZE, WIN_PRESCALED_SIZE(h_size, v_size)); 437 WR4(sc, DC_WIN_DDA_INCREMENT, 439 WR4(sc, DC_WIN_H_INITIAL_DDA, h_init_dda); 440 WR4(sc, DC_WIN_V_INITIAL_DDA, v_init_dda); 443 WR4(sc, DC_WINBUF_START_ADDR, win->base[0]); 445 WR4(s [all...] |
H A D | tegra_hdmi.c | 61 #define WR4(_sc, _r, _v) bus_write_4((_sc)->mem_res, 4 * (_r), (_v)) macro 359 WR4(sc, HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_HEADER, 361 WR4(sc, HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK0_LOW, 363 WR4(sc, HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH, 365 WR4(sc, HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK1_LOW, 367 WR4(sc, HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH, 370 WR4(sc, HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL, 391 WR4(sc, HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_HEADER, 393 WR4(sc, HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_SUBPACK0_LOW, 395 WR4(s [all...] |
/freebsd-11-stable/sys/arm/allwinner/ |
H A D | aw_thermal.c | 116 #define WR4(sc, reg, val) bus_write_4((sc)->res, (reg), (val)) macro 130 WR4(sc, THS_CALIB0, calib0); 131 WR4(sc, THS_CALIB1, calib1); 134 WR4(sc, THS_CTRL0, ADC_ACQUIRE_TIME); 135 WR4(sc, THS_CTRL2, (ADC_ACQUIRE_TIME << SENSOR_ACQ1_SHIFT) | 139 WR4(sc, THS_INTC, 0); 140 WR4(sc, THS_INTS, RD4(sc, THS_INTS)); 143 WR4(sc, THS_FILTER, RD4(sc, THS_FILTER) | FILTER_EN);
|
/freebsd-11-stable/sys/dev/ffec/ |
H A D | if_ffec.c | 230 WR4(struct ffec_softc *sc, bus_size_t off, uint32_t val) function 323 WR4(sc, FEC_IER_REG, FEC_IER_MII); 325 WR4(sc, FEC_MMFR_REG, FEC_MMFR_OP_READ | 347 WR4(sc, FEC_IER_REG, FEC_IER_MII); 349 WR4(sc, FEC_MMFR_REG, FEC_MMFR_OP_WRITE | 435 WR4(sc, FEC_RCR_REG, rcr); 436 WR4(sc, FEC_TCR_REG, tcr); 437 WR4(sc, FEC_ECR_REG, ecr); 489 WR4(sc, FEC_MIBC_REG, mibc | FEC_MIBC_CLEAR); 490 WR4(s [all...] |
/freebsd-11-stable/sys/arm/xilinx/ |
H A D | uart_dev_cdnc.c | 59 #define WR4(bas, reg, value) \ macro 212 WR4(bas, CDNC_UART_BAUDDIV_REG, best_bauddiv); 213 WR4(bas, CDNC_UART_BAUDGEN_REG, best_baudgen); 260 WR4(bas, CDNC_UART_MODE_REG, mode_reg_value); 273 WR4(bas, CDNC_UART_CTRL_REG, 277 WR4(bas, CDNC_UART_IDIS_REG, CDNC_UART_INT_ALL); 278 WR4(bas, CDNC_UART_ISTAT_REG, CDNC_UART_INT_ALL); 281 WR4(bas, CDNC_UART_MODEM_STAT_REG, 286 WR4(bas, CDNC_UART_RX_WATER_REG, UART_FIFO_SIZE/2); 287 WR4(ba [all...] |
H A D | zy7_slcr.c | 77 #define WR4(sc, off, val) (bus_write_4((sc)->mem_res, (off), (val))) macro 116 WR4(sc, ZY7_SLCR_UNLOCK, ZY7_SLCR_UNLOCK_MAGIC); 124 WR4(sc, ZY7_SLCR_LOCK, ZY7_SLCR_LOCK_MAGIC); 138 WR4(sc, ZY7_SLCR_REBOOT_STAT, 142 WR4(sc, ZY7_SLCR_PSS_RST_CTRL, ZY7_SLCR_PSS_RST_CTRL_SOFT_RESET); 165 WR4(sc, ZY7_SLCR_FPGA_RST_CTRL, ZY7_SLCR_FPGA_RST_CTRL_RST_ALL); 168 WR4(sc, ZY7_SLCR_LVL_SHFTR_EN, 0); 196 WR4(sc, ZY7_SLCR_LVL_SHFTR_EN, ZY7_SLCR_LVL_SHFTR_EN_ALL); 199 WR4(sc, ZY7_SLCR_FPGA_RST_CTRL, 0); 241 WR4(s [all...] |
H A D | zy7_devcfg.c | 101 #define WR4(sc, off, val) (bus_write_4((sc)->mem_res, (off), (val))) macro 404 WR4(sc, ZY7_DEVCFG_CTRL, 417 WR4(sc, ZY7_DEVCFG_MCTRL, RD4(sc, ZY7_DEVCFG_MCTRL) & 433 WR4(sc, ZY7_DEVCFG_INT_STATUS, ZY7_DEVCFG_INT_ALL); 434 WR4(sc, ZY7_DEVCFG_INT_MASK, ~ZY7_DEVCFG_INT_PCFG_INIT_PE); 438 WR4(sc, ZY7_DEVCFG_CTRL, devcfg_ctl); 447 WR4(sc, ZY7_DEVCFG_INT_MASK, ~0); 458 WR4(sc, ZY7_DEVCFG_CTRL, devcfg_ctl); 470 WR4(sc, ZY7_DEVCFG_INT_STATUS, ZY7_DEVCFG_INT_ALL); 471 WR4(s [all...] |
H A D | zy7_gpio.c | 97 #define WR4(sc, off, val) bus_write_4((sc)->mem_res, (off), (val)) macro 207 WR4(sc, ZY7_GPIO_DIRM(pin >> 5), 211 WR4(sc, ZY7_GPIO_OEN(pin >> 5), 215 WR4(sc, ZY7_GPIO_OEN(pin >> 5), 220 WR4(sc, ZY7_GPIO_DIRM(pin >> 5), 222 WR4(sc, ZY7_GPIO_OEN(pin >> 5), 242 WR4(sc, ZY7_GPIO_MASK_DATA_MSW(pin >> 5), 246 WR4(sc, ZY7_GPIO_MASK_DATA_LSW(pin >> 5), 278 WR4(sc, ZY7_GPIO_DATA(pin >> 5),
|
/freebsd-11-stable/sys/arm/nvidia/tegra124/ |
H A D | tegra124_clk_pll.c | 423 WR4(sc, sc->base_reg, reg); 436 WR4(sc, sc->base_reg, reg); 574 WR4(sc, sc->base_reg, reg); 579 WR4(sc, PLLE_AUX, reg); 589 WR4(sc, sc->misc_reg, reg); 594 WR4(sc, PLLE_SS_CNTL, reg); 600 WR4(sc, sc->base_reg, reg); 613 WR4(sc, PLLE_SS_CNTL, reg); 616 WR4(sc, PLLE_SS_CNTL, reg); 620 WR4(s [all...] |
H A D | tegra124_xusbpadctl.c | 177 #define WR4(_sc, _r, _v) bus_write_4((_sc)->mem_res, (_r), (_v)) macro 383 WR4(sc, XUSB_PADCTL_SS_PORT_MAP, reg); 392 WR4(sc, XUSB_PADCTL_IOPHY_USB3_PAD_CTL2(port->idx), reg); 394 WR4(sc, XUSB_PADCTL_IOPHY_USB3_PAD_CTL4(port->idx), 399 WR4(sc, XUSB_PADCTL_ELPG_PROGRAM, reg); 404 WR4(sc, XUSB_PADCTL_ELPG_PROGRAM, reg); 409 WR4(sc, XUSB_PADCTL_ELPG_PROGRAM, reg); 423 WR4(sc, XUSB_PADCTL_IOPHY_PLL_P0_CTL1, reg); 430 WR4(sc, XUSB_PADCTL_IOPHY_PLL_P0_CTL2, reg); 435 WR4(s [all...] |
/freebsd-11-stable/sys/arm/nvidia/ |
H A D | tegra_rtc.c | 78 #define WR4(_sc, _r, _v) bus_write_4((_sc)->mem_res, (_r), (_v)) macro 158 WR4(sc, RTC_SECONDS, tv.tv_sec); 174 WR4(sc, RTC_INTR_STATUS, status); 234 WR4(sc, RTC_SECONDS_ALARM0, 0); 235 WR4(sc, RTC_SECONDS_ALARM1, 0); 236 WR4(sc, RTC_INTR_STATUS, 0xFFFFFFFF); 237 WR4(sc, RTC_INTR_MASK, 0);
|