arm/at91/if_ate.c

174 WR4(struct ate_softc *sc, bus_size_t off, uint32_t val)
528 		WR4(sc, ETH_HSL, 0xffffffff);
529 		WR4(sc, ETH_HSH, 0xffffffff);
553 	WR4(sc, ETH_HSL, mcaf[0]);
554 	WR4(sc, ETH_HSH, mcaf[1]);
633 	WR4(sc, ETH_RBQP, sc->rx_desc_phys);
671 		WR4(sc, ETHB_TBQP, sc->tx_desc_phys);
674 		WR4(sc, ETHB_UIO, RD4(sc, ETHB_UIO) | ETHB_UIO_CLKE);
740 		WR4(sc, ETHB_UIO, RD4(sc, ETHB_UIO) & ~ETHB_UIO_CLKE);
791 	WR4(sc, ETH_CFG, reg);
865 	WR4(sc, ETH_SA1L, (eaddr[3] << 24) | (eaddr[2] << 16) |
867 	WR4(sc, ETH_SA1H, (eaddr[5] << 8) | (eaddr[4]));
977 			WR4(sc, ETH_RSR, RD4(sc, ETH_RSR));	/* Reset status */
1067 		WR4(sc, ETH_CTL, reg & ~ETH_CTL_RE);
1069 		WR4(sc, ETH_CTL, reg | ETH_CTL_RE);
1111 		WR4(sc, ETH_CFG, reg);
1116 		WR4(sc, ETHB_UIO, reg);
1131 		WR4(sc, ETHB_TBQP, sc->tx_desc_phys);
1137 	WR4(sc, ETH_CTL, RD4(sc, ETH_CTL) | ETH_CTL_TE | ETH_CTL_RE);
1138 	WR4(sc, ETH_IER, ETH_ISR_RCOM | ETH_ISR_TCOM | ETH_ISR_RBNA);
1141 	WR4(sc, ETH_CFG, RD4(sc, ETH_CFG) | ETH_CFG_BIG);
1228 			WR4(sc, ETH_TAR, segs[0].ds_addr);
1230 			WR4(sc, ETH_TCR, segs[0].ds_len);
1240 			WR4(sc, ETH_CTL, RD4(sc, ETH_CTL) | ETHB_CTL_TGO);
1297 	WR4(sc, ETH_CTL, ETH_CTL_MPE);
1307 		WR4(sc, ETH_CFG, ETH_CFG_CLK_8);
1309 		WR4(sc, ETH_CFG, ETH_CFG_CLK_16);
1311 		WR4(sc, ETH_CFG, ETH_CFG_CLK_32);
1313 		WR4(sc, ETH_CFG, ETH_CFG_CLK_64);
1319 	WR4(sc, ETH_IDR, 0xffffffff);
1326 	WR4(sc, ETH_TSR, 0xffffffff);
1327 	WR4(sc, ETH_RSR, 0xffffffff);
1342 		WR4(sc, ETHB_UIO, RD4(sc, ETHB_UIO) & ~ETHB_UIO_CLKE);
1380 	WR4(sc, ETH_CFG, reg);
1436 				WR4(sc, ETH_CFG, RD4(sc, ETH_CFG) | ETH_CFG_BIG);
1439 				WR4(sc, ETH_CFG, RD4(sc, ETH_CFG) & ~ETH_CFG_BIG);
1477 	WR4(sc, ETH_MAN, ETH_MAN_REG_RD(phy, reg));
1496 	WR4(sc, ETH_MAN, ETH_MAN_REG_WR(phy, reg, data));