1/*- 2 * Copyright (c) 2016 Michal Meloun <mmel@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27#include <sys/cdefs.h> 28__FBSDID("$FreeBSD: stable/11/sys/arm/nvidia/tegra_rtc.c 308335 2016-11-05 10:56:32Z mmel $"); 29 30/* 31 * RTC driver for Tegra SoCs. 32 */ 33#include <sys/param.h> 34#include <sys/systm.h> 35#include <sys/bus.h> 36#include <sys/clock.h> 37#include <sys/kernel.h> 38#include <sys/limits.h> 39#include <sys/lock.h> 40#include <sys/mutex.h> 41#include <sys/module.h> 42#include <sys/resource.h> 43 44#include <machine/bus.h> 45#include <machine/resource.h> 46#include <sys/rman.h> 47 48#include <dev/extres/clk/clk.h> 49#include <dev/fdt/fdt_common.h> 50#include <dev/ofw/ofw_bus.h> 51#include <dev/ofw/ofw_bus_subr.h> 52 53#include "clock_if.h" 54 55#define RTC_CONTROL 0x00 56#define RTC_BUSY 0x04 57#define RTC_BUSY_STATUS (1 << 0) 58#define RTC_SECONDS 0x08 59#define RTC_SHADOW_SECONDS 0x0c 60#define RTC_MILLI_SECONDS 0x10 61#define RTC_SECONDS_ALARM0 0x14 62#define RTC_SECONDS_ALARM1 0x18 63#define RTC_MILLI_SECONDS_ALARM 0x1c 64#define RTC_SECONDS_COUNTDOWN_ALARM 0x20 65#define RTC_MILLI_SECONDS_COUNTDOW_ALARM 0x24 66#define RTC_INTR_MASK 0x28 67#define RTC_INTR_MSEC_CDN_ALARM (1 << 4) 68#define RTC_INTR_SEC_CDN_ALARM (1 << 3) 69#define RTC_INTR_MSEC_ALARM (1 << 2) 70#define RTC_INTR_SEC_ALARM1 (1 << 1) 71#define RTC_INTR_SEC_ALARM0 (1 << 0) 72 73#define RTC_INTR_STATUS 0x2c 74#define RTC_INTR_SOURCE 0x30 75#define RTC_INTR_SET 0x34 76#define RTC_CORRECTION_FACTOR 0x38 77 78#define WR4(_sc, _r, _v) bus_write_4((_sc)->mem_res, (_r), (_v)) 79#define RD4(_sc, _r) bus_read_4((_sc)->mem_res, (_r)) 80 81#define LOCK(_sc) mtx_lock(&(_sc)->mtx) 82#define UNLOCK(_sc) mtx_unlock(&(_sc)->mtx) 83#define SLEEP(_sc, timeout) \ 84 mtx_sleep(sc, &sc->mtx, 0, "rtcwait", timeout); 85#define LOCK_INIT(_sc) \ 86 mtx_init(&_sc->mtx, device_get_nameunit(_sc->dev), "tegra_rtc", MTX_DEF) 87#define LOCK_DESTROY(_sc) mtx_destroy(&_sc->mtx) 88#define ASSERT_LOCKED(_sc) mtx_assert(&_sc->mtx, MA_OWNED) 89#define ASSERT_UNLOCKED(_sc) mtx_assert(&_sc->mtx, MA_NOTOWNED) 90 91static struct ofw_compat_data compat_data[] = { 92 {"nvidia,tegra124-rtc", 1}, 93 {NULL, 0} 94}; 95 96struct tegra_rtc_softc { 97 device_t dev; 98 struct mtx mtx; 99 100 struct resource *mem_res; 101 struct resource *irq_res; 102 void *irq_h; 103 104 clk_t clk; 105 uint32_t core_freq; 106}; 107 108static void 109tegra_rtc_wait(struct tegra_rtc_softc *sc) 110{ 111 int timeout; 112 113 for (timeout = 500; timeout >0; timeout--) { 114 if ((RD4(sc, RTC_BUSY) & RTC_BUSY_STATUS) == 0) 115 break; 116 DELAY(1); 117 } 118 if (timeout <= 0) 119 device_printf(sc->dev, "Device busy timeouted\n"); 120 121} 122 123/* 124 * Get the time of day clock and return it in ts. 125 * Return 0 on success, an error number otherwise. 126 */ 127static int 128tegra_rtc_gettime(device_t dev, struct timespec *ts) 129{ 130 struct tegra_rtc_softc *sc; 131 struct timeval tv; 132 uint32_t msec, sec; 133 134 sc = device_get_softc(dev); 135 136 LOCK(sc); 137 msec = RD4(sc, RTC_MILLI_SECONDS); 138 sec = RD4(sc, RTC_SHADOW_SECONDS); 139 UNLOCK(sc); 140 tv.tv_sec = sec; 141 tv.tv_usec = msec * 1000; 142 TIMEVAL_TO_TIMESPEC(&tv, ts); 143 return (0); 144} 145 146 147static int 148tegra_rtc_settime(device_t dev, struct timespec *ts) 149{ 150 struct tegra_rtc_softc *sc; 151 struct timeval tv; 152 153 sc = device_get_softc(dev); 154 155 LOCK(sc); 156 TIMESPEC_TO_TIMEVAL(&tv, ts); 157 tegra_rtc_wait(sc); 158 WR4(sc, RTC_SECONDS, tv.tv_sec); 159 UNLOCK(sc); 160 161 return (0); 162} 163 164 165static void 166tegra_rtc_intr(void *arg) 167{ 168 struct tegra_rtc_softc *sc; 169 uint32_t status; 170 171 sc = (struct tegra_rtc_softc *)arg; 172 LOCK(sc); 173 status = RD4(sc, RTC_INTR_STATUS); 174 WR4(sc, RTC_INTR_STATUS, status); 175 UNLOCK(sc); 176} 177 178static int 179tegra_rtc_probe(device_t dev) 180{ 181 if (!ofw_bus_status_okay(dev)) 182 return (ENXIO); 183 184 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) 185 return (ENXIO); 186 187 return (BUS_PROBE_DEFAULT); 188} 189 190static int 191tegra_rtc_attach(device_t dev) 192{ 193 int rv, rid; 194 struct tegra_rtc_softc *sc; 195 196 sc = device_get_softc(dev); 197 sc->dev = dev; 198 199 LOCK_INIT(sc); 200 201 /* Get the memory resource for the register mapping. */ 202 rid = 0; 203 sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 204 RF_ACTIVE); 205 if (sc->mem_res == NULL) { 206 device_printf(dev, "Cannot map registers.\n"); 207 rv = ENXIO; 208 goto fail; 209 } 210 211 /* Allocate our IRQ resource. */ 212 rid = 0; 213 sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 214 RF_ACTIVE); 215 if (sc->irq_res == NULL) { 216 device_printf(dev, "Cannot allocate interrupt.\n"); 217 rv = ENXIO; 218 goto fail; 219 } 220 221 /* OFW resources. */ 222 rv = clk_get_by_ofw_index(dev, 0, 0, &sc->clk); 223 if (rv != 0) { 224 device_printf(dev, "Cannot get i2c clock: %d\n", rv); 225 goto fail; 226 } 227 rv = clk_enable(sc->clk); 228 if (rv != 0) { 229 device_printf(dev, "Cannot enable clock: %d\n", rv); 230 goto fail; 231 } 232 233 /* Init hardware. */ 234 WR4(sc, RTC_SECONDS_ALARM0, 0); 235 WR4(sc, RTC_SECONDS_ALARM1, 0); 236 WR4(sc, RTC_INTR_STATUS, 0xFFFFFFFF); 237 WR4(sc, RTC_INTR_MASK, 0); 238 239 /* Setup interrupt */ 240 rv = bus_setup_intr(dev, sc->irq_res, INTR_TYPE_MISC | INTR_MPSAFE, 241 NULL, tegra_rtc_intr, sc, &sc->irq_h); 242 if (rv) { 243 device_printf(dev, "Cannot setup interrupt.\n"); 244 goto fail; 245 } 246 247 /* 248 * Register as a time of day clock with 1-second resolution. 249 * 250 * XXXX Not yet, we don't have support for multiple RTCs 251 */ 252 /* clock_register(dev, 1000000); */ 253 254 return (bus_generic_attach(dev)); 255 256fail: 257 if (sc->clk != NULL) 258 clk_release(sc->clk); 259 if (sc->irq_h != NULL) 260 bus_teardown_intr(dev, sc->irq_res, sc->irq_h); 261 if (sc->irq_res != NULL) 262 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->irq_res); 263 if (sc->mem_res != NULL) 264 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->mem_res); 265 LOCK_DESTROY(sc); 266 267 return (rv); 268} 269 270static int 271tegra_rtc_detach(device_t dev) 272{ 273 struct tegra_rtc_softc *sc; 274 275 sc = device_get_softc(dev); 276 if (sc->irq_h != NULL) 277 bus_teardown_intr(dev, sc->irq_res, sc->irq_h); 278 if (sc->irq_res != NULL) 279 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->irq_res); 280 if (sc->mem_res != NULL) 281 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->mem_res); 282 283 LOCK_DESTROY(sc); 284 return (bus_generic_detach(dev)); 285} 286 287static device_method_t tegra_rtc_methods[] = { 288 /* Device interface */ 289 DEVMETHOD(device_probe, tegra_rtc_probe), 290 DEVMETHOD(device_attach, tegra_rtc_attach), 291 DEVMETHOD(device_detach, tegra_rtc_detach), 292 293 /* clock interface */ 294 DEVMETHOD(clock_gettime, tegra_rtc_gettime), 295 DEVMETHOD(clock_settime, tegra_rtc_settime), 296 297 DEVMETHOD_END 298}; 299 300static devclass_t tegra_rtc_devclass; 301static DEFINE_CLASS_0(rtc, tegra_rtc_driver, tegra_rtc_methods, 302 sizeof(struct tegra_rtc_softc)); 303DRIVER_MODULE(tegra_rtc, simplebus, tegra_rtc_driver, tegra_rtc_devclass, 304 NULL, NULL); 305