nvidia/drm2/tegra_hdmi.c

61 #define	WR4(_sc, _r, _v)	bus_write_4((_sc)->mem_res, 4 * (_r), (_v))
359 	WR4(sc, HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_HEADER,
361 	WR4(sc, HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK0_LOW,
363 	WR4(sc, HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH,
365 	WR4(sc, HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK1_LOW,
367 	WR4(sc, HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH,
370 	WR4(sc, HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL,
391 	WR4(sc, HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_HEADER,
393 	WR4(sc, HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_SUBPACK0_LOW,
395 	WR4(sc, HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_SUBPACK0_HIGH,
398 	WR4(sc, HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL,
419 		WR4(sc, HDMI_NV_PDISP_SOR_AUDIO_HDA_ELD_BUFWR, val);
421 	WR4(sc,HDMI_NV_PDISP_SOR_AUDIO_HDA_PRESENSE,
550 	WR4(sc, HDMI_NV_PDISP_SOR_AUDIO_CNTRL0,
556 	WR4(sc, HDMI_NV_PDISP_SOR_AUDIO_SPARE0, val);
558 	WR4(sc, HDMI_NV_PDISP_HDMI_ACR_CTRL, 0);
560 	WR4(sc, HDMI_NV_PDISP_AUDIO_N,
565 	WR4(sc, HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_HIGH,
568 	WR4(sc, HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_LOW,
571 	WR4(sc, HDMI_NV_PDISP_HDMI_SPARE,
576 	WR4(sc, HDMI_NV_PDISP_AUDIO_N, val);
578 	WR4(sc, aval_reg, audio_aval);
590 	WR4(sc, HDMI_NV_PDISP_HDMI_GENERIC_CTRL, val);
595 	WR4(sc, HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL, val);
608 	WR4(sc, HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL, val);
613 	WR4(sc, HDMI_NV_PDISP_HDMI_GENERIC_CTRL, val);
657 	WR4(sc, HDMI_NV_PDISP_SOR_PLL0, tmds->pll0);
658 	WR4(sc, HDMI_NV_PDISP_SOR_PLL1, tmds->pll1);
659 	WR4(sc, HDMI_NV_PDISP_PE_CURRENT, tmds->pe_c);
660 	WR4(sc, HDMI_NV_PDISP_SOR_LANE_DRIVE_CURRENT, tmds->drive_c);
661 	WR4(sc, HDMI_NV_PDISP_SOR_IO_PEAK_CURRENT, tmds->peak_c);
662 	WR4(sc, HDMI_NV_PDISP_SOR_PAD_CTLS0, tmds->pad_ctls);
676 	WR4(sc, HDMI_NV_PDISP_SOR_PLL0, val);
681 	WR4(sc, HDMI_NV_PDISP_SOR_PLL0, val);
683 	WR4(sc, HDMI_NV_PDISP_SOR_PWR, SOR_PWR_SETTING_NEW);
684 	WR4(sc, HDMI_NV_PDISP_SOR_PWR, 0);
706 	WR4(sc, HDMI_NV_PDISP_SOR_STATE2, val);
708 	WR4(sc, HDMI_NV_PDISP_SOR_STATE1, SOR_STATE1_ASY_ORMODE_NORMAL |
711 	WR4(sc, HDMI_NV_PDISP_SOR_STATE0, 0);
712 	WR4(sc, HDMI_NV_PDISP_SOR_STATE0, SOR_STATE0_UPDATE);
716 	WR4(sc, HDMI_NV_PDISP_SOR_STATE1, val);
718 	WR4(sc, HDMI_NV_PDISP_SOR_STATE0, 0);
744 	WR4(sc, HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL, val);
747 	WR4(sc, HDMI_NV_PDISP_INT_ENABLE, 0);
748 	WR4(sc, HDMI_NV_PDISP_INT_MASK, 0);
798 	WR4(sc, HDMI_NV_PDISP_SOR_PLL0, val);
803 	WR4(sc, HDMI_NV_PDISP_SOR_PLL0, val);
807 	WR4(sc, HDMI_NV_PDISP_HDMI_VSYNC_WINDOW,
817 	WR4(sc, HDMI_NV_PDISP_INPUT_CONTROL, val);
822 	WR4(sc, HDMI_NV_PDISP_SOR_REFCLK, val);
837 	WR4(sc, HDMI_NV_PDISP_HDMI_CTRL, val);
848 	WR4(sc, HDMI_NV_PDISP_SOR_SEQ_CTL,
856 	WR4(sc, HDMI_NV_PDISP_SOR_SEQ_INST(0), val);
857 	WR4(sc, HDMI_NV_PDISP_SOR_SEQ_INST(8), val);
866 	WR4(sc, HDMI_NV_PDISP_SOR_CSTM, val);
878 	WR4(sc, HDMI_NV_PDISP_INT_MASK, INT_CODEC_SCRATCH0);
879 	WR4(sc, HDMI_NV_PDISP_INT_ENABLE, INT_CODEC_SCRATCH0);
1174 	WR4(sc, HDMI_NV_PDISP_INT_STATUS, status);