1256806Sian/*- 2256806Sian * Copyright (c) 2013 Ian Lepore <ian@freebsd.org> 3256806Sian * All rights reserved. 4256806Sian * 5256806Sian * Redistribution and use in source and binary forms, with or without 6256806Sian * modification, are permitted provided that the following conditions 7256806Sian * are met: 8256806Sian * 1. Redistributions of source code must retain the above copyright 9256806Sian * notice, this list of conditions and the following disclaimer. 10256806Sian * 2. Redistributions in binary form must reproduce the above copyright 11256806Sian * notice, this list of conditions and the following disclaimer in the 12256806Sian * documentation and/or other materials provided with the distribution. 13256806Sian * 14256806Sian * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15256806Sian * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16256806Sian * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17256806Sian * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18256806Sian * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19256806Sian * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20256806Sian * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21256806Sian * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22256806Sian * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23256806Sian * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24256806Sian * SUCH DAMAGE. 25256806Sian * 26256806Sian */ 27256806Sian 28256806Sian#include <sys/cdefs.h> 29256806Sian__FBSDID("$FreeBSD: stable/11/sys/dev/ffec/if_ffec.c 338992 2018-09-28 10:02:47Z ae $"); 30256806Sian 31256806Sian/* 32256806Sian * Driver for Freescale Fast Ethernet Controller, found on imx-series SoCs among 33256806Sian * others. Also works for the ENET Gigibit controller found on imx6 and imx28, 34256806Sian * but the driver doesn't currently use any of the ENET advanced features other 35256806Sian * than enabling gigabit. 36256806Sian * 37256806Sian * The interface name 'fec' is already taken by netgraph's Fast Etherchannel 38256806Sian * (netgraph/ng_fec.c), so we use 'ffec'. 39256806Sian * 40256806Sian * Requires an FDT entry with at least these properties: 41256806Sian * fec: ethernet@02188000 { 42256806Sian * compatible = "fsl,imxNN-fec"; 43256806Sian * reg = <0x02188000 0x4000>; 44256806Sian * interrupts = <150 151>; 45256806Sian * phy-mode = "rgmii"; 46256806Sian * phy-disable-preamble; // optional 47256806Sian * }; 48256806Sian * The second interrupt number is for IEEE-1588, and is not currently used; it 49256806Sian * need not be present. phy-mode must be one of: "mii", "rmii", "rgmii". 50256806Sian * There is also an optional property, phy-disable-preamble, which if present 51256806Sian * will disable the preamble bits, cutting the size of each mdio transaction 52256806Sian * (and thus the busy-wait time) in half. 53256806Sian */ 54256806Sian 55256806Sian#include <sys/param.h> 56256806Sian#include <sys/systm.h> 57256806Sian#include <sys/bus.h> 58256806Sian#include <sys/endian.h> 59256806Sian#include <sys/kernel.h> 60256806Sian#include <sys/lock.h> 61256806Sian#include <sys/malloc.h> 62256806Sian#include <sys/mbuf.h> 63256806Sian#include <sys/module.h> 64256806Sian#include <sys/mutex.h> 65256806Sian#include <sys/rman.h> 66256806Sian#include <sys/socket.h> 67256806Sian#include <sys/sockio.h> 68256806Sian#include <sys/sysctl.h> 69256806Sian 70256806Sian#include <machine/bus.h> 71256806Sian 72256806Sian#include <net/bpf.h> 73256806Sian#include <net/if.h> 74256806Sian#include <net/ethernet.h> 75256806Sian#include <net/if_dl.h> 76256806Sian#include <net/if_media.h> 77256806Sian#include <net/if_types.h> 78256806Sian#include <net/if_var.h> 79256806Sian#include <net/if_vlan_var.h> 80256806Sian 81323410Sian#include <dev/fdt/fdt_common.h> 82256806Sian#include <dev/ffec/if_ffecreg.h> 83256806Sian#include <dev/ofw/ofw_bus.h> 84256806Sian#include <dev/ofw/ofw_bus_subr.h> 85256806Sian#include <dev/mii/mii.h> 86256806Sian#include <dev/mii/miivar.h> 87323414Sian#include <dev/mii/mii_fdt.h> 88256806Sian#include "miibus_if.h" 89256806Sian 90256806Sian/* 91257167Sian * There are small differences in the hardware on various SoCs. Not every SoC 92257167Sian * we support has its own FECTYPE; most work as GENERIC and only the ones that 93257167Sian * need different handling get their own entry. In addition to the types in 94257167Sian * this list, there are some flags below that can be ORed into the upper bits. 95257167Sian */ 96257167Sianenum { 97257167Sian FECTYPE_NONE, 98257167Sian FECTYPE_GENERIC, 99257167Sian FECTYPE_IMX53, 100327638Sian FECTYPE_IMX6, /* imx6 and imx7 */ 101260256Sbr FECTYPE_MVF, 102257167Sian}; 103257167Sian 104257167Sian/* 105257167Sian * Flags that describe general differences between the FEC hardware in various 106327638Sian * SoCs. These are ORed into the FECTYPE enum values in the ofw_compat_data, so 107327638Sian * the low 8 bits are reserved for the type enum. In the softc, the type and 108327638Sian * flags are put into separate members, so that you don't need to mask the flags 109327638Sian * out of the type to compare it. 110257167Sian */ 111327638Sian#define FECTYPE_MASK 0x000000ff 112327638Sian#define FECFLAG_GBE (1 << 8) 113327638Sian#define FECFLAG_AVB (1 << 9) 114327638Sian#define FECFLAG_RACC (1 << 10) 115257167Sian 116257167Sian/* 117257167Sian * Table of supported FDT compat strings and their associated FECTYPE values. 118257167Sian */ 119257167Sianstatic struct ofw_compat_data compat_data[] = { 120257167Sian {"fsl,imx51-fec", FECTYPE_GENERIC}, 121257167Sian {"fsl,imx53-fec", FECTYPE_IMX53}, 122327638Sian {"fsl,imx6q-fec", FECTYPE_IMX6 | FECFLAG_RACC | FECFLAG_GBE }, 123327638Sian {"fsl,imx6ul-fec", FECTYPE_IMX6 | FECFLAG_RACC }, 124327638Sian {"fsl,imx7d-fec", FECTYPE_IMX6 | FECFLAG_RACC | FECFLAG_GBE | 125327638Sian FECFLAG_AVB }, 126327638Sian {"fsl,mvf600-fec", FECTYPE_MVF | FECFLAG_RACC }, 127260256Sbr {"fsl,mvf-fec", FECTYPE_MVF}, 128257167Sian {NULL, FECTYPE_NONE}, 129257167Sian}; 130257167Sian 131257167Sian/* 132256806Sian * Driver data and defines. 133256806Sian */ 134256806Sian#define RX_DESC_COUNT 64 135256806Sian#define RX_DESC_SIZE (sizeof(struct ffec_hwdesc) * RX_DESC_COUNT) 136256806Sian#define TX_DESC_COUNT 64 137256806Sian#define TX_DESC_SIZE (sizeof(struct ffec_hwdesc) * TX_DESC_COUNT) 138256806Sian 139256806Sian#define WATCHDOG_TIMEOUT_SECS 5 140256806Sian 141327638Sian#define MAX_IRQ_COUNT 3 142327638Sian 143256806Sianstruct ffec_bufmap { 144256806Sian struct mbuf *mbuf; 145256806Sian bus_dmamap_t map; 146256806Sian}; 147256806Sian 148256806Sianstruct ffec_softc { 149256806Sian device_t dev; 150256806Sian device_t miibus; 151256806Sian struct mii_data * mii_softc; 152256806Sian struct ifnet *ifp; 153256806Sian int if_flags; 154256806Sian struct mtx mtx; 155327638Sian struct resource *irq_res[MAX_IRQ_COUNT]; 156256806Sian struct resource *mem_res; 157327638Sian void * intr_cookie[MAX_IRQ_COUNT]; 158256806Sian struct callout ffec_callout; 159323414Sian mii_contype_t phy_conn_type; 160327638Sian uint32_t fecflags; 161256806Sian uint8_t fectype; 162256806Sian boolean_t link_is_up; 163256806Sian boolean_t is_attached; 164256806Sian boolean_t is_detaching; 165256806Sian int tx_watchdog_count; 166327638Sian int rxbuf_align; 167327638Sian int txbuf_align; 168256806Sian 169256806Sian bus_dma_tag_t rxdesc_tag; 170256806Sian bus_dmamap_t rxdesc_map; 171256806Sian struct ffec_hwdesc *rxdesc_ring; 172256806Sian bus_addr_t rxdesc_ring_paddr; 173256806Sian bus_dma_tag_t rxbuf_tag; 174256806Sian struct ffec_bufmap rxbuf_map[RX_DESC_COUNT]; 175256806Sian uint32_t rx_idx; 176256806Sian 177256806Sian bus_dma_tag_t txdesc_tag; 178256806Sian bus_dmamap_t txdesc_map; 179256806Sian struct ffec_hwdesc *txdesc_ring; 180256806Sian bus_addr_t txdesc_ring_paddr; 181256806Sian bus_dma_tag_t txbuf_tag; 182300878Sian struct ffec_bufmap txbuf_map[TX_DESC_COUNT]; 183256806Sian uint32_t tx_idx_head; 184256806Sian uint32_t tx_idx_tail; 185256806Sian int txcount; 186256806Sian}; 187256806Sian 188327638Sianstatic struct resource_spec irq_res_spec[MAX_IRQ_COUNT + 1] = { 189327638Sian { SYS_RES_IRQ, 0, RF_ACTIVE }, 190327638Sian { SYS_RES_IRQ, 1, RF_ACTIVE | RF_OPTIONAL }, 191327638Sian { SYS_RES_IRQ, 2, RF_ACTIVE | RF_OPTIONAL }, 192327638Sian RESOURCE_SPEC_END 193327638Sian}; 194327638Sian 195256806Sian#define FFEC_LOCK(sc) mtx_lock(&(sc)->mtx) 196256806Sian#define FFEC_UNLOCK(sc) mtx_unlock(&(sc)->mtx) 197256806Sian#define FFEC_LOCK_INIT(sc) mtx_init(&(sc)->mtx, \ 198256806Sian device_get_nameunit((sc)->dev), MTX_NETWORK_LOCK, MTX_DEF) 199256806Sian#define FFEC_LOCK_DESTROY(sc) mtx_destroy(&(sc)->mtx); 200256806Sian#define FFEC_ASSERT_LOCKED(sc) mtx_assert(&(sc)->mtx, MA_OWNED); 201256806Sian#define FFEC_ASSERT_UNLOCKED(sc) mtx_assert(&(sc)->mtx, MA_NOTOWNED); 202256806Sian 203256806Sianstatic void ffec_init_locked(struct ffec_softc *sc); 204256806Sianstatic void ffec_stop_locked(struct ffec_softc *sc); 205256806Sianstatic void ffec_txstart_locked(struct ffec_softc *sc); 206256806Sianstatic void ffec_txfinish_locked(struct ffec_softc *sc); 207256806Sian 208256806Sianstatic inline uint16_t 209256806SianRD2(struct ffec_softc *sc, bus_size_t off) 210256806Sian{ 211256806Sian 212256806Sian return (bus_read_2(sc->mem_res, off)); 213256806Sian} 214256806Sian 215256806Sianstatic inline void 216256806SianWR2(struct ffec_softc *sc, bus_size_t off, uint16_t val) 217256806Sian{ 218256806Sian 219256806Sian bus_write_2(sc->mem_res, off, val); 220256806Sian} 221256806Sian 222256806Sianstatic inline uint32_t 223256806SianRD4(struct ffec_softc *sc, bus_size_t off) 224256806Sian{ 225256806Sian 226256806Sian return (bus_read_4(sc->mem_res, off)); 227256806Sian} 228256806Sian 229256806Sianstatic inline void 230256806SianWR4(struct ffec_softc *sc, bus_size_t off, uint32_t val) 231256806Sian{ 232256806Sian 233256806Sian bus_write_4(sc->mem_res, off, val); 234256806Sian} 235256806Sian 236256806Sianstatic inline uint32_t 237256806Siannext_rxidx(struct ffec_softc *sc, uint32_t curidx) 238256806Sian{ 239256806Sian 240256806Sian return ((curidx == RX_DESC_COUNT - 1) ? 0 : curidx + 1); 241256806Sian} 242256806Sian 243256806Sianstatic inline uint32_t 244256806Siannext_txidx(struct ffec_softc *sc, uint32_t curidx) 245256806Sian{ 246256806Sian 247256806Sian return ((curidx == TX_DESC_COUNT - 1) ? 0 : curidx + 1); 248256806Sian} 249256806Sian 250256806Sianstatic void 251256806Sianffec_get1paddr(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 252256806Sian{ 253256806Sian 254256806Sian if (error != 0) 255256806Sian return; 256256806Sian *(bus_addr_t *)arg = segs[0].ds_addr; 257256806Sian} 258256806Sian 259256806Sianstatic void 260256806Sianffec_miigasket_setup(struct ffec_softc *sc) 261256806Sian{ 262256806Sian uint32_t ifmode; 263256806Sian 264256806Sian /* 265256806Sian * We only need the gasket for MII and RMII connections on certain SoCs. 266256806Sian */ 267256806Sian 268327638Sian switch (sc->fectype) 269256806Sian { 270256806Sian case FECTYPE_IMX53: 271256806Sian break; 272256806Sian default: 273256806Sian return; 274256806Sian } 275256806Sian 276256806Sian switch (sc->phy_conn_type) 277256806Sian { 278323414Sian case MII_CONTYPE_MII: 279256806Sian ifmode = 0; 280256806Sian break; 281323414Sian case MII_CONTYPE_RMII: 282256806Sian ifmode = FEC_MIIGSK_CFGR_IF_MODE_RMII; 283256806Sian break; 284256806Sian default: 285256806Sian return; 286256806Sian } 287256806Sian 288256806Sian /* 289256806Sian * Disable the gasket, configure for either MII or RMII, then enable. 290256806Sian */ 291256806Sian 292256806Sian WR2(sc, FEC_MIIGSK_ENR, 0); 293256806Sian while (RD2(sc, FEC_MIIGSK_ENR) & FEC_MIIGSK_ENR_READY) 294256806Sian continue; 295256806Sian 296256806Sian WR2(sc, FEC_MIIGSK_CFGR, ifmode); 297256806Sian 298256806Sian WR2(sc, FEC_MIIGSK_ENR, FEC_MIIGSK_ENR_EN); 299256806Sian while (!(RD2(sc, FEC_MIIGSK_ENR) & FEC_MIIGSK_ENR_READY)) 300256806Sian continue; 301256806Sian} 302256806Sian 303256806Sianstatic boolean_t 304256806Sianffec_miibus_iowait(struct ffec_softc *sc) 305256806Sian{ 306256806Sian uint32_t timeout; 307256806Sian 308256806Sian for (timeout = 10000; timeout != 0; --timeout) 309256806Sian if (RD4(sc, FEC_IER_REG) & FEC_IER_MII) 310256806Sian return (true); 311256806Sian 312256806Sian return (false); 313256806Sian} 314256806Sian 315256806Sianstatic int 316256806Sianffec_miibus_readreg(device_t dev, int phy, int reg) 317256806Sian{ 318256806Sian struct ffec_softc *sc; 319256806Sian int val; 320256806Sian 321256806Sian sc = device_get_softc(dev); 322256806Sian 323256806Sian WR4(sc, FEC_IER_REG, FEC_IER_MII); 324256806Sian 325256806Sian WR4(sc, FEC_MMFR_REG, FEC_MMFR_OP_READ | 326256806Sian FEC_MMFR_ST_VALUE | FEC_MMFR_TA_VALUE | 327256806Sian ((phy << FEC_MMFR_PA_SHIFT) & FEC_MMFR_PA_MASK) | 328256806Sian ((reg << FEC_MMFR_RA_SHIFT) & FEC_MMFR_RA_MASK)); 329256806Sian 330256806Sian if (!ffec_miibus_iowait(sc)) { 331256806Sian device_printf(dev, "timeout waiting for mii read\n"); 332256806Sian return (-1); /* All-ones is a symptom of bad mdio. */ 333256806Sian } 334256806Sian 335256806Sian val = RD4(sc, FEC_MMFR_REG) & FEC_MMFR_DATA_MASK; 336256806Sian 337256806Sian return (val); 338256806Sian} 339256806Sian 340256806Sianstatic int 341256806Sianffec_miibus_writereg(device_t dev, int phy, int reg, int val) 342256806Sian{ 343256806Sian struct ffec_softc *sc; 344256806Sian 345256806Sian sc = device_get_softc(dev); 346256806Sian 347256806Sian WR4(sc, FEC_IER_REG, FEC_IER_MII); 348256806Sian 349256806Sian WR4(sc, FEC_MMFR_REG, FEC_MMFR_OP_WRITE | 350256806Sian FEC_MMFR_ST_VALUE | FEC_MMFR_TA_VALUE | 351256806Sian ((phy << FEC_MMFR_PA_SHIFT) & FEC_MMFR_PA_MASK) | 352256806Sian ((reg << FEC_MMFR_RA_SHIFT) & FEC_MMFR_RA_MASK) | 353256806Sian (val & FEC_MMFR_DATA_MASK)); 354256806Sian 355256806Sian if (!ffec_miibus_iowait(sc)) { 356256806Sian device_printf(dev, "timeout waiting for mii write\n"); 357256806Sian return (-1); 358256806Sian } 359256806Sian 360256806Sian return (0); 361256806Sian} 362256806Sian 363256806Sianstatic void 364256806Sianffec_miibus_statchg(device_t dev) 365256806Sian{ 366256806Sian struct ffec_softc *sc; 367256806Sian struct mii_data *mii; 368256806Sian uint32_t ecr, rcr, tcr; 369256806Sian 370256806Sian /* 371256806Sian * Called by the MII bus driver when the PHY establishes link to set the 372256806Sian * MAC interface registers. 373256806Sian */ 374256806Sian 375256806Sian sc = device_get_softc(dev); 376256806Sian 377256806Sian FFEC_ASSERT_LOCKED(sc); 378256806Sian 379256806Sian mii = sc->mii_softc; 380256806Sian 381256806Sian if (mii->mii_media_status & IFM_ACTIVE) 382256806Sian sc->link_is_up = true; 383256806Sian else 384256806Sian sc->link_is_up = false; 385256806Sian 386256806Sian ecr = RD4(sc, FEC_ECR_REG) & ~FEC_ECR_SPEED; 387256806Sian rcr = RD4(sc, FEC_RCR_REG) & ~(FEC_RCR_RMII_10T | FEC_RCR_RMII_MODE | 388256806Sian FEC_RCR_RGMII_EN | FEC_RCR_DRT | FEC_RCR_FCE); 389256806Sian tcr = RD4(sc, FEC_TCR_REG) & ~FEC_TCR_FDEN; 390256806Sian 391256806Sian rcr |= FEC_RCR_MII_MODE; /* Must always be on even for R[G]MII. */ 392256806Sian switch (sc->phy_conn_type) { 393323414Sian case MII_CONTYPE_RMII: 394256806Sian rcr |= FEC_RCR_RMII_MODE; 395256806Sian break; 396323414Sian case MII_CONTYPE_RGMII: 397323414Sian case MII_CONTYPE_RGMII_ID: 398323414Sian case MII_CONTYPE_RGMII_RXID: 399323414Sian case MII_CONTYPE_RGMII_TXID: 400256806Sian rcr |= FEC_RCR_RGMII_EN; 401256806Sian break; 402323414Sian default: 403323414Sian break; 404256806Sian } 405256806Sian 406256806Sian switch (IFM_SUBTYPE(mii->mii_media_active)) { 407256806Sian case IFM_1000_T: 408256806Sian case IFM_1000_SX: 409256806Sian ecr |= FEC_ECR_SPEED; 410256806Sian break; 411256806Sian case IFM_100_TX: 412256806Sian /* Not-FEC_ECR_SPEED + not-FEC_RCR_RMII_10T means 100TX */ 413256806Sian break; 414256806Sian case IFM_10_T: 415256806Sian rcr |= FEC_RCR_RMII_10T; 416256806Sian break; 417256806Sian case IFM_NONE: 418256806Sian sc->link_is_up = false; 419256806Sian return; 420256806Sian default: 421256806Sian sc->link_is_up = false; 422256806Sian device_printf(dev, "Unsupported media %u\n", 423256806Sian IFM_SUBTYPE(mii->mii_media_active)); 424256806Sian return; 425256806Sian } 426256806Sian 427256806Sian if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) 428256806Sian tcr |= FEC_TCR_FDEN; 429256806Sian else 430256806Sian rcr |= FEC_RCR_DRT; 431256806Sian 432256806Sian if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FLOW) != 0) 433256806Sian rcr |= FEC_RCR_FCE; 434256806Sian 435256806Sian WR4(sc, FEC_RCR_REG, rcr); 436256806Sian WR4(sc, FEC_TCR_REG, tcr); 437256806Sian WR4(sc, FEC_ECR_REG, ecr); 438256806Sian} 439256806Sian 440256806Sianstatic void 441256806Sianffec_media_status(struct ifnet * ifp, struct ifmediareq *ifmr) 442256806Sian{ 443256806Sian struct ffec_softc *sc; 444256806Sian struct mii_data *mii; 445256806Sian 446256806Sian 447256806Sian sc = ifp->if_softc; 448256806Sian mii = sc->mii_softc; 449256806Sian FFEC_LOCK(sc); 450256806Sian mii_pollstat(mii); 451256806Sian ifmr->ifm_active = mii->mii_media_active; 452256806Sian ifmr->ifm_status = mii->mii_media_status; 453256806Sian FFEC_UNLOCK(sc); 454256806Sian} 455256806Sian 456256806Sianstatic int 457256806Sianffec_media_change_locked(struct ffec_softc *sc) 458256806Sian{ 459256806Sian 460256806Sian return (mii_mediachg(sc->mii_softc)); 461256806Sian} 462256806Sian 463256806Sianstatic int 464256806Sianffec_media_change(struct ifnet * ifp) 465256806Sian{ 466256806Sian struct ffec_softc *sc; 467256806Sian int error; 468256806Sian 469256806Sian sc = ifp->if_softc; 470256806Sian 471256806Sian FFEC_LOCK(sc); 472256806Sian error = ffec_media_change_locked(sc); 473256806Sian FFEC_UNLOCK(sc); 474256806Sian return (error); 475256806Sian} 476256806Sian 477256806Sianstatic void ffec_clear_stats(struct ffec_softc *sc) 478256806Sian{ 479323411Sian uint32_t mibc; 480256806Sian 481323411Sian mibc = RD4(sc, FEC_MIBC_REG); 482323411Sian 483323411Sian /* 484323411Sian * On newer hardware the statistic regs are cleared by toggling a bit in 485323411Sian * the mib control register. On older hardware the clear procedure is 486323411Sian * to disable statistics collection, zero the regs, then re-enable. 487323411Sian */ 488323411Sian if (sc->fectype == FECTYPE_IMX6 || sc->fectype == FECTYPE_MVF) { 489323411Sian WR4(sc, FEC_MIBC_REG, mibc | FEC_MIBC_CLEAR); 490323411Sian WR4(sc, FEC_MIBC_REG, mibc & ~FEC_MIBC_CLEAR); 491323411Sian } else { 492323411Sian WR4(sc, FEC_MIBC_REG, mibc | FEC_MIBC_DIS); 493323411Sian 494323411Sian WR4(sc, FEC_IEEE_R_DROP, 0); 495323411Sian WR4(sc, FEC_IEEE_R_MACERR, 0); 496323411Sian WR4(sc, FEC_RMON_R_CRC_ALIGN, 0); 497323411Sian WR4(sc, FEC_RMON_R_FRAG, 0); 498323411Sian WR4(sc, FEC_RMON_R_JAB, 0); 499323411Sian WR4(sc, FEC_RMON_R_MC_PKT, 0); 500323411Sian WR4(sc, FEC_RMON_R_OVERSIZE, 0); 501323411Sian WR4(sc, FEC_RMON_R_PACKETS, 0); 502323411Sian WR4(sc, FEC_RMON_R_UNDERSIZE, 0); 503323411Sian WR4(sc, FEC_RMON_T_COL, 0); 504323411Sian WR4(sc, FEC_RMON_T_CRC_ALIGN, 0); 505323411Sian WR4(sc, FEC_RMON_T_FRAG, 0); 506323411Sian WR4(sc, FEC_RMON_T_JAB, 0); 507323411Sian WR4(sc, FEC_RMON_T_MC_PKT, 0); 508323411Sian WR4(sc, FEC_RMON_T_OVERSIZE , 0); 509323411Sian WR4(sc, FEC_RMON_T_PACKETS, 0); 510323411Sian WR4(sc, FEC_RMON_T_UNDERSIZE, 0); 511323411Sian 512323411Sian WR4(sc, FEC_MIBC_REG, mibc); 513323411Sian } 514256806Sian} 515256806Sian 516256806Sianstatic void 517256806Sianffec_harvest_stats(struct ffec_softc *sc) 518256806Sian{ 519256806Sian struct ifnet *ifp; 520256806Sian 521323411Sian ifp = sc->ifp; 522256806Sian 523256806Sian /* 524323411Sian * - FEC_IEEE_R_DROP is "dropped due to invalid start frame delimiter" 525323411Sian * so it's really just another type of input error. 526323411Sian * - FEC_IEEE_R_MACERR is "no receive fifo space"; count as input drops. 527256806Sian */ 528271826Sglebius if_inc_counter(ifp, IFCOUNTER_IPACKETS, RD4(sc, FEC_RMON_R_PACKETS)); 529271826Sglebius if_inc_counter(ifp, IFCOUNTER_IMCASTS, RD4(sc, FEC_RMON_R_MC_PKT)); 530271826Sglebius if_inc_counter(ifp, IFCOUNTER_IERRORS, 531271826Sglebius RD4(sc, FEC_RMON_R_CRC_ALIGN) + RD4(sc, FEC_RMON_R_UNDERSIZE) + 532271826Sglebius RD4(sc, FEC_RMON_R_OVERSIZE) + RD4(sc, FEC_RMON_R_FRAG) + 533323411Sian RD4(sc, FEC_RMON_R_JAB) + RD4(sc, FEC_IEEE_R_DROP)); 534256806Sian 535323411Sian if_inc_counter(ifp, IFCOUNTER_IQDROPS, RD4(sc, FEC_IEEE_R_MACERR)); 536323411Sian 537271826Sglebius if_inc_counter(ifp, IFCOUNTER_OPACKETS, RD4(sc, FEC_RMON_T_PACKETS)); 538271826Sglebius if_inc_counter(ifp, IFCOUNTER_OMCASTS, RD4(sc, FEC_RMON_T_MC_PKT)); 539271826Sglebius if_inc_counter(ifp, IFCOUNTER_OERRORS, 540271826Sglebius RD4(sc, FEC_RMON_T_CRC_ALIGN) + RD4(sc, FEC_RMON_T_UNDERSIZE) + 541271826Sglebius RD4(sc, FEC_RMON_T_OVERSIZE) + RD4(sc, FEC_RMON_T_FRAG) + 542271826Sglebius RD4(sc, FEC_RMON_T_JAB)); 543256806Sian 544271826Sglebius if_inc_counter(ifp, IFCOUNTER_COLLISIONS, RD4(sc, FEC_RMON_T_COL)); 545256806Sian 546256806Sian ffec_clear_stats(sc); 547256806Sian} 548256806Sian 549256806Sianstatic void 550256806Sianffec_tick(void *arg) 551256806Sian{ 552256806Sian struct ffec_softc *sc; 553256806Sian struct ifnet *ifp; 554256806Sian int link_was_up; 555256806Sian 556256806Sian sc = arg; 557256806Sian 558256806Sian FFEC_ASSERT_LOCKED(sc); 559256806Sian 560256806Sian ifp = sc->ifp; 561256806Sian 562256806Sian if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) 563256806Sian return; 564256806Sian 565256806Sian /* 566256806Sian * Typical tx watchdog. If this fires it indicates that we enqueued 567256806Sian * packets for output and never got a txdone interrupt for them. Maybe 568256806Sian * it's a missed interrupt somehow, just pretend we got one. 569256806Sian */ 570256806Sian if (sc->tx_watchdog_count > 0) { 571256806Sian if (--sc->tx_watchdog_count == 0) { 572256806Sian ffec_txfinish_locked(sc); 573256806Sian } 574256806Sian } 575256806Sian 576256806Sian /* Gather stats from hardware counters. */ 577256806Sian ffec_harvest_stats(sc); 578256806Sian 579256806Sian /* Check the media status. */ 580256806Sian link_was_up = sc->link_is_up; 581256806Sian mii_tick(sc->mii_softc); 582256806Sian if (sc->link_is_up && !link_was_up) 583256806Sian ffec_txstart_locked(sc); 584256806Sian 585256806Sian /* Schedule another check one second from now. */ 586256806Sian callout_reset(&sc->ffec_callout, hz, ffec_tick, sc); 587256806Sian} 588256806Sian 589256806Sianinline static uint32_t 590256806Sianffec_setup_txdesc(struct ffec_softc *sc, int idx, bus_addr_t paddr, 591256806Sian uint32_t len) 592256806Sian{ 593256806Sian uint32_t nidx; 594256806Sian uint32_t flags; 595256806Sian 596256806Sian nidx = next_txidx(sc, idx); 597256806Sian 598256806Sian /* Addr/len 0 means we're clearing the descriptor after xmit done. */ 599256806Sian if (paddr == 0 || len == 0) { 600256806Sian flags = 0; 601256806Sian --sc->txcount; 602256806Sian } else { 603256806Sian flags = FEC_TXDESC_READY | FEC_TXDESC_L | FEC_TXDESC_TC; 604256806Sian ++sc->txcount; 605256806Sian } 606256806Sian if (nidx == 0) 607256806Sian flags |= FEC_TXDESC_WRAP; 608256806Sian 609256806Sian /* 610256806Sian * The hardware requires 32-bit physical addresses. We set up the dma 611256806Sian * tag to indicate that, so the cast to uint32_t should never lose 612256806Sian * significant bits. 613256806Sian */ 614256806Sian sc->txdesc_ring[idx].buf_paddr = (uint32_t)paddr; 615256806Sian sc->txdesc_ring[idx].flags_len = flags | len; /* Must be set last! */ 616256806Sian 617256806Sian return (nidx); 618256806Sian} 619256806Sian 620256806Sianstatic int 621256806Sianffec_setup_txbuf(struct ffec_softc *sc, int idx, struct mbuf **mp) 622256806Sian{ 623256806Sian struct mbuf * m; 624256806Sian int error, nsegs; 625256806Sian struct bus_dma_segment seg; 626256806Sian 627256806Sian if ((m = m_defrag(*mp, M_NOWAIT)) == NULL) 628256806Sian return (ENOMEM); 629256806Sian *mp = m; 630256806Sian 631256806Sian error = bus_dmamap_load_mbuf_sg(sc->txbuf_tag, sc->txbuf_map[idx].map, 632256806Sian m, &seg, &nsegs, 0); 633256806Sian if (error != 0) { 634256806Sian return (ENOMEM); 635256806Sian } 636256806Sian bus_dmamap_sync(sc->txbuf_tag, sc->txbuf_map[idx].map, 637256806Sian BUS_DMASYNC_PREWRITE); 638256806Sian 639256806Sian sc->txbuf_map[idx].mbuf = m; 640256806Sian ffec_setup_txdesc(sc, idx, seg.ds_addr, seg.ds_len); 641256806Sian 642256806Sian return (0); 643256806Sian 644256806Sian} 645256806Sian 646256806Sianstatic void 647256806Sianffec_txstart_locked(struct ffec_softc *sc) 648256806Sian{ 649256806Sian struct ifnet *ifp; 650256806Sian struct mbuf *m; 651256806Sian int enqueued; 652256806Sian 653256806Sian FFEC_ASSERT_LOCKED(sc); 654256806Sian 655256806Sian if (!sc->link_is_up) 656256806Sian return; 657256806Sian 658256806Sian ifp = sc->ifp; 659256806Sian 660256806Sian if (ifp->if_drv_flags & IFF_DRV_OACTIVE) 661256806Sian return; 662256806Sian 663256806Sian enqueued = 0; 664256806Sian 665256806Sian for (;;) { 666256806Sian if (sc->txcount == (TX_DESC_COUNT-1)) { 667256806Sian ifp->if_drv_flags |= IFF_DRV_OACTIVE; 668256806Sian break; 669256806Sian } 670256806Sian IFQ_DRV_DEQUEUE(&ifp->if_snd, m); 671256806Sian if (m == NULL) 672256806Sian break; 673256806Sian if (ffec_setup_txbuf(sc, sc->tx_idx_head, &m) != 0) { 674256806Sian IFQ_DRV_PREPEND(&ifp->if_snd, m); 675256806Sian break; 676256806Sian } 677256806Sian BPF_MTAP(ifp, m); 678256806Sian sc->tx_idx_head = next_txidx(sc, sc->tx_idx_head); 679256806Sian ++enqueued; 680256806Sian } 681256806Sian 682256806Sian if (enqueued != 0) { 683274967Sian bus_dmamap_sync(sc->txdesc_tag, sc->txdesc_map, BUS_DMASYNC_PREWRITE); 684256806Sian WR4(sc, FEC_TDAR_REG, FEC_TDAR_TDAR); 685274967Sian bus_dmamap_sync(sc->txdesc_tag, sc->txdesc_map, BUS_DMASYNC_POSTWRITE); 686256806Sian sc->tx_watchdog_count = WATCHDOG_TIMEOUT_SECS; 687256806Sian } 688256806Sian} 689256806Sian 690256806Sianstatic void 691256806Sianffec_txstart(struct ifnet *ifp) 692256806Sian{ 693256806Sian struct ffec_softc *sc = ifp->if_softc; 694256806Sian 695256806Sian FFEC_LOCK(sc); 696256806Sian ffec_txstart_locked(sc); 697256806Sian FFEC_UNLOCK(sc); 698256806Sian} 699256806Sian 700256806Sianstatic void 701256806Sianffec_txfinish_locked(struct ffec_softc *sc) 702256806Sian{ 703256806Sian struct ifnet *ifp; 704256806Sian struct ffec_hwdesc *desc; 705256806Sian struct ffec_bufmap *bmap; 706256806Sian boolean_t retired_buffer; 707256806Sian 708256806Sian FFEC_ASSERT_LOCKED(sc); 709256806Sian 710274967Sian /* XXX Can't set PRE|POST right now, but we need both. */ 711274967Sian bus_dmamap_sync(sc->txdesc_tag, sc->txdesc_map, BUS_DMASYNC_PREREAD); 712274967Sian bus_dmamap_sync(sc->txdesc_tag, sc->txdesc_map, BUS_DMASYNC_POSTREAD); 713256806Sian ifp = sc->ifp; 714256806Sian retired_buffer = false; 715256806Sian while (sc->tx_idx_tail != sc->tx_idx_head) { 716256806Sian desc = &sc->txdesc_ring[sc->tx_idx_tail]; 717256806Sian if (desc->flags_len & FEC_TXDESC_READY) 718256806Sian break; 719256806Sian retired_buffer = true; 720256806Sian bmap = &sc->txbuf_map[sc->tx_idx_tail]; 721256806Sian bus_dmamap_sync(sc->txbuf_tag, bmap->map, 722256806Sian BUS_DMASYNC_POSTWRITE); 723256806Sian bus_dmamap_unload(sc->txbuf_tag, bmap->map); 724256806Sian m_freem(bmap->mbuf); 725256806Sian bmap->mbuf = NULL; 726256806Sian ffec_setup_txdesc(sc, sc->tx_idx_tail, 0, 0); 727256806Sian sc->tx_idx_tail = next_txidx(sc, sc->tx_idx_tail); 728256806Sian } 729256806Sian 730256806Sian /* 731256806Sian * If we retired any buffers, there will be open tx slots available in 732256806Sian * the descriptor ring, go try to start some new output. 733256806Sian */ 734256806Sian if (retired_buffer) { 735256806Sian ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 736256806Sian ffec_txstart_locked(sc); 737256806Sian } 738256806Sian 739256806Sian /* If there are no buffers outstanding, muzzle the watchdog. */ 740256806Sian if (sc->tx_idx_tail == sc->tx_idx_head) { 741256806Sian sc->tx_watchdog_count = 0; 742256806Sian } 743256806Sian} 744256806Sian 745256806Sianinline static uint32_t 746256806Sianffec_setup_rxdesc(struct ffec_softc *sc, int idx, bus_addr_t paddr) 747256806Sian{ 748256806Sian uint32_t nidx; 749256806Sian 750256806Sian /* 751256806Sian * The hardware requires 32-bit physical addresses. We set up the dma 752256806Sian * tag to indicate that, so the cast to uint32_t should never lose 753256806Sian * significant bits. 754256806Sian */ 755256806Sian nidx = next_rxidx(sc, idx); 756256806Sian sc->rxdesc_ring[idx].buf_paddr = (uint32_t)paddr; 757256806Sian sc->rxdesc_ring[idx].flags_len = FEC_RXDESC_EMPTY | 758256806Sian ((nidx == 0) ? FEC_RXDESC_WRAP : 0); 759256806Sian 760256806Sian return (nidx); 761256806Sian} 762256806Sian 763256806Sianstatic int 764256806Sianffec_setup_rxbuf(struct ffec_softc *sc, int idx, struct mbuf * m) 765256806Sian{ 766256806Sian int error, nsegs; 767256806Sian struct bus_dma_segment seg; 768256806Sian 769327638Sian if (!(sc->fecflags & FECFLAG_RACC)) { 770327638Sian /* 771327638Sian * The RACC[SHIFT16] feature is not available. So, we need to 772327638Sian * leave at least ETHER_ALIGN bytes free at the beginning of the 773327638Sian * buffer to allow the data to be re-aligned after receiving it 774327638Sian * (by copying it backwards ETHER_ALIGN bytes in the same 775327638Sian * buffer). We also have to ensure that the beginning of the 776327638Sian * buffer is aligned to the hardware's requirements. 777327638Sian */ 778327638Sian m_adj(m, roundup(ETHER_ALIGN, sc->rxbuf_align)); 779327638Sian } 780256806Sian 781256806Sian error = bus_dmamap_load_mbuf_sg(sc->rxbuf_tag, sc->rxbuf_map[idx].map, 782256806Sian m, &seg, &nsegs, 0); 783256806Sian if (error != 0) { 784256806Sian return (error); 785256806Sian } 786256806Sian 787256806Sian bus_dmamap_sync(sc->rxbuf_tag, sc->rxbuf_map[idx].map, 788256806Sian BUS_DMASYNC_PREREAD); 789256806Sian 790256806Sian sc->rxbuf_map[idx].mbuf = m; 791256806Sian ffec_setup_rxdesc(sc, idx, seg.ds_addr); 792256806Sian 793256806Sian return (0); 794256806Sian} 795256806Sian 796256806Sianstatic struct mbuf * 797256806Sianffec_alloc_mbufcl(struct ffec_softc *sc) 798256806Sian{ 799256806Sian struct mbuf *m; 800256806Sian 801256806Sian m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 802338992Sae if (m != NULL) 803338992Sae m->m_pkthdr.len = m->m_len = m->m_ext.ext_size; 804256806Sian 805256806Sian return (m); 806256806Sian} 807256806Sian 808256806Sianstatic void 809256806Sianffec_rxfinish_onebuf(struct ffec_softc *sc, int len) 810256806Sian{ 811256806Sian struct mbuf *m, *newmbuf; 812256806Sian struct ffec_bufmap *bmap; 813256806Sian uint8_t *dst, *src; 814256806Sian int error; 815256806Sian 816256806Sian /* 817256806Sian * First try to get a new mbuf to plug into this slot in the rx ring. 818256806Sian * If that fails, drop the current packet and recycle the current 819256806Sian * mbuf, which is still mapped and loaded. 820256806Sian */ 821256806Sian if ((newmbuf = ffec_alloc_mbufcl(sc)) == NULL) { 822271826Sglebius if_inc_counter(sc->ifp, IFCOUNTER_IQDROPS, 1); 823256806Sian ffec_setup_rxdesc(sc, sc->rx_idx, 824256806Sian sc->rxdesc_ring[sc->rx_idx].buf_paddr); 825256806Sian return; 826256806Sian } 827256806Sian 828256806Sian FFEC_UNLOCK(sc); 829256806Sian 830256806Sian bmap = &sc->rxbuf_map[sc->rx_idx]; 831256806Sian len -= ETHER_CRC_LEN; 832256806Sian bus_dmamap_sync(sc->rxbuf_tag, bmap->map, BUS_DMASYNC_POSTREAD); 833256806Sian bus_dmamap_unload(sc->rxbuf_tag, bmap->map); 834256806Sian m = bmap->mbuf; 835256806Sian bmap->mbuf = NULL; 836256806Sian m->m_len = len; 837256806Sian m->m_pkthdr.len = len; 838256806Sian m->m_pkthdr.rcvif = sc->ifp; 839256806Sian 840327638Sian /* 841327638Sian * Align the protocol headers in the receive buffer on a 32-bit 842327638Sian * boundary. Newer hardware does the alignment for us. On hardware 843327638Sian * that doesn't support this feature, we have to copy-align the data. 844327638Sian * 845327638Sian * XXX for older hardware, could we speed this up by copying just the 846327638Sian * protocol headers into their own small mbuf then chaining the cluster 847327638Sian * to it? That way we'd only need to copy like 64 bytes or whatever the 848327638Sian * biggest header is, instead of the whole 1530ish-byte frame. 849327638Sian */ 850327638Sian if (sc->fecflags & FECFLAG_RACC) { 851327638Sian m->m_data = mtod(m, uint8_t *) + 2; 852327638Sian } else { 853327638Sian src = mtod(m, uint8_t*); 854327638Sian dst = src - ETHER_ALIGN; 855327638Sian bcopy(src, dst, len); 856327638Sian m->m_data = dst; 857327638Sian } 858256806Sian sc->ifp->if_input(sc->ifp, m); 859256806Sian 860256806Sian FFEC_LOCK(sc); 861256806Sian 862256806Sian if ((error = ffec_setup_rxbuf(sc, sc->rx_idx, newmbuf)) != 0) { 863256806Sian device_printf(sc->dev, "ffec_setup_rxbuf error %d\n", error); 864256806Sian /* XXX Now what? We've got a hole in the rx ring. */ 865256806Sian } 866256806Sian 867256806Sian} 868256806Sian 869256806Sianstatic void 870256806Sianffec_rxfinish_locked(struct ffec_softc *sc) 871256806Sian{ 872256806Sian struct ffec_hwdesc *desc; 873256806Sian int len; 874256806Sian boolean_t produced_empty_buffer; 875256806Sian 876256806Sian FFEC_ASSERT_LOCKED(sc); 877256806Sian 878274967Sian /* XXX Can't set PRE|POST right now, but we need both. */ 879274967Sian bus_dmamap_sync(sc->rxdesc_tag, sc->rxdesc_map, BUS_DMASYNC_PREREAD); 880274967Sian bus_dmamap_sync(sc->rxdesc_tag, sc->rxdesc_map, BUS_DMASYNC_POSTREAD); 881256806Sian produced_empty_buffer = false; 882256806Sian for (;;) { 883256806Sian desc = &sc->rxdesc_ring[sc->rx_idx]; 884256806Sian if (desc->flags_len & FEC_RXDESC_EMPTY) 885256806Sian break; 886256806Sian produced_empty_buffer = true; 887256806Sian len = (desc->flags_len & FEC_RXDESC_LEN_MASK); 888256806Sian if (len < 64) { 889256806Sian /* 890256806Sian * Just recycle the descriptor and continue. . 891256806Sian */ 892256806Sian ffec_setup_rxdesc(sc, sc->rx_idx, 893256806Sian sc->rxdesc_ring[sc->rx_idx].buf_paddr); 894256806Sian } else if ((desc->flags_len & FEC_RXDESC_L) == 0) { 895256806Sian /* 896256806Sian * The entire frame is not in this buffer. Impossible. 897256806Sian * Recycle the descriptor and continue. 898256806Sian * 899256806Sian * XXX what's the right way to handle this? Probably we 900256806Sian * should stop/init the hardware because this should 901256806Sian * just really never happen when we have buffers bigger 902256806Sian * than the maximum frame size. 903256806Sian */ 904256806Sian device_printf(sc->dev, 905256806Sian "fec_rxfinish: received frame without LAST bit set"); 906256806Sian ffec_setup_rxdesc(sc, sc->rx_idx, 907256806Sian sc->rxdesc_ring[sc->rx_idx].buf_paddr); 908256806Sian } else if (desc->flags_len & FEC_RXDESC_ERROR_BITS) { 909256806Sian /* 910256806Sian * Something went wrong with receiving the frame, we 911256806Sian * don't care what (the hardware has counted the error 912256806Sian * in the stats registers already), we just reuse the 913256806Sian * same mbuf, which is still dma-mapped, by resetting 914256806Sian * the rx descriptor. 915256806Sian */ 916256806Sian ffec_setup_rxdesc(sc, sc->rx_idx, 917256806Sian sc->rxdesc_ring[sc->rx_idx].buf_paddr); 918256806Sian } else { 919256806Sian /* 920256806Sian * Normal case: a good frame all in one buffer. 921256806Sian */ 922256806Sian ffec_rxfinish_onebuf(sc, len); 923256806Sian } 924256806Sian sc->rx_idx = next_rxidx(sc, sc->rx_idx); 925256806Sian } 926256806Sian 927256806Sian if (produced_empty_buffer) { 928300878Sian bus_dmamap_sync(sc->rxdesc_tag, sc->rxdesc_map, BUS_DMASYNC_PREWRITE); 929256806Sian WR4(sc, FEC_RDAR_REG, FEC_RDAR_RDAR); 930300878Sian bus_dmamap_sync(sc->rxdesc_tag, sc->rxdesc_map, BUS_DMASYNC_POSTWRITE); 931256806Sian } 932256806Sian} 933256806Sian 934256806Sianstatic void 935256806Sianffec_get_hwaddr(struct ffec_softc *sc, uint8_t *hwaddr) 936256806Sian{ 937256806Sian uint32_t palr, paur, rnd; 938256806Sian 939256806Sian /* 940256806Sian * Try to recover a MAC address from the running hardware. If there's 941256806Sian * something non-zero there, assume the bootloader did the right thing 942256806Sian * and just use it. 943256806Sian * 944256806Sian * Otherwise, set the address to a convenient locally assigned address, 945256806Sian * 'bsd' + random 24 low-order bits. 'b' is 0x62, which has the locally 946256806Sian * assigned bit set, and the broadcast/multicast bit clear. 947256806Sian */ 948256806Sian palr = RD4(sc, FEC_PALR_REG); 949256919Sian paur = RD4(sc, FEC_PAUR_REG) & FEC_PAUR_PADDR2_MASK; 950256806Sian if ((palr | paur) != 0) { 951256806Sian hwaddr[0] = palr >> 24; 952256806Sian hwaddr[1] = palr >> 16; 953256806Sian hwaddr[2] = palr >> 8; 954256806Sian hwaddr[3] = palr >> 0; 955256806Sian hwaddr[4] = paur >> 24; 956256806Sian hwaddr[5] = paur >> 16; 957256806Sian } else { 958256806Sian rnd = arc4random() & 0x00ffffff; 959256806Sian hwaddr[0] = 'b'; 960256806Sian hwaddr[1] = 's'; 961256806Sian hwaddr[2] = 'd'; 962256806Sian hwaddr[3] = rnd >> 16; 963256806Sian hwaddr[4] = rnd >> 8; 964256806Sian hwaddr[5] = rnd >> 0; 965256806Sian } 966256806Sian 967256806Sian if (bootverbose) { 968256806Sian device_printf(sc->dev, 969256806Sian "MAC address %02x:%02x:%02x:%02x:%02x:%02x:\n", 970256806Sian hwaddr[0], hwaddr[1], hwaddr[2], 971256806Sian hwaddr[3], hwaddr[4], hwaddr[5]); 972256806Sian } 973256806Sian} 974256806Sian 975256806Sianstatic void 976256806Sianffec_setup_rxfilter(struct ffec_softc *sc) 977256806Sian{ 978256806Sian struct ifnet *ifp; 979256806Sian struct ifmultiaddr *ifma; 980256806Sian uint8_t *eaddr; 981256806Sian uint32_t crc; 982256806Sian uint64_t ghash, ihash; 983256806Sian 984256806Sian FFEC_ASSERT_LOCKED(sc); 985256806Sian 986256806Sian ifp = sc->ifp; 987256806Sian 988256806Sian /* 989256806Sian * Set the multicast (group) filter hash. 990256806Sian */ 991256806Sian if ((ifp->if_flags & IFF_ALLMULTI)) 992256806Sian ghash = 0xffffffffffffffffLLU; 993256806Sian else { 994256806Sian ghash = 0; 995256806Sian if_maddr_rlock(ifp); 996256806Sian TAILQ_FOREACH(ifma, &sc->ifp->if_multiaddrs, ifma_link) { 997256806Sian if (ifma->ifma_addr->sa_family != AF_LINK) 998256806Sian continue; 999262929Shrs /* 6 bits from MSB in LE CRC32 are used for hash. */ 1000262929Shrs crc = ether_crc32_le(LLADDR((struct sockaddr_dl *) 1001256806Sian ifma->ifma_addr), ETHER_ADDR_LEN); 1002262929Shrs ghash |= 1LLU << (((uint8_t *)&crc)[3] >> 2); 1003256806Sian } 1004256806Sian if_maddr_runlock(ifp); 1005256806Sian } 1006256806Sian WR4(sc, FEC_GAUR_REG, (uint32_t)(ghash >> 32)); 1007256806Sian WR4(sc, FEC_GALR_REG, (uint32_t)ghash); 1008256806Sian 1009256806Sian /* 1010256806Sian * Set the individual address filter hash. 1011256806Sian * 1012256806Sian * XXX Is 0 the right value when promiscuous is off? This hw feature 1013256806Sian * seems to support the concept of MAC address aliases, does such a 1014256806Sian * thing even exist? 1015256806Sian */ 1016256806Sian if ((ifp->if_flags & IFF_PROMISC)) 1017256806Sian ihash = 0xffffffffffffffffLLU; 1018256806Sian else { 1019256806Sian ihash = 0; 1020256806Sian } 1021256806Sian WR4(sc, FEC_IAUR_REG, (uint32_t)(ihash >> 32)); 1022256806Sian WR4(sc, FEC_IALR_REG, (uint32_t)ihash); 1023256806Sian 1024256806Sian /* 1025256806Sian * Set the primary address. 1026256806Sian */ 1027256806Sian eaddr = IF_LLADDR(ifp); 1028256806Sian WR4(sc, FEC_PALR_REG, (eaddr[0] << 24) | (eaddr[1] << 16) | 1029256806Sian (eaddr[2] << 8) | eaddr[3]); 1030256806Sian WR4(sc, FEC_PAUR_REG, (eaddr[4] << 24) | (eaddr[5] << 16)); 1031256806Sian} 1032256806Sian 1033256806Sianstatic void 1034256806Sianffec_stop_locked(struct ffec_softc *sc) 1035256806Sian{ 1036256806Sian struct ifnet *ifp; 1037256806Sian struct ffec_hwdesc *desc; 1038256806Sian struct ffec_bufmap *bmap; 1039256806Sian int idx; 1040256806Sian 1041256806Sian FFEC_ASSERT_LOCKED(sc); 1042256806Sian 1043256806Sian ifp = sc->ifp; 1044256806Sian ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 1045256806Sian sc->tx_watchdog_count = 0; 1046256806Sian 1047256806Sian /* 1048256806Sian * Stop the hardware, mask all interrupts, and clear all current 1049256806Sian * interrupt status bits. 1050256806Sian */ 1051256806Sian WR4(sc, FEC_ECR_REG, RD4(sc, FEC_ECR_REG) & ~FEC_ECR_ETHEREN); 1052256806Sian WR4(sc, FEC_IEM_REG, 0x00000000); 1053256806Sian WR4(sc, FEC_IER_REG, 0xffffffff); 1054256806Sian 1055256806Sian /* 1056256806Sian * Stop the media-check callout. Do not use callout_drain() because 1057256806Sian * we're holding a mutex the callout acquires, and if it's currently 1058256806Sian * waiting to acquire it, we'd deadlock. If it is waiting now, the 1059256806Sian * ffec_tick() routine will return without doing anything when it sees 1060256806Sian * that IFF_DRV_RUNNING is not set, so avoiding callout_drain() is safe. 1061256806Sian */ 1062256806Sian callout_stop(&sc->ffec_callout); 1063256806Sian 1064256806Sian /* 1065256806Sian * Discard all untransmitted buffers. Each buffer is simply freed; 1066256806Sian * it's as if the bits were transmitted and then lost on the wire. 1067256806Sian * 1068256806Sian * XXX Is this right? Or should we use IFQ_DRV_PREPEND() to put them 1069256806Sian * back on the queue for when we get restarted later? 1070256806Sian */ 1071256806Sian idx = sc->tx_idx_tail; 1072256806Sian while (idx != sc->tx_idx_head) { 1073256806Sian desc = &sc->txdesc_ring[idx]; 1074256806Sian bmap = &sc->txbuf_map[idx]; 1075256806Sian if (desc->buf_paddr != 0) { 1076256806Sian bus_dmamap_unload(sc->txbuf_tag, bmap->map); 1077256806Sian m_freem(bmap->mbuf); 1078256806Sian bmap->mbuf = NULL; 1079256806Sian ffec_setup_txdesc(sc, idx, 0, 0); 1080256806Sian } 1081256806Sian idx = next_txidx(sc, idx); 1082256806Sian } 1083256806Sian 1084256806Sian /* 1085256806Sian * Discard all unprocessed receive buffers. This amounts to just 1086256806Sian * pretending that nothing ever got received into them. We reuse the 1087256806Sian * mbuf already mapped for each desc, simply turning the EMPTY flags 1088256806Sian * back on so they'll get reused when we start up again. 1089256806Sian */ 1090256806Sian for (idx = 0; idx < RX_DESC_COUNT; ++idx) { 1091256806Sian desc = &sc->rxdesc_ring[idx]; 1092256806Sian ffec_setup_rxdesc(sc, idx, desc->buf_paddr); 1093256806Sian } 1094256806Sian} 1095256806Sian 1096256806Sianstatic void 1097256806Sianffec_init_locked(struct ffec_softc *sc) 1098256806Sian{ 1099256806Sian struct ifnet *ifp = sc->ifp; 1100256806Sian uint32_t maxbuf, maxfl, regval; 1101256806Sian 1102256806Sian FFEC_ASSERT_LOCKED(sc); 1103256806Sian 1104256806Sian /* 1105256806Sian * The hardware has a limit of 0x7ff as the max frame length (see 1106256806Sian * comments for MRBR below), and we use mbuf clusters as receive 1107256806Sian * buffers, and we currently are designed to receive an entire frame 1108256806Sian * into a single buffer. 1109256806Sian * 1110256806Sian * We start with a MCLBYTES-sized cluster, but we have to offset into 1111256806Sian * the buffer by ETHER_ALIGN to make room for post-receive re-alignment, 1112256806Sian * and then that value has to be rounded up to the hardware's DMA 1113256806Sian * alignment requirements, so all in all our buffer is that much smaller 1114256806Sian * than MCLBYTES. 1115256806Sian * 1116256806Sian * The resulting value is used as the frame truncation length and the 1117256806Sian * max buffer receive buffer size for now. It'll become more complex 1118256806Sian * when we support jumbo frames and receiving fragments of them into 1119256806Sian * separate buffers. 1120256806Sian */ 1121327638Sian maxbuf = MCLBYTES - roundup(ETHER_ALIGN, sc->rxbuf_align); 1122256806Sian maxfl = min(maxbuf, 0x7ff); 1123256806Sian 1124256806Sian if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1125256806Sian return; 1126256806Sian 1127256806Sian /* Mask all interrupts and clear all current interrupt status bits. */ 1128256806Sian WR4(sc, FEC_IEM_REG, 0x00000000); 1129256806Sian WR4(sc, FEC_IER_REG, 0xffffffff); 1130256806Sian 1131256806Sian /* 1132256806Sian * Go set up palr/puar, galr/gaur, ialr/iaur. 1133256806Sian */ 1134256806Sian ffec_setup_rxfilter(sc); 1135256806Sian 1136256806Sian /* 1137256806Sian * TFWR - Transmit FIFO watermark register. 1138256806Sian * 1139256806Sian * Set the transmit fifo watermark register to "store and forward" mode 1140256806Sian * and also set a threshold of 128 bytes in the fifo before transmission 1141256806Sian * of a frame begins (to avoid dma underruns). Recent FEC hardware 1142256806Sian * supports STRFWD and when that bit is set, the watermark level in the 1143256806Sian * low bits is ignored. Older hardware doesn't have STRFWD, but writing 1144256806Sian * to that bit is innocuous, and the TWFR bits get used instead. 1145256806Sian */ 1146256806Sian WR4(sc, FEC_TFWR_REG, FEC_TFWR_STRFWD | FEC_TFWR_TWFR_128BYTE); 1147256806Sian 1148256806Sian /* RCR - Receive control register. 1149256806Sian * 1150256806Sian * Set max frame length + clean out anything left from u-boot. 1151256806Sian */ 1152256806Sian WR4(sc, FEC_RCR_REG, (maxfl << FEC_RCR_MAX_FL_SHIFT)); 1153256806Sian 1154256806Sian /* 1155256806Sian * TCR - Transmit control register. 1156256806Sian * 1157256806Sian * Clean out anything left from u-boot. Any necessary values are set in 1158256806Sian * ffec_miibus_statchg() based on the media type. 1159256806Sian */ 1160256806Sian WR4(sc, FEC_TCR_REG, 0); 1161256806Sian 1162256806Sian /* 1163256806Sian * OPD - Opcode/pause duration. 1164256806Sian * 1165256806Sian * XXX These magic numbers come from u-boot. 1166256806Sian */ 1167256806Sian WR4(sc, FEC_OPD_REG, 0x00010020); 1168256806Sian 1169256806Sian /* 1170256806Sian * FRSR - Fifo receive start register. 1171256806Sian * 1172256806Sian * This register does not exist on imx6, it is present on earlier 1173256806Sian * hardware. The u-boot code sets this to a non-default value that's 32 1174256806Sian * bytes larger than the default, with no clue as to why. The default 1175256806Sian * value should work fine, so there's no code to init it here. 1176256806Sian */ 1177256806Sian 1178256806Sian /* 1179256806Sian * MRBR - Max RX buffer size. 1180256806Sian * 1181256806Sian * Note: For hardware prior to imx6 this value cannot exceed 0x07ff, 1182256806Sian * but the datasheet says no such thing for imx6. On the imx6, setting 1183256806Sian * this to 2K without setting EN1588 resulted in a crazy runaway 1184256806Sian * receive loop in the hardware, where every rx descriptor in the ring 1185256806Sian * had its EMPTY flag cleared, no completion or error flags set, and a 1186256806Sian * length of zero. I think maybe you can only exceed it when EN1588 is 1187256806Sian * set, like maybe that's what enables jumbo frames, because in general 1188256806Sian * the EN1588 flag seems to be the "enable new stuff" vs. "be legacy- 1189256806Sian * compatible" flag. 1190256806Sian */ 1191256806Sian WR4(sc, FEC_MRBR_REG, maxfl << FEC_MRBR_R_BUF_SIZE_SHIFT); 1192256806Sian 1193256806Sian /* 1194256806Sian * FTRL - Frame truncation length. 1195256806Sian * 1196256806Sian * Must be greater than or equal to the value set in FEC_RCR_MAXFL. 1197256806Sian */ 1198256806Sian WR4(sc, FEC_FTRL_REG, maxfl); 1199256806Sian 1200256806Sian /* 1201256806Sian * RDSR / TDSR descriptor ring pointers. 1202256806Sian * 1203256806Sian * When we turn on ECR_ETHEREN at the end, the hardware zeroes its 1204256806Sian * internal current descriptor index values for both rings, so we zero 1205256806Sian * our index values as well. 1206256806Sian */ 1207256806Sian sc->rx_idx = 0; 1208256806Sian sc->tx_idx_head = sc->tx_idx_tail = 0; 1209256806Sian sc->txcount = 0; 1210256806Sian WR4(sc, FEC_RDSR_REG, sc->rxdesc_ring_paddr); 1211256806Sian WR4(sc, FEC_TDSR_REG, sc->txdesc_ring_paddr); 1212256806Sian 1213256806Sian /* 1214256806Sian * EIM - interrupt mask register. 1215256806Sian * 1216256806Sian * We always enable the same set of interrupts while running; unlike 1217256806Sian * some drivers there's no need to change the mask on the fly depending 1218256806Sian * on what operations are in progress. 1219256806Sian */ 1220256806Sian WR4(sc, FEC_IEM_REG, FEC_IER_TXF | FEC_IER_RXF | FEC_IER_EBERR); 1221256806Sian 1222256806Sian /* 1223323411Sian * MIBC - MIB control (hardware stats); clear all statistics regs, then 1224323411Sian * enable collection of statistics. 1225256806Sian */ 1226256806Sian regval = RD4(sc, FEC_MIBC_REG); 1227256806Sian WR4(sc, FEC_MIBC_REG, regval | FEC_MIBC_DIS); 1228256806Sian ffec_clear_stats(sc); 1229256806Sian WR4(sc, FEC_MIBC_REG, regval & ~FEC_MIBC_DIS); 1230256806Sian 1231327638Sian if (sc->fecflags & FECFLAG_RACC) { 1232327638Sian /* 1233327638Sian * RACC - Receive Accelerator Function Configuration. 1234327638Sian */ 1235327638Sian regval = RD4(sc, FEC_RACC_REG); 1236327638Sian WR4(sc, FEC_RACC_REG, regval | FEC_RACC_SHIFT16); 1237327638Sian } 1238327638Sian 1239256806Sian /* 1240256806Sian * ECR - Ethernet control register. 1241256806Sian * 1242256806Sian * This must happen after all the other config registers are set. If 1243256806Sian * we're running on little-endian hardware, also set the flag for byte- 1244256806Sian * swapping descriptor ring entries. This flag doesn't exist on older 1245256806Sian * hardware, but it can be safely set -- the bit position it occupies 1246256806Sian * was unused. 1247256806Sian */ 1248256806Sian regval = RD4(sc, FEC_ECR_REG); 1249256806Sian#if _BYTE_ORDER == _LITTLE_ENDIAN 1250256806Sian regval |= FEC_ECR_DBSWP; 1251256806Sian#endif 1252256806Sian regval |= FEC_ECR_ETHEREN; 1253256806Sian WR4(sc, FEC_ECR_REG, regval); 1254256806Sian 1255256806Sian ifp->if_drv_flags |= IFF_DRV_RUNNING; 1256256806Sian 1257256806Sian /* 1258256806Sian * Call mii_mediachg() which will call back into ffec_miibus_statchg() to 1259256806Sian * set up the remaining config registers based on the current media. 1260256806Sian */ 1261256806Sian mii_mediachg(sc->mii_softc); 1262256806Sian callout_reset(&sc->ffec_callout, hz, ffec_tick, sc); 1263256806Sian 1264256806Sian /* 1265256806Sian * Tell the hardware that receive buffers are available. They were made 1266256806Sian * available in ffec_attach() or ffec_stop(). 1267256806Sian */ 1268256806Sian WR4(sc, FEC_RDAR_REG, FEC_RDAR_RDAR); 1269256806Sian} 1270256806Sian 1271256806Sianstatic void 1272256806Sianffec_init(void *if_softc) 1273256806Sian{ 1274256806Sian struct ffec_softc *sc = if_softc; 1275256806Sian 1276256806Sian FFEC_LOCK(sc); 1277256806Sian ffec_init_locked(sc); 1278256806Sian FFEC_UNLOCK(sc); 1279256806Sian} 1280256806Sian 1281256806Sianstatic void 1282256806Sianffec_intr(void *arg) 1283256806Sian{ 1284256806Sian struct ffec_softc *sc; 1285256806Sian uint32_t ier; 1286256806Sian 1287256806Sian sc = arg; 1288256806Sian 1289256806Sian FFEC_LOCK(sc); 1290256806Sian 1291256806Sian ier = RD4(sc, FEC_IER_REG); 1292256806Sian 1293256806Sian if (ier & FEC_IER_TXF) { 1294256806Sian WR4(sc, FEC_IER_REG, FEC_IER_TXF); 1295256806Sian ffec_txfinish_locked(sc); 1296256806Sian } 1297256806Sian 1298256806Sian if (ier & FEC_IER_RXF) { 1299256806Sian WR4(sc, FEC_IER_REG, FEC_IER_RXF); 1300256806Sian ffec_rxfinish_locked(sc); 1301256806Sian } 1302256806Sian 1303256806Sian /* 1304256806Sian * We actually don't care about most errors, because the hardware copes 1305256806Sian * with them just fine, discarding the incoming bad frame, or forcing a 1306256806Sian * bad CRC onto an outgoing bad frame, and counting the errors in the 1307256806Sian * stats registers. The one that really matters is EBERR (DMA bus 1308256806Sian * error) because the hardware automatically clears ECR[ETHEREN] and we 1309256806Sian * have to restart it here. It should never happen. 1310256806Sian */ 1311256806Sian if (ier & FEC_IER_EBERR) { 1312256806Sian WR4(sc, FEC_IER_REG, FEC_IER_EBERR); 1313256806Sian device_printf(sc->dev, 1314256806Sian "Ethernet DMA error, restarting controller.\n"); 1315256806Sian ffec_stop_locked(sc); 1316256806Sian ffec_init_locked(sc); 1317256806Sian } 1318256806Sian 1319256806Sian FFEC_UNLOCK(sc); 1320256806Sian 1321256806Sian} 1322256806Sian 1323256806Sianstatic int 1324256806Sianffec_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1325256806Sian{ 1326256806Sian struct ffec_softc *sc; 1327256806Sian struct mii_data *mii; 1328256806Sian struct ifreq *ifr; 1329256806Sian int mask, error; 1330256806Sian 1331256806Sian sc = ifp->if_softc; 1332256806Sian ifr = (struct ifreq *)data; 1333256806Sian 1334256806Sian error = 0; 1335256806Sian switch (cmd) { 1336256806Sian case SIOCSIFFLAGS: 1337256806Sian FFEC_LOCK(sc); 1338256806Sian if (ifp->if_flags & IFF_UP) { 1339256806Sian if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 1340256806Sian if ((ifp->if_flags ^ sc->if_flags) & 1341256806Sian (IFF_PROMISC | IFF_ALLMULTI)) 1342256806Sian ffec_setup_rxfilter(sc); 1343256806Sian } else { 1344256806Sian if (!sc->is_detaching) 1345256806Sian ffec_init_locked(sc); 1346256806Sian } 1347256806Sian } else { 1348256806Sian if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1349256806Sian ffec_stop_locked(sc); 1350256806Sian } 1351256806Sian sc->if_flags = ifp->if_flags; 1352256806Sian FFEC_UNLOCK(sc); 1353256806Sian break; 1354256806Sian 1355256806Sian case SIOCADDMULTI: 1356256806Sian case SIOCDELMULTI: 1357256806Sian if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 1358256806Sian FFEC_LOCK(sc); 1359256806Sian ffec_setup_rxfilter(sc); 1360256806Sian FFEC_UNLOCK(sc); 1361256806Sian } 1362256806Sian break; 1363256806Sian 1364256806Sian case SIOCSIFMEDIA: 1365256806Sian case SIOCGIFMEDIA: 1366256806Sian mii = sc->mii_softc; 1367256806Sian error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd); 1368256806Sian break; 1369256806Sian 1370256806Sian case SIOCSIFCAP: 1371256806Sian mask = ifp->if_capenable ^ ifr->ifr_reqcap; 1372256806Sian if (mask & IFCAP_VLAN_MTU) { 1373256806Sian /* No work to do except acknowledge the change took. */ 1374256806Sian ifp->if_capenable ^= IFCAP_VLAN_MTU; 1375256806Sian } 1376256806Sian break; 1377256806Sian 1378256806Sian default: 1379256806Sian error = ether_ioctl(ifp, cmd, data); 1380256806Sian break; 1381256806Sian } 1382256806Sian 1383256806Sian return (error); 1384256806Sian} 1385256806Sian 1386256806Sianstatic int 1387256806Sianffec_detach(device_t dev) 1388256806Sian{ 1389256806Sian struct ffec_softc *sc; 1390256806Sian bus_dmamap_t map; 1391327638Sian int idx, irq; 1392256806Sian 1393256806Sian /* 1394256806Sian * NB: This function can be called internally to unwind a failure to 1395256806Sian * attach. Make sure a resource got allocated/created before destroying. 1396256806Sian */ 1397256806Sian 1398256806Sian sc = device_get_softc(dev); 1399256806Sian 1400256806Sian if (sc->is_attached) { 1401256806Sian FFEC_LOCK(sc); 1402256806Sian sc->is_detaching = true; 1403256806Sian ffec_stop_locked(sc); 1404256806Sian FFEC_UNLOCK(sc); 1405256806Sian callout_drain(&sc->ffec_callout); 1406256806Sian ether_ifdetach(sc->ifp); 1407256806Sian } 1408256806Sian 1409256806Sian /* XXX no miibus detach? */ 1410256806Sian 1411256806Sian /* Clean up RX DMA resources and free mbufs. */ 1412256806Sian for (idx = 0; idx < RX_DESC_COUNT; ++idx) { 1413256806Sian if ((map = sc->rxbuf_map[idx].map) != NULL) { 1414256806Sian bus_dmamap_unload(sc->rxbuf_tag, map); 1415256806Sian bus_dmamap_destroy(sc->rxbuf_tag, map); 1416256806Sian m_freem(sc->rxbuf_map[idx].mbuf); 1417256806Sian } 1418256806Sian } 1419256806Sian if (sc->rxbuf_tag != NULL) 1420256806Sian bus_dma_tag_destroy(sc->rxbuf_tag); 1421256806Sian if (sc->rxdesc_map != NULL) { 1422256806Sian bus_dmamap_unload(sc->rxdesc_tag, sc->rxdesc_map); 1423256806Sian bus_dmamap_destroy(sc->rxdesc_tag, sc->rxdesc_map); 1424256806Sian } 1425256806Sian if (sc->rxdesc_tag != NULL) 1426256806Sian bus_dma_tag_destroy(sc->rxdesc_tag); 1427256806Sian 1428256806Sian /* Clean up TX DMA resources. */ 1429256806Sian for (idx = 0; idx < TX_DESC_COUNT; ++idx) { 1430256806Sian if ((map = sc->txbuf_map[idx].map) != NULL) { 1431256806Sian /* TX maps are already unloaded. */ 1432256806Sian bus_dmamap_destroy(sc->txbuf_tag, map); 1433256806Sian } 1434256806Sian } 1435256806Sian if (sc->txbuf_tag != NULL) 1436256806Sian bus_dma_tag_destroy(sc->txbuf_tag); 1437256806Sian if (sc->txdesc_map != NULL) { 1438256806Sian bus_dmamap_unload(sc->txdesc_tag, sc->txdesc_map); 1439256806Sian bus_dmamap_destroy(sc->txdesc_tag, sc->txdesc_map); 1440256806Sian } 1441256806Sian if (sc->txdesc_tag != NULL) 1442327638Sian bus_dma_tag_destroy(sc->txdesc_tag); 1443256806Sian 1444256806Sian /* Release bus resources. */ 1445327638Sian for (irq = 0; irq < MAX_IRQ_COUNT; ++irq) { 1446327638Sian if (sc->intr_cookie[irq] != NULL) { 1447327638Sian bus_teardown_intr(dev, sc->irq_res[irq], 1448327638Sian sc->intr_cookie[irq]); 1449327638Sian } 1450327638Sian } 1451327638Sian bus_release_resources(dev, irq_res_spec, sc->irq_res); 1452256806Sian 1453256806Sian if (sc->mem_res != NULL) 1454256806Sian bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->mem_res); 1455256806Sian 1456256806Sian FFEC_LOCK_DESTROY(sc); 1457256806Sian return (0); 1458256806Sian} 1459256806Sian 1460256806Sianstatic int 1461256806Sianffec_attach(device_t dev) 1462256806Sian{ 1463256806Sian struct ffec_softc *sc; 1464256806Sian struct ifnet *ifp = NULL; 1465256806Sian struct mbuf *m; 1466323410Sian void *dummy; 1467327638Sian uintptr_t typeflags; 1468256806Sian phandle_t ofw_node; 1469327638Sian uint32_t idx, mscr; 1470327638Sian int error, phynum, rid, irq; 1471256806Sian uint8_t eaddr[ETHER_ADDR_LEN]; 1472256806Sian 1473256806Sian sc = device_get_softc(dev); 1474256806Sian sc->dev = dev; 1475256806Sian 1476256806Sian FFEC_LOCK_INIT(sc); 1477256806Sian 1478256806Sian /* 1479256806Sian * There are differences in the implementation and features of the FEC 1480256806Sian * hardware on different SoCs, so figure out what type we are. 1481256806Sian */ 1482327638Sian typeflags = ofw_bus_search_compatible(dev, compat_data)->ocd_data; 1483327638Sian sc->fectype = (uint8_t)(typeflags & FECTYPE_MASK); 1484327638Sian sc->fecflags = (uint32_t)(typeflags & ~FECTYPE_MASK); 1485256806Sian 1486327638Sian if (sc->fecflags & FECFLAG_AVB) { 1487327638Sian sc->rxbuf_align = 64; 1488327638Sian sc->txbuf_align = 1; 1489327638Sian } else { 1490327638Sian sc->rxbuf_align = 16; 1491327638Sian sc->txbuf_align = 16; 1492327638Sian } 1493327638Sian 1494256806Sian /* 1495256806Sian * We have to be told what kind of electrical connection exists between 1496256806Sian * the MAC and PHY or we can't operate correctly. 1497256806Sian */ 1498256806Sian if ((ofw_node = ofw_bus_get_node(dev)) == -1) { 1499256806Sian device_printf(dev, "Impossible: Can't find ofw bus node\n"); 1500256806Sian error = ENXIO; 1501256806Sian goto out; 1502256806Sian } 1503323414Sian sc->phy_conn_type = mii_fdt_get_contype(ofw_node); 1504323414Sian if (sc->phy_conn_type == MII_CONTYPE_UNKNOWN) { 1505256806Sian device_printf(sc->dev, "No valid 'phy-mode' " 1506256806Sian "property found in FDT data for device.\n"); 1507256806Sian error = ENOATTR; 1508256806Sian goto out; 1509256806Sian } 1510256806Sian 1511256806Sian callout_init_mtx(&sc->ffec_callout, &sc->mtx, 0); 1512256806Sian 1513256806Sian /* Allocate bus resources for accessing the hardware. */ 1514256806Sian rid = 0; 1515256806Sian sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 1516256806Sian RF_ACTIVE); 1517256806Sian if (sc->mem_res == NULL) { 1518256806Sian device_printf(dev, "could not allocate memory resources.\n"); 1519256806Sian error = ENOMEM; 1520256806Sian goto out; 1521256806Sian } 1522327638Sian 1523327638Sian error = bus_alloc_resources(dev, irq_res_spec, sc->irq_res); 1524327638Sian if (error != 0) { 1525327638Sian device_printf(dev, "could not allocate interrupt resources\n"); 1526256806Sian goto out; 1527256806Sian } 1528256806Sian 1529256806Sian /* 1530256806Sian * Set up TX descriptor ring, descriptors, and dma maps. 1531256806Sian */ 1532256806Sian error = bus_dma_tag_create( 1533256806Sian bus_get_dma_tag(dev), /* Parent tag. */ 1534256806Sian FEC_DESC_RING_ALIGN, 0, /* alignment, boundary */ 1535256806Sian BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 1536256806Sian BUS_SPACE_MAXADDR, /* highaddr */ 1537256806Sian NULL, NULL, /* filter, filterarg */ 1538256806Sian TX_DESC_SIZE, 1, /* maxsize, nsegments */ 1539256806Sian TX_DESC_SIZE, /* maxsegsize */ 1540256806Sian 0, /* flags */ 1541256806Sian NULL, NULL, /* lockfunc, lockarg */ 1542256806Sian &sc->txdesc_tag); 1543256806Sian if (error != 0) { 1544256806Sian device_printf(sc->dev, 1545256806Sian "could not create TX ring DMA tag.\n"); 1546256806Sian goto out; 1547256806Sian } 1548256806Sian 1549256806Sian error = bus_dmamem_alloc(sc->txdesc_tag, (void**)&sc->txdesc_ring, 1550256806Sian BUS_DMA_COHERENT | BUS_DMA_WAITOK | BUS_DMA_ZERO, &sc->txdesc_map); 1551256806Sian if (error != 0) { 1552256806Sian device_printf(sc->dev, 1553256806Sian "could not allocate TX descriptor ring.\n"); 1554256806Sian goto out; 1555256806Sian } 1556256806Sian 1557256806Sian error = bus_dmamap_load(sc->txdesc_tag, sc->txdesc_map, sc->txdesc_ring, 1558256806Sian TX_DESC_SIZE, ffec_get1paddr, &sc->txdesc_ring_paddr, 0); 1559256806Sian if (error != 0) { 1560256806Sian device_printf(sc->dev, 1561256806Sian "could not load TX descriptor ring map.\n"); 1562256806Sian goto out; 1563256806Sian } 1564256806Sian 1565256806Sian error = bus_dma_tag_create( 1566256806Sian bus_get_dma_tag(dev), /* Parent tag. */ 1567327638Sian sc->txbuf_align, 0, /* alignment, boundary */ 1568256806Sian BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 1569256806Sian BUS_SPACE_MAXADDR, /* highaddr */ 1570256806Sian NULL, NULL, /* filter, filterarg */ 1571256806Sian MCLBYTES, 1, /* maxsize, nsegments */ 1572256806Sian MCLBYTES, /* maxsegsize */ 1573256806Sian 0, /* flags */ 1574256806Sian NULL, NULL, /* lockfunc, lockarg */ 1575256806Sian &sc->txbuf_tag); 1576256806Sian if (error != 0) { 1577256806Sian device_printf(sc->dev, 1578256806Sian "could not create TX ring DMA tag.\n"); 1579256806Sian goto out; 1580256806Sian } 1581256806Sian 1582256806Sian for (idx = 0; idx < TX_DESC_COUNT; ++idx) { 1583256806Sian error = bus_dmamap_create(sc->txbuf_tag, 0, 1584256806Sian &sc->txbuf_map[idx].map); 1585256806Sian if (error != 0) { 1586256806Sian device_printf(sc->dev, 1587256806Sian "could not create TX buffer DMA map.\n"); 1588256806Sian goto out; 1589256806Sian } 1590256806Sian ffec_setup_txdesc(sc, idx, 0, 0); 1591256806Sian } 1592256806Sian 1593256806Sian /* 1594256806Sian * Set up RX descriptor ring, descriptors, dma maps, and mbufs. 1595256806Sian */ 1596256806Sian error = bus_dma_tag_create( 1597256806Sian bus_get_dma_tag(dev), /* Parent tag. */ 1598256806Sian FEC_DESC_RING_ALIGN, 0, /* alignment, boundary */ 1599256806Sian BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 1600256806Sian BUS_SPACE_MAXADDR, /* highaddr */ 1601256806Sian NULL, NULL, /* filter, filterarg */ 1602256806Sian RX_DESC_SIZE, 1, /* maxsize, nsegments */ 1603256806Sian RX_DESC_SIZE, /* maxsegsize */ 1604256806Sian 0, /* flags */ 1605256806Sian NULL, NULL, /* lockfunc, lockarg */ 1606256806Sian &sc->rxdesc_tag); 1607256806Sian if (error != 0) { 1608256806Sian device_printf(sc->dev, 1609256806Sian "could not create RX ring DMA tag.\n"); 1610256806Sian goto out; 1611256806Sian } 1612256806Sian 1613256806Sian error = bus_dmamem_alloc(sc->rxdesc_tag, (void **)&sc->rxdesc_ring, 1614256806Sian BUS_DMA_COHERENT | BUS_DMA_WAITOK | BUS_DMA_ZERO, &sc->rxdesc_map); 1615256806Sian if (error != 0) { 1616256806Sian device_printf(sc->dev, 1617256806Sian "could not allocate RX descriptor ring.\n"); 1618256806Sian goto out; 1619256806Sian } 1620256806Sian 1621256806Sian error = bus_dmamap_load(sc->rxdesc_tag, sc->rxdesc_map, sc->rxdesc_ring, 1622256806Sian RX_DESC_SIZE, ffec_get1paddr, &sc->rxdesc_ring_paddr, 0); 1623256806Sian if (error != 0) { 1624256806Sian device_printf(sc->dev, 1625256806Sian "could not load RX descriptor ring map.\n"); 1626256806Sian goto out; 1627256806Sian } 1628256806Sian 1629256806Sian error = bus_dma_tag_create( 1630256806Sian bus_get_dma_tag(dev), /* Parent tag. */ 1631256806Sian 1, 0, /* alignment, boundary */ 1632256806Sian BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 1633256806Sian BUS_SPACE_MAXADDR, /* highaddr */ 1634256806Sian NULL, NULL, /* filter, filterarg */ 1635256806Sian MCLBYTES, 1, /* maxsize, nsegments */ 1636256806Sian MCLBYTES, /* maxsegsize */ 1637256806Sian 0, /* flags */ 1638256806Sian NULL, NULL, /* lockfunc, lockarg */ 1639256806Sian &sc->rxbuf_tag); 1640256806Sian if (error != 0) { 1641256806Sian device_printf(sc->dev, 1642256806Sian "could not create RX buf DMA tag.\n"); 1643256806Sian goto out; 1644256806Sian } 1645256806Sian 1646256806Sian for (idx = 0; idx < RX_DESC_COUNT; ++idx) { 1647256806Sian error = bus_dmamap_create(sc->rxbuf_tag, 0, 1648256806Sian &sc->rxbuf_map[idx].map); 1649256806Sian if (error != 0) { 1650256806Sian device_printf(sc->dev, 1651256806Sian "could not create RX buffer DMA map.\n"); 1652256806Sian goto out; 1653256806Sian } 1654256806Sian if ((m = ffec_alloc_mbufcl(sc)) == NULL) { 1655256806Sian device_printf(dev, "Could not alloc mbuf\n"); 1656256806Sian error = ENOMEM; 1657256806Sian goto out; 1658256806Sian } 1659256806Sian if ((error = ffec_setup_rxbuf(sc, idx, m)) != 0) { 1660256806Sian device_printf(sc->dev, 1661256806Sian "could not create new RX buffer.\n"); 1662256806Sian goto out; 1663256806Sian } 1664256806Sian } 1665256806Sian 1666256806Sian /* Try to get the MAC address from the hardware before resetting it. */ 1667256806Sian ffec_get_hwaddr(sc, eaddr); 1668256806Sian 1669327638Sian /* 1670327638Sian * Reset the hardware. Disables all interrupts. 1671327638Sian * 1672327638Sian * When the FEC is connected to the AXI bus (indicated by AVB flag), a 1673327638Sian * MAC reset while a bus transaction is pending can hang the bus. 1674327638Sian * Instead of resetting, turn off the ENABLE bit, which allows the 1675327638Sian * hardware to complete any in-progress transfers (appending a bad CRC 1676327638Sian * to any partial packet) and release the AXI bus. This could probably 1677327638Sian * be done unconditionally for all hardware variants, but that hasn't 1678327638Sian * been tested. 1679327638Sian */ 1680327638Sian if (sc->fecflags & FECFLAG_AVB) 1681327638Sian WR4(sc, FEC_ECR_REG, 0); 1682327638Sian else 1683327638Sian WR4(sc, FEC_ECR_REG, FEC_ECR_RESET); 1684256806Sian 1685256806Sian /* Setup interrupt handler. */ 1686327638Sian for (irq = 0; irq < MAX_IRQ_COUNT; ++irq) { 1687327638Sian if (sc->irq_res[irq] != NULL) { 1688327638Sian error = bus_setup_intr(dev, sc->irq_res[irq], 1689327638Sian INTR_TYPE_NET | INTR_MPSAFE, NULL, ffec_intr, sc, 1690327638Sian &sc->intr_cookie[irq]); 1691327638Sian if (error != 0) { 1692327638Sian device_printf(dev, 1693327638Sian "could not setup interrupt handler.\n"); 1694327638Sian goto out; 1695327638Sian } 1696327638Sian } 1697256806Sian } 1698256806Sian 1699256806Sian /* 1700256806Sian * Set up the PHY control register. 1701256806Sian * 1702256806Sian * Speed formula for ENET is md_clock = mac_clock / ((N + 1) * 2). 1703256806Sian * Speed formula for FEC is md_clock = mac_clock / (N * 2) 1704256806Sian * 1705256806Sian * XXX - Revisit this... 1706256806Sian * 1707256806Sian * For a Wandboard imx6 (ENET) I was originally using 4, but the uboot 1708256806Sian * code uses 10. Both values seem to work, but I suspect many modern 1709256806Sian * PHY parts can do mdio at speeds far above the standard 2.5 MHz. 1710256806Sian * 1711256806Sian * Different imx manuals use confusingly different terminology (things 1712256806Sian * like "system clock" and "internal module clock") with examples that 1713256806Sian * use frequencies that have nothing to do with ethernet, giving the 1714256806Sian * vague impression that maybe the clock in question is the periphclock 1715256806Sian * or something. In fact, on an imx53 development board (FEC), 1716256806Sian * measuring the mdio clock at the pin on the PHY and playing with 1717256806Sian * various divisors showed that the root speed was 66 MHz (clk_ipg_root 1718256806Sian * aka periphclock) and 13 was the right divisor. 1719256806Sian * 1720256806Sian * All in all, it seems likely that 13 is a safe divisor for now, 1721256806Sian * because if we really do need to base it on the peripheral clock 1722256806Sian * speed, then we need a platform-independant get-clock-freq API. 1723256806Sian */ 1724256806Sian mscr = 13 << FEC_MSCR_MII_SPEED_SHIFT; 1725256806Sian if (OF_hasprop(ofw_node, "phy-disable-preamble")) { 1726256806Sian mscr |= FEC_MSCR_DIS_PRE; 1727256806Sian if (bootverbose) 1728256806Sian device_printf(dev, "PHY preamble disabled\n"); 1729256806Sian } 1730256806Sian WR4(sc, FEC_MSCR_REG, mscr); 1731256806Sian 1732256806Sian /* Set up the ethernet interface. */ 1733256806Sian sc->ifp = ifp = if_alloc(IFT_ETHER); 1734256806Sian 1735256806Sian ifp->if_softc = sc; 1736256806Sian if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1737256806Sian ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1738256806Sian ifp->if_capabilities = IFCAP_VLAN_MTU; 1739256806Sian ifp->if_capenable = ifp->if_capabilities; 1740256806Sian ifp->if_start = ffec_txstart; 1741256806Sian ifp->if_ioctl = ffec_ioctl; 1742256806Sian ifp->if_init = ffec_init; 1743256806Sian IFQ_SET_MAXLEN(&ifp->if_snd, TX_DESC_COUNT - 1); 1744256806Sian ifp->if_snd.ifq_drv_maxlen = TX_DESC_COUNT - 1; 1745256806Sian IFQ_SET_READY(&ifp->if_snd); 1746270856Sglebius ifp->if_hdrlen = sizeof(struct ether_vlan_header); 1747256806Sian 1748256806Sian#if 0 /* XXX The hardware keeps stats we could use for these. */ 1749256806Sian ifp->if_linkmib = &sc->mibdata; 1750256806Sian ifp->if_linkmiblen = sizeof(sc->mibdata); 1751256806Sian#endif 1752256806Sian 1753256806Sian /* Set up the miigasket hardware (if any). */ 1754256806Sian ffec_miigasket_setup(sc); 1755256806Sian 1756256806Sian /* Attach the mii driver. */ 1757323410Sian if (fdt_get_phyaddr(ofw_node, dev, &phynum, &dummy) != 0) { 1758323410Sian phynum = MII_PHY_ANY; 1759323410Sian } 1760256806Sian error = mii_attach(dev, &sc->miibus, ifp, ffec_media_change, 1761323410Sian ffec_media_status, BMSR_DEFCAPMASK, phynum, MII_OFFSET_ANY, 1762327638Sian (sc->fecflags & FECTYPE_MVF) ? MIIF_FORCEANEG : 0); 1763256806Sian if (error != 0) { 1764256806Sian device_printf(dev, "PHY attach failed\n"); 1765256806Sian goto out; 1766256806Sian } 1767256806Sian sc->mii_softc = device_get_softc(sc->miibus); 1768256806Sian 1769256806Sian /* All ready to run, attach the ethernet interface. */ 1770256806Sian ether_ifattach(ifp, eaddr); 1771256806Sian sc->is_attached = true; 1772256806Sian 1773256806Sian error = 0; 1774256806Sianout: 1775256806Sian 1776256806Sian if (error != 0) 1777256806Sian ffec_detach(dev); 1778256806Sian 1779256806Sian return (error); 1780256806Sian} 1781256806Sian 1782256806Sianstatic int 1783256806Sianffec_probe(device_t dev) 1784256806Sian{ 1785257167Sian uintptr_t fectype; 1786256806Sian 1787261410Sian if (!ofw_bus_status_okay(dev)) 1788261410Sian return (ENXIO); 1789261410Sian 1790257167Sian fectype = ofw_bus_search_compatible(dev, compat_data)->ocd_data; 1791257167Sian if (fectype == FECTYPE_NONE) 1792256806Sian return (ENXIO); 1793257167Sian 1794257167Sian device_set_desc(dev, (fectype & FECFLAG_GBE) ? 1795257167Sian "Freescale Gigabit Ethernet Controller" : 1796257167Sian "Freescale Fast Ethernet Controller"); 1797257167Sian 1798256806Sian return (BUS_PROBE_DEFAULT); 1799256806Sian} 1800256806Sian 1801256806Sian 1802256806Sianstatic device_method_t ffec_methods[] = { 1803256806Sian /* Device interface. */ 1804256806Sian DEVMETHOD(device_probe, ffec_probe), 1805256806Sian DEVMETHOD(device_attach, ffec_attach), 1806256806Sian DEVMETHOD(device_detach, ffec_detach), 1807256806Sian 1808256806Sian/* 1809256806Sian DEVMETHOD(device_shutdown, ffec_shutdown), 1810256806Sian DEVMETHOD(device_suspend, ffec_suspend), 1811256806Sian DEVMETHOD(device_resume, ffec_resume), 1812256806Sian*/ 1813256806Sian 1814256806Sian /* MII interface. */ 1815256806Sian DEVMETHOD(miibus_readreg, ffec_miibus_readreg), 1816256806Sian DEVMETHOD(miibus_writereg, ffec_miibus_writereg), 1817256806Sian DEVMETHOD(miibus_statchg, ffec_miibus_statchg), 1818256806Sian 1819256806Sian DEVMETHOD_END 1820256806Sian}; 1821256806Sian 1822256806Sianstatic driver_t ffec_driver = { 1823256806Sian "ffec", 1824256806Sian ffec_methods, 1825256806Sian sizeof(struct ffec_softc) 1826256806Sian}; 1827256806Sian 1828256806Sianstatic devclass_t ffec_devclass; 1829256806Sian 1830256806SianDRIVER_MODULE(ffec, simplebus, ffec_driver, ffec_devclass, 0, 0); 1831256806SianDRIVER_MODULE(miibus, ffec, miibus_driver, miibus_devclass, 0, 0); 1832256806Sian 1833256806SianMODULE_DEPEND(ffec, ether, 1, 1, 1); 1834256806SianMODULE_DEPEND(ffec, miibus, 1, 1, 1); 1835