1/*- 2 * Copyright (c) 2013 Ian Lepore <ian@freebsd.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 */ 27 28#include <sys/cdefs.h> 29__FBSDID("$FreeBSD: stable/11/sys/dev/ffec/if_ffec.c 338992 2018-09-28 10:02:47Z ae $"); 30 31/* 32 * Driver for Freescale Fast Ethernet Controller, found on imx-series SoCs among 33 * others. Also works for the ENET Gigibit controller found on imx6 and imx28, 34 * but the driver doesn't currently use any of the ENET advanced features other 35 * than enabling gigabit. 36 * 37 * The interface name 'fec' is already taken by netgraph's Fast Etherchannel 38 * (netgraph/ng_fec.c), so we use 'ffec'. 39 * 40 * Requires an FDT entry with at least these properties: 41 * fec: ethernet@02188000 { 42 * compatible = "fsl,imxNN-fec"; 43 * reg = <0x02188000 0x4000>; 44 * interrupts = <150 151>; 45 * phy-mode = "rgmii"; 46 * phy-disable-preamble; // optional 47 * }; 48 * The second interrupt number is for IEEE-1588, and is not currently used; it 49 * need not be present. phy-mode must be one of: "mii", "rmii", "rgmii". 50 * There is also an optional property, phy-disable-preamble, which if present 51 * will disable the preamble bits, cutting the size of each mdio transaction 52 * (and thus the busy-wait time) in half. 53 */ 54 55#include <sys/param.h> 56#include <sys/systm.h> 57#include <sys/bus.h> 58#include <sys/endian.h> 59#include <sys/kernel.h> 60#include <sys/lock.h> 61#include <sys/malloc.h> 62#include <sys/mbuf.h> 63#include <sys/module.h> 64#include <sys/mutex.h> 65#include <sys/rman.h> 66#include <sys/socket.h> 67#include <sys/sockio.h> 68#include <sys/sysctl.h> 69 70#include <machine/bus.h> 71 72#include <net/bpf.h> 73#include <net/if.h> 74#include <net/ethernet.h> 75#include <net/if_dl.h> 76#include <net/if_media.h> 77#include <net/if_types.h> 78#include <net/if_var.h> 79#include <net/if_vlan_var.h> 80 81#include <dev/fdt/fdt_common.h> 82#include <dev/ffec/if_ffecreg.h> 83#include <dev/ofw/ofw_bus.h> 84#include <dev/ofw/ofw_bus_subr.h> 85#include <dev/mii/mii.h> 86#include <dev/mii/miivar.h> 87#include <dev/mii/mii_fdt.h> 88#include "miibus_if.h" 89 90/* 91 * There are small differences in the hardware on various SoCs. Not every SoC 92 * we support has its own FECTYPE; most work as GENERIC and only the ones that 93 * need different handling get their own entry. In addition to the types in 94 * this list, there are some flags below that can be ORed into the upper bits. 95 */ 96enum { 97 FECTYPE_NONE, 98 FECTYPE_GENERIC, 99 FECTYPE_IMX53, 100 FECTYPE_IMX6, /* imx6 and imx7 */ 101 FECTYPE_MVF, 102}; 103 104/* 105 * Flags that describe general differences between the FEC hardware in various 106 * SoCs. These are ORed into the FECTYPE enum values in the ofw_compat_data, so 107 * the low 8 bits are reserved for the type enum. In the softc, the type and 108 * flags are put into separate members, so that you don't need to mask the flags 109 * out of the type to compare it. 110 */ 111#define FECTYPE_MASK 0x000000ff 112#define FECFLAG_GBE (1 << 8) 113#define FECFLAG_AVB (1 << 9) 114#define FECFLAG_RACC (1 << 10) 115 116/* 117 * Table of supported FDT compat strings and their associated FECTYPE values. 118 */ 119static struct ofw_compat_data compat_data[] = { 120 {"fsl,imx51-fec", FECTYPE_GENERIC}, 121 {"fsl,imx53-fec", FECTYPE_IMX53}, 122 {"fsl,imx6q-fec", FECTYPE_IMX6 | FECFLAG_RACC | FECFLAG_GBE }, 123 {"fsl,imx6ul-fec", FECTYPE_IMX6 | FECFLAG_RACC }, 124 {"fsl,imx7d-fec", FECTYPE_IMX6 | FECFLAG_RACC | FECFLAG_GBE | 125 FECFLAG_AVB }, 126 {"fsl,mvf600-fec", FECTYPE_MVF | FECFLAG_RACC }, 127 {"fsl,mvf-fec", FECTYPE_MVF}, 128 {NULL, FECTYPE_NONE}, 129}; 130 131/* 132 * Driver data and defines. 133 */ 134#define RX_DESC_COUNT 64 135#define RX_DESC_SIZE (sizeof(struct ffec_hwdesc) * RX_DESC_COUNT) 136#define TX_DESC_COUNT 64 137#define TX_DESC_SIZE (sizeof(struct ffec_hwdesc) * TX_DESC_COUNT) 138 139#define WATCHDOG_TIMEOUT_SECS 5 140 141#define MAX_IRQ_COUNT 3 142 143struct ffec_bufmap { 144 struct mbuf *mbuf; 145 bus_dmamap_t map; 146}; 147 148struct ffec_softc { 149 device_t dev; 150 device_t miibus; 151 struct mii_data * mii_softc; 152 struct ifnet *ifp; 153 int if_flags; 154 struct mtx mtx; 155 struct resource *irq_res[MAX_IRQ_COUNT]; 156 struct resource *mem_res; 157 void * intr_cookie[MAX_IRQ_COUNT]; 158 struct callout ffec_callout; 159 mii_contype_t phy_conn_type; 160 uint32_t fecflags; 161 uint8_t fectype; 162 boolean_t link_is_up; 163 boolean_t is_attached; 164 boolean_t is_detaching; 165 int tx_watchdog_count; 166 int rxbuf_align; 167 int txbuf_align; 168 169 bus_dma_tag_t rxdesc_tag; 170 bus_dmamap_t rxdesc_map; 171 struct ffec_hwdesc *rxdesc_ring; 172 bus_addr_t rxdesc_ring_paddr; 173 bus_dma_tag_t rxbuf_tag; 174 struct ffec_bufmap rxbuf_map[RX_DESC_COUNT]; 175 uint32_t rx_idx; 176 177 bus_dma_tag_t txdesc_tag; 178 bus_dmamap_t txdesc_map; 179 struct ffec_hwdesc *txdesc_ring; 180 bus_addr_t txdesc_ring_paddr; 181 bus_dma_tag_t txbuf_tag; 182 struct ffec_bufmap txbuf_map[TX_DESC_COUNT]; 183 uint32_t tx_idx_head; 184 uint32_t tx_idx_tail; 185 int txcount; 186}; 187 188static struct resource_spec irq_res_spec[MAX_IRQ_COUNT + 1] = { 189 { SYS_RES_IRQ, 0, RF_ACTIVE }, 190 { SYS_RES_IRQ, 1, RF_ACTIVE | RF_OPTIONAL }, 191 { SYS_RES_IRQ, 2, RF_ACTIVE | RF_OPTIONAL }, 192 RESOURCE_SPEC_END 193}; 194 195#define FFEC_LOCK(sc) mtx_lock(&(sc)->mtx) 196#define FFEC_UNLOCK(sc) mtx_unlock(&(sc)->mtx) 197#define FFEC_LOCK_INIT(sc) mtx_init(&(sc)->mtx, \ 198 device_get_nameunit((sc)->dev), MTX_NETWORK_LOCK, MTX_DEF) 199#define FFEC_LOCK_DESTROY(sc) mtx_destroy(&(sc)->mtx); 200#define FFEC_ASSERT_LOCKED(sc) mtx_assert(&(sc)->mtx, MA_OWNED); 201#define FFEC_ASSERT_UNLOCKED(sc) mtx_assert(&(sc)->mtx, MA_NOTOWNED); 202 203static void ffec_init_locked(struct ffec_softc *sc); 204static void ffec_stop_locked(struct ffec_softc *sc); 205static void ffec_txstart_locked(struct ffec_softc *sc); 206static void ffec_txfinish_locked(struct ffec_softc *sc); 207 208static inline uint16_t 209RD2(struct ffec_softc *sc, bus_size_t off) 210{ 211 212 return (bus_read_2(sc->mem_res, off)); 213} 214 215static inline void 216WR2(struct ffec_softc *sc, bus_size_t off, uint16_t val) 217{ 218 219 bus_write_2(sc->mem_res, off, val); 220} 221 222static inline uint32_t 223RD4(struct ffec_softc *sc, bus_size_t off) 224{ 225 226 return (bus_read_4(sc->mem_res, off)); 227} 228 229static inline void 230WR4(struct ffec_softc *sc, bus_size_t off, uint32_t val) 231{ 232 233 bus_write_4(sc->mem_res, off, val); 234} 235 236static inline uint32_t 237next_rxidx(struct ffec_softc *sc, uint32_t curidx) 238{ 239 240 return ((curidx == RX_DESC_COUNT - 1) ? 0 : curidx + 1); 241} 242 243static inline uint32_t 244next_txidx(struct ffec_softc *sc, uint32_t curidx) 245{ 246 247 return ((curidx == TX_DESC_COUNT - 1) ? 0 : curidx + 1); 248} 249 250static void 251ffec_get1paddr(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 252{ 253 254 if (error != 0) 255 return; 256 *(bus_addr_t *)arg = segs[0].ds_addr; 257} 258 259static void 260ffec_miigasket_setup(struct ffec_softc *sc) 261{ 262 uint32_t ifmode; 263 264 /* 265 * We only need the gasket for MII and RMII connections on certain SoCs. 266 */ 267 268 switch (sc->fectype) 269 { 270 case FECTYPE_IMX53: 271 break; 272 default: 273 return; 274 } 275 276 switch (sc->phy_conn_type) 277 { 278 case MII_CONTYPE_MII: 279 ifmode = 0; 280 break; 281 case MII_CONTYPE_RMII: 282 ifmode = FEC_MIIGSK_CFGR_IF_MODE_RMII; 283 break; 284 default: 285 return; 286 } 287 288 /* 289 * Disable the gasket, configure for either MII or RMII, then enable. 290 */ 291 292 WR2(sc, FEC_MIIGSK_ENR, 0); 293 while (RD2(sc, FEC_MIIGSK_ENR) & FEC_MIIGSK_ENR_READY) 294 continue; 295 296 WR2(sc, FEC_MIIGSK_CFGR, ifmode); 297 298 WR2(sc, FEC_MIIGSK_ENR, FEC_MIIGSK_ENR_EN); 299 while (!(RD2(sc, FEC_MIIGSK_ENR) & FEC_MIIGSK_ENR_READY)) 300 continue; 301} 302 303static boolean_t 304ffec_miibus_iowait(struct ffec_softc *sc) 305{ 306 uint32_t timeout; 307 308 for (timeout = 10000; timeout != 0; --timeout) 309 if (RD4(sc, FEC_IER_REG) & FEC_IER_MII) 310 return (true); 311 312 return (false); 313} 314 315static int 316ffec_miibus_readreg(device_t dev, int phy, int reg) 317{ 318 struct ffec_softc *sc; 319 int val; 320 321 sc = device_get_softc(dev); 322 323 WR4(sc, FEC_IER_REG, FEC_IER_MII); 324 325 WR4(sc, FEC_MMFR_REG, FEC_MMFR_OP_READ | 326 FEC_MMFR_ST_VALUE | FEC_MMFR_TA_VALUE | 327 ((phy << FEC_MMFR_PA_SHIFT) & FEC_MMFR_PA_MASK) | 328 ((reg << FEC_MMFR_RA_SHIFT) & FEC_MMFR_RA_MASK)); 329 330 if (!ffec_miibus_iowait(sc)) { 331 device_printf(dev, "timeout waiting for mii read\n"); 332 return (-1); /* All-ones is a symptom of bad mdio. */ 333 } 334 335 val = RD4(sc, FEC_MMFR_REG) & FEC_MMFR_DATA_MASK; 336 337 return (val); 338} 339 340static int 341ffec_miibus_writereg(device_t dev, int phy, int reg, int val) 342{ 343 struct ffec_softc *sc; 344 345 sc = device_get_softc(dev); 346 347 WR4(sc, FEC_IER_REG, FEC_IER_MII); 348 349 WR4(sc, FEC_MMFR_REG, FEC_MMFR_OP_WRITE | 350 FEC_MMFR_ST_VALUE | FEC_MMFR_TA_VALUE | 351 ((phy << FEC_MMFR_PA_SHIFT) & FEC_MMFR_PA_MASK) | 352 ((reg << FEC_MMFR_RA_SHIFT) & FEC_MMFR_RA_MASK) | 353 (val & FEC_MMFR_DATA_MASK)); 354 355 if (!ffec_miibus_iowait(sc)) { 356 device_printf(dev, "timeout waiting for mii write\n"); 357 return (-1); 358 } 359 360 return (0); 361} 362 363static void 364ffec_miibus_statchg(device_t dev) 365{ 366 struct ffec_softc *sc; 367 struct mii_data *mii; 368 uint32_t ecr, rcr, tcr; 369 370 /* 371 * Called by the MII bus driver when the PHY establishes link to set the 372 * MAC interface registers. 373 */ 374 375 sc = device_get_softc(dev); 376 377 FFEC_ASSERT_LOCKED(sc); 378 379 mii = sc->mii_softc; 380 381 if (mii->mii_media_status & IFM_ACTIVE) 382 sc->link_is_up = true; 383 else 384 sc->link_is_up = false; 385 386 ecr = RD4(sc, FEC_ECR_REG) & ~FEC_ECR_SPEED; 387 rcr = RD4(sc, FEC_RCR_REG) & ~(FEC_RCR_RMII_10T | FEC_RCR_RMII_MODE | 388 FEC_RCR_RGMII_EN | FEC_RCR_DRT | FEC_RCR_FCE); 389 tcr = RD4(sc, FEC_TCR_REG) & ~FEC_TCR_FDEN; 390 391 rcr |= FEC_RCR_MII_MODE; /* Must always be on even for R[G]MII. */ 392 switch (sc->phy_conn_type) { 393 case MII_CONTYPE_RMII: 394 rcr |= FEC_RCR_RMII_MODE; 395 break; 396 case MII_CONTYPE_RGMII: 397 case MII_CONTYPE_RGMII_ID: 398 case MII_CONTYPE_RGMII_RXID: 399 case MII_CONTYPE_RGMII_TXID: 400 rcr |= FEC_RCR_RGMII_EN; 401 break; 402 default: 403 break; 404 } 405 406 switch (IFM_SUBTYPE(mii->mii_media_active)) { 407 case IFM_1000_T: 408 case IFM_1000_SX: 409 ecr |= FEC_ECR_SPEED; 410 break; 411 case IFM_100_TX: 412 /* Not-FEC_ECR_SPEED + not-FEC_RCR_RMII_10T means 100TX */ 413 break; 414 case IFM_10_T: 415 rcr |= FEC_RCR_RMII_10T; 416 break; 417 case IFM_NONE: 418 sc->link_is_up = false; 419 return; 420 default: 421 sc->link_is_up = false; 422 device_printf(dev, "Unsupported media %u\n", 423 IFM_SUBTYPE(mii->mii_media_active)); 424 return; 425 } 426 427 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) 428 tcr |= FEC_TCR_FDEN; 429 else 430 rcr |= FEC_RCR_DRT; 431 432 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FLOW) != 0) 433 rcr |= FEC_RCR_FCE; 434 435 WR4(sc, FEC_RCR_REG, rcr); 436 WR4(sc, FEC_TCR_REG, tcr); 437 WR4(sc, FEC_ECR_REG, ecr); 438} 439 440static void 441ffec_media_status(struct ifnet * ifp, struct ifmediareq *ifmr) 442{ 443 struct ffec_softc *sc; 444 struct mii_data *mii; 445 446 447 sc = ifp->if_softc; 448 mii = sc->mii_softc; 449 FFEC_LOCK(sc); 450 mii_pollstat(mii); 451 ifmr->ifm_active = mii->mii_media_active; 452 ifmr->ifm_status = mii->mii_media_status; 453 FFEC_UNLOCK(sc); 454} 455 456static int 457ffec_media_change_locked(struct ffec_softc *sc) 458{ 459 460 return (mii_mediachg(sc->mii_softc)); 461} 462 463static int 464ffec_media_change(struct ifnet * ifp) 465{ 466 struct ffec_softc *sc; 467 int error; 468 469 sc = ifp->if_softc; 470 471 FFEC_LOCK(sc); 472 error = ffec_media_change_locked(sc); 473 FFEC_UNLOCK(sc); 474 return (error); 475} 476 477static void ffec_clear_stats(struct ffec_softc *sc) 478{ 479 uint32_t mibc; 480 481 mibc = RD4(sc, FEC_MIBC_REG); 482 483 /* 484 * On newer hardware the statistic regs are cleared by toggling a bit in 485 * the mib control register. On older hardware the clear procedure is 486 * to disable statistics collection, zero the regs, then re-enable. 487 */ 488 if (sc->fectype == FECTYPE_IMX6 || sc->fectype == FECTYPE_MVF) { 489 WR4(sc, FEC_MIBC_REG, mibc | FEC_MIBC_CLEAR); 490 WR4(sc, FEC_MIBC_REG, mibc & ~FEC_MIBC_CLEAR); 491 } else { 492 WR4(sc, FEC_MIBC_REG, mibc | FEC_MIBC_DIS); 493 494 WR4(sc, FEC_IEEE_R_DROP, 0); 495 WR4(sc, FEC_IEEE_R_MACERR, 0); 496 WR4(sc, FEC_RMON_R_CRC_ALIGN, 0); 497 WR4(sc, FEC_RMON_R_FRAG, 0); 498 WR4(sc, FEC_RMON_R_JAB, 0); 499 WR4(sc, FEC_RMON_R_MC_PKT, 0); 500 WR4(sc, FEC_RMON_R_OVERSIZE, 0); 501 WR4(sc, FEC_RMON_R_PACKETS, 0); 502 WR4(sc, FEC_RMON_R_UNDERSIZE, 0); 503 WR4(sc, FEC_RMON_T_COL, 0); 504 WR4(sc, FEC_RMON_T_CRC_ALIGN, 0); 505 WR4(sc, FEC_RMON_T_FRAG, 0); 506 WR4(sc, FEC_RMON_T_JAB, 0); 507 WR4(sc, FEC_RMON_T_MC_PKT, 0); 508 WR4(sc, FEC_RMON_T_OVERSIZE , 0); 509 WR4(sc, FEC_RMON_T_PACKETS, 0); 510 WR4(sc, FEC_RMON_T_UNDERSIZE, 0); 511 512 WR4(sc, FEC_MIBC_REG, mibc); 513 } 514} 515 516static void 517ffec_harvest_stats(struct ffec_softc *sc) 518{ 519 struct ifnet *ifp; 520 521 ifp = sc->ifp; 522 523 /* 524 * - FEC_IEEE_R_DROP is "dropped due to invalid start frame delimiter" 525 * so it's really just another type of input error. 526 * - FEC_IEEE_R_MACERR is "no receive fifo space"; count as input drops. 527 */ 528 if_inc_counter(ifp, IFCOUNTER_IPACKETS, RD4(sc, FEC_RMON_R_PACKETS)); 529 if_inc_counter(ifp, IFCOUNTER_IMCASTS, RD4(sc, FEC_RMON_R_MC_PKT)); 530 if_inc_counter(ifp, IFCOUNTER_IERRORS, 531 RD4(sc, FEC_RMON_R_CRC_ALIGN) + RD4(sc, FEC_RMON_R_UNDERSIZE) + 532 RD4(sc, FEC_RMON_R_OVERSIZE) + RD4(sc, FEC_RMON_R_FRAG) + 533 RD4(sc, FEC_RMON_R_JAB) + RD4(sc, FEC_IEEE_R_DROP)); 534 535 if_inc_counter(ifp, IFCOUNTER_IQDROPS, RD4(sc, FEC_IEEE_R_MACERR)); 536 537 if_inc_counter(ifp, IFCOUNTER_OPACKETS, RD4(sc, FEC_RMON_T_PACKETS)); 538 if_inc_counter(ifp, IFCOUNTER_OMCASTS, RD4(sc, FEC_RMON_T_MC_PKT)); 539 if_inc_counter(ifp, IFCOUNTER_OERRORS, 540 RD4(sc, FEC_RMON_T_CRC_ALIGN) + RD4(sc, FEC_RMON_T_UNDERSIZE) + 541 RD4(sc, FEC_RMON_T_OVERSIZE) + RD4(sc, FEC_RMON_T_FRAG) + 542 RD4(sc, FEC_RMON_T_JAB)); 543 544 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, RD4(sc, FEC_RMON_T_COL)); 545 546 ffec_clear_stats(sc); 547} 548 549static void 550ffec_tick(void *arg) 551{ 552 struct ffec_softc *sc; 553 struct ifnet *ifp; 554 int link_was_up; 555 556 sc = arg; 557 558 FFEC_ASSERT_LOCKED(sc); 559 560 ifp = sc->ifp; 561 562 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) 563 return; 564 565 /* 566 * Typical tx watchdog. If this fires it indicates that we enqueued 567 * packets for output and never got a txdone interrupt for them. Maybe 568 * it's a missed interrupt somehow, just pretend we got one. 569 */ 570 if (sc->tx_watchdog_count > 0) { 571 if (--sc->tx_watchdog_count == 0) { 572 ffec_txfinish_locked(sc); 573 } 574 } 575 576 /* Gather stats from hardware counters. */ 577 ffec_harvest_stats(sc); 578 579 /* Check the media status. */ 580 link_was_up = sc->link_is_up; 581 mii_tick(sc->mii_softc); 582 if (sc->link_is_up && !link_was_up) 583 ffec_txstart_locked(sc); 584 585 /* Schedule another check one second from now. */ 586 callout_reset(&sc->ffec_callout, hz, ffec_tick, sc); 587} 588 589inline static uint32_t 590ffec_setup_txdesc(struct ffec_softc *sc, int idx, bus_addr_t paddr, 591 uint32_t len) 592{ 593 uint32_t nidx; 594 uint32_t flags; 595 596 nidx = next_txidx(sc, idx); 597 598 /* Addr/len 0 means we're clearing the descriptor after xmit done. */ 599 if (paddr == 0 || len == 0) { 600 flags = 0; 601 --sc->txcount; 602 } else { 603 flags = FEC_TXDESC_READY | FEC_TXDESC_L | FEC_TXDESC_TC; 604 ++sc->txcount; 605 } 606 if (nidx == 0) 607 flags |= FEC_TXDESC_WRAP; 608 609 /* 610 * The hardware requires 32-bit physical addresses. We set up the dma 611 * tag to indicate that, so the cast to uint32_t should never lose 612 * significant bits. 613 */ 614 sc->txdesc_ring[idx].buf_paddr = (uint32_t)paddr; 615 sc->txdesc_ring[idx].flags_len = flags | len; /* Must be set last! */ 616 617 return (nidx); 618} 619 620static int 621ffec_setup_txbuf(struct ffec_softc *sc, int idx, struct mbuf **mp) 622{ 623 struct mbuf * m; 624 int error, nsegs; 625 struct bus_dma_segment seg; 626 627 if ((m = m_defrag(*mp, M_NOWAIT)) == NULL) 628 return (ENOMEM); 629 *mp = m; 630 631 error = bus_dmamap_load_mbuf_sg(sc->txbuf_tag, sc->txbuf_map[idx].map, 632 m, &seg, &nsegs, 0); 633 if (error != 0) { 634 return (ENOMEM); 635 } 636 bus_dmamap_sync(sc->txbuf_tag, sc->txbuf_map[idx].map, 637 BUS_DMASYNC_PREWRITE); 638 639 sc->txbuf_map[idx].mbuf = m; 640 ffec_setup_txdesc(sc, idx, seg.ds_addr, seg.ds_len); 641 642 return (0); 643 644} 645 646static void 647ffec_txstart_locked(struct ffec_softc *sc) 648{ 649 struct ifnet *ifp; 650 struct mbuf *m; 651 int enqueued; 652 653 FFEC_ASSERT_LOCKED(sc); 654 655 if (!sc->link_is_up) 656 return; 657 658 ifp = sc->ifp; 659 660 if (ifp->if_drv_flags & IFF_DRV_OACTIVE) 661 return; 662 663 enqueued = 0; 664 665 for (;;) { 666 if (sc->txcount == (TX_DESC_COUNT-1)) { 667 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 668 break; 669 } 670 IFQ_DRV_DEQUEUE(&ifp->if_snd, m); 671 if (m == NULL) 672 break; 673 if (ffec_setup_txbuf(sc, sc->tx_idx_head, &m) != 0) { 674 IFQ_DRV_PREPEND(&ifp->if_snd, m); 675 break; 676 } 677 BPF_MTAP(ifp, m); 678 sc->tx_idx_head = next_txidx(sc, sc->tx_idx_head); 679 ++enqueued; 680 } 681 682 if (enqueued != 0) { 683 bus_dmamap_sync(sc->txdesc_tag, sc->txdesc_map, BUS_DMASYNC_PREWRITE); 684 WR4(sc, FEC_TDAR_REG, FEC_TDAR_TDAR); 685 bus_dmamap_sync(sc->txdesc_tag, sc->txdesc_map, BUS_DMASYNC_POSTWRITE); 686 sc->tx_watchdog_count = WATCHDOG_TIMEOUT_SECS; 687 } 688} 689 690static void 691ffec_txstart(struct ifnet *ifp) 692{ 693 struct ffec_softc *sc = ifp->if_softc; 694 695 FFEC_LOCK(sc); 696 ffec_txstart_locked(sc); 697 FFEC_UNLOCK(sc); 698} 699 700static void 701ffec_txfinish_locked(struct ffec_softc *sc) 702{ 703 struct ifnet *ifp; 704 struct ffec_hwdesc *desc; 705 struct ffec_bufmap *bmap; 706 boolean_t retired_buffer; 707 708 FFEC_ASSERT_LOCKED(sc); 709 710 /* XXX Can't set PRE|POST right now, but we need both. */ 711 bus_dmamap_sync(sc->txdesc_tag, sc->txdesc_map, BUS_DMASYNC_PREREAD); 712 bus_dmamap_sync(sc->txdesc_tag, sc->txdesc_map, BUS_DMASYNC_POSTREAD); 713 ifp = sc->ifp; 714 retired_buffer = false; 715 while (sc->tx_idx_tail != sc->tx_idx_head) { 716 desc = &sc->txdesc_ring[sc->tx_idx_tail]; 717 if (desc->flags_len & FEC_TXDESC_READY) 718 break; 719 retired_buffer = true; 720 bmap = &sc->txbuf_map[sc->tx_idx_tail]; 721 bus_dmamap_sync(sc->txbuf_tag, bmap->map, 722 BUS_DMASYNC_POSTWRITE); 723 bus_dmamap_unload(sc->txbuf_tag, bmap->map); 724 m_freem(bmap->mbuf); 725 bmap->mbuf = NULL; 726 ffec_setup_txdesc(sc, sc->tx_idx_tail, 0, 0); 727 sc->tx_idx_tail = next_txidx(sc, sc->tx_idx_tail); 728 } 729 730 /* 731 * If we retired any buffers, there will be open tx slots available in 732 * the descriptor ring, go try to start some new output. 733 */ 734 if (retired_buffer) { 735 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 736 ffec_txstart_locked(sc); 737 } 738 739 /* If there are no buffers outstanding, muzzle the watchdog. */ 740 if (sc->tx_idx_tail == sc->tx_idx_head) { 741 sc->tx_watchdog_count = 0; 742 } 743} 744 745inline static uint32_t 746ffec_setup_rxdesc(struct ffec_softc *sc, int idx, bus_addr_t paddr) 747{ 748 uint32_t nidx; 749 750 /* 751 * The hardware requires 32-bit physical addresses. We set up the dma 752 * tag to indicate that, so the cast to uint32_t should never lose 753 * significant bits. 754 */ 755 nidx = next_rxidx(sc, idx); 756 sc->rxdesc_ring[idx].buf_paddr = (uint32_t)paddr; 757 sc->rxdesc_ring[idx].flags_len = FEC_RXDESC_EMPTY | 758 ((nidx == 0) ? FEC_RXDESC_WRAP : 0); 759 760 return (nidx); 761} 762 763static int 764ffec_setup_rxbuf(struct ffec_softc *sc, int idx, struct mbuf * m) 765{ 766 int error, nsegs; 767 struct bus_dma_segment seg; 768 769 if (!(sc->fecflags & FECFLAG_RACC)) { 770 /* 771 * The RACC[SHIFT16] feature is not available. So, we need to 772 * leave at least ETHER_ALIGN bytes free at the beginning of the 773 * buffer to allow the data to be re-aligned after receiving it 774 * (by copying it backwards ETHER_ALIGN bytes in the same 775 * buffer). We also have to ensure that the beginning of the 776 * buffer is aligned to the hardware's requirements. 777 */ 778 m_adj(m, roundup(ETHER_ALIGN, sc->rxbuf_align)); 779 } 780 781 error = bus_dmamap_load_mbuf_sg(sc->rxbuf_tag, sc->rxbuf_map[idx].map, 782 m, &seg, &nsegs, 0); 783 if (error != 0) { 784 return (error); 785 } 786 787 bus_dmamap_sync(sc->rxbuf_tag, sc->rxbuf_map[idx].map, 788 BUS_DMASYNC_PREREAD); 789 790 sc->rxbuf_map[idx].mbuf = m; 791 ffec_setup_rxdesc(sc, idx, seg.ds_addr); 792 793 return (0); 794} 795 796static struct mbuf * 797ffec_alloc_mbufcl(struct ffec_softc *sc) 798{ 799 struct mbuf *m; 800 801 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 802 if (m != NULL) 803 m->m_pkthdr.len = m->m_len = m->m_ext.ext_size; 804 805 return (m); 806} 807 808static void 809ffec_rxfinish_onebuf(struct ffec_softc *sc, int len) 810{ 811 struct mbuf *m, *newmbuf; 812 struct ffec_bufmap *bmap; 813 uint8_t *dst, *src; 814 int error; 815 816 /* 817 * First try to get a new mbuf to plug into this slot in the rx ring. 818 * If that fails, drop the current packet and recycle the current 819 * mbuf, which is still mapped and loaded. 820 */ 821 if ((newmbuf = ffec_alloc_mbufcl(sc)) == NULL) { 822 if_inc_counter(sc->ifp, IFCOUNTER_IQDROPS, 1); 823 ffec_setup_rxdesc(sc, sc->rx_idx, 824 sc->rxdesc_ring[sc->rx_idx].buf_paddr); 825 return; 826 } 827 828 FFEC_UNLOCK(sc); 829 830 bmap = &sc->rxbuf_map[sc->rx_idx]; 831 len -= ETHER_CRC_LEN; 832 bus_dmamap_sync(sc->rxbuf_tag, bmap->map, BUS_DMASYNC_POSTREAD); 833 bus_dmamap_unload(sc->rxbuf_tag, bmap->map); 834 m = bmap->mbuf; 835 bmap->mbuf = NULL; 836 m->m_len = len; 837 m->m_pkthdr.len = len; 838 m->m_pkthdr.rcvif = sc->ifp; 839 840 /* 841 * Align the protocol headers in the receive buffer on a 32-bit 842 * boundary. Newer hardware does the alignment for us. On hardware 843 * that doesn't support this feature, we have to copy-align the data. 844 * 845 * XXX for older hardware, could we speed this up by copying just the 846 * protocol headers into their own small mbuf then chaining the cluster 847 * to it? That way we'd only need to copy like 64 bytes or whatever the 848 * biggest header is, instead of the whole 1530ish-byte frame. 849 */ 850 if (sc->fecflags & FECFLAG_RACC) { 851 m->m_data = mtod(m, uint8_t *) + 2; 852 } else { 853 src = mtod(m, uint8_t*); 854 dst = src - ETHER_ALIGN; 855 bcopy(src, dst, len); 856 m->m_data = dst; 857 } 858 sc->ifp->if_input(sc->ifp, m); 859 860 FFEC_LOCK(sc); 861 862 if ((error = ffec_setup_rxbuf(sc, sc->rx_idx, newmbuf)) != 0) { 863 device_printf(sc->dev, "ffec_setup_rxbuf error %d\n", error); 864 /* XXX Now what? We've got a hole in the rx ring. */ 865 } 866 867} 868 869static void 870ffec_rxfinish_locked(struct ffec_softc *sc) 871{ 872 struct ffec_hwdesc *desc; 873 int len; 874 boolean_t produced_empty_buffer; 875 876 FFEC_ASSERT_LOCKED(sc); 877 878 /* XXX Can't set PRE|POST right now, but we need both. */ 879 bus_dmamap_sync(sc->rxdesc_tag, sc->rxdesc_map, BUS_DMASYNC_PREREAD); 880 bus_dmamap_sync(sc->rxdesc_tag, sc->rxdesc_map, BUS_DMASYNC_POSTREAD); 881 produced_empty_buffer = false; 882 for (;;) { 883 desc = &sc->rxdesc_ring[sc->rx_idx]; 884 if (desc->flags_len & FEC_RXDESC_EMPTY) 885 break; 886 produced_empty_buffer = true; 887 len = (desc->flags_len & FEC_RXDESC_LEN_MASK); 888 if (len < 64) { 889 /* 890 * Just recycle the descriptor and continue. . 891 */ 892 ffec_setup_rxdesc(sc, sc->rx_idx, 893 sc->rxdesc_ring[sc->rx_idx].buf_paddr); 894 } else if ((desc->flags_len & FEC_RXDESC_L) == 0) { 895 /* 896 * The entire frame is not in this buffer. Impossible. 897 * Recycle the descriptor and continue. 898 * 899 * XXX what's the right way to handle this? Probably we 900 * should stop/init the hardware because this should 901 * just really never happen when we have buffers bigger 902 * than the maximum frame size. 903 */ 904 device_printf(sc->dev, 905 "fec_rxfinish: received frame without LAST bit set"); 906 ffec_setup_rxdesc(sc, sc->rx_idx, 907 sc->rxdesc_ring[sc->rx_idx].buf_paddr); 908 } else if (desc->flags_len & FEC_RXDESC_ERROR_BITS) { 909 /* 910 * Something went wrong with receiving the frame, we 911 * don't care what (the hardware has counted the error 912 * in the stats registers already), we just reuse the 913 * same mbuf, which is still dma-mapped, by resetting 914 * the rx descriptor. 915 */ 916 ffec_setup_rxdesc(sc, sc->rx_idx, 917 sc->rxdesc_ring[sc->rx_idx].buf_paddr); 918 } else { 919 /* 920 * Normal case: a good frame all in one buffer. 921 */ 922 ffec_rxfinish_onebuf(sc, len); 923 } 924 sc->rx_idx = next_rxidx(sc, sc->rx_idx); 925 } 926 927 if (produced_empty_buffer) { 928 bus_dmamap_sync(sc->rxdesc_tag, sc->rxdesc_map, BUS_DMASYNC_PREWRITE); 929 WR4(sc, FEC_RDAR_REG, FEC_RDAR_RDAR); 930 bus_dmamap_sync(sc->rxdesc_tag, sc->rxdesc_map, BUS_DMASYNC_POSTWRITE); 931 } 932} 933 934static void 935ffec_get_hwaddr(struct ffec_softc *sc, uint8_t *hwaddr) 936{ 937 uint32_t palr, paur, rnd; 938 939 /* 940 * Try to recover a MAC address from the running hardware. If there's 941 * something non-zero there, assume the bootloader did the right thing 942 * and just use it. 943 * 944 * Otherwise, set the address to a convenient locally assigned address, 945 * 'bsd' + random 24 low-order bits. 'b' is 0x62, which has the locally 946 * assigned bit set, and the broadcast/multicast bit clear. 947 */ 948 palr = RD4(sc, FEC_PALR_REG); 949 paur = RD4(sc, FEC_PAUR_REG) & FEC_PAUR_PADDR2_MASK; 950 if ((palr | paur) != 0) { 951 hwaddr[0] = palr >> 24; 952 hwaddr[1] = palr >> 16; 953 hwaddr[2] = palr >> 8; 954 hwaddr[3] = palr >> 0; 955 hwaddr[4] = paur >> 24; 956 hwaddr[5] = paur >> 16; 957 } else { 958 rnd = arc4random() & 0x00ffffff; 959 hwaddr[0] = 'b'; 960 hwaddr[1] = 's'; 961 hwaddr[2] = 'd'; 962 hwaddr[3] = rnd >> 16; 963 hwaddr[4] = rnd >> 8; 964 hwaddr[5] = rnd >> 0; 965 } 966 967 if (bootverbose) { 968 device_printf(sc->dev, 969 "MAC address %02x:%02x:%02x:%02x:%02x:%02x:\n", 970 hwaddr[0], hwaddr[1], hwaddr[2], 971 hwaddr[3], hwaddr[4], hwaddr[5]); 972 } 973} 974 975static void 976ffec_setup_rxfilter(struct ffec_softc *sc) 977{ 978 struct ifnet *ifp; 979 struct ifmultiaddr *ifma; 980 uint8_t *eaddr; 981 uint32_t crc; 982 uint64_t ghash, ihash; 983 984 FFEC_ASSERT_LOCKED(sc); 985 986 ifp = sc->ifp; 987 988 /* 989 * Set the multicast (group) filter hash. 990 */ 991 if ((ifp->if_flags & IFF_ALLMULTI)) 992 ghash = 0xffffffffffffffffLLU; 993 else { 994 ghash = 0; 995 if_maddr_rlock(ifp); 996 TAILQ_FOREACH(ifma, &sc->ifp->if_multiaddrs, ifma_link) { 997 if (ifma->ifma_addr->sa_family != AF_LINK) 998 continue; 999 /* 6 bits from MSB in LE CRC32 are used for hash. */ 1000 crc = ether_crc32_le(LLADDR((struct sockaddr_dl *) 1001 ifma->ifma_addr), ETHER_ADDR_LEN); 1002 ghash |= 1LLU << (((uint8_t *)&crc)[3] >> 2); 1003 } 1004 if_maddr_runlock(ifp); 1005 } 1006 WR4(sc, FEC_GAUR_REG, (uint32_t)(ghash >> 32)); 1007 WR4(sc, FEC_GALR_REG, (uint32_t)ghash); 1008 1009 /* 1010 * Set the individual address filter hash. 1011 * 1012 * XXX Is 0 the right value when promiscuous is off? This hw feature 1013 * seems to support the concept of MAC address aliases, does such a 1014 * thing even exist? 1015 */ 1016 if ((ifp->if_flags & IFF_PROMISC)) 1017 ihash = 0xffffffffffffffffLLU; 1018 else { 1019 ihash = 0; 1020 } 1021 WR4(sc, FEC_IAUR_REG, (uint32_t)(ihash >> 32)); 1022 WR4(sc, FEC_IALR_REG, (uint32_t)ihash); 1023 1024 /* 1025 * Set the primary address. 1026 */ 1027 eaddr = IF_LLADDR(ifp); 1028 WR4(sc, FEC_PALR_REG, (eaddr[0] << 24) | (eaddr[1] << 16) | 1029 (eaddr[2] << 8) | eaddr[3]); 1030 WR4(sc, FEC_PAUR_REG, (eaddr[4] << 24) | (eaddr[5] << 16)); 1031} 1032 1033static void 1034ffec_stop_locked(struct ffec_softc *sc) 1035{ 1036 struct ifnet *ifp; 1037 struct ffec_hwdesc *desc; 1038 struct ffec_bufmap *bmap; 1039 int idx; 1040 1041 FFEC_ASSERT_LOCKED(sc); 1042 1043 ifp = sc->ifp; 1044 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 1045 sc->tx_watchdog_count = 0; 1046 1047 /* 1048 * Stop the hardware, mask all interrupts, and clear all current 1049 * interrupt status bits. 1050 */ 1051 WR4(sc, FEC_ECR_REG, RD4(sc, FEC_ECR_REG) & ~FEC_ECR_ETHEREN); 1052 WR4(sc, FEC_IEM_REG, 0x00000000); 1053 WR4(sc, FEC_IER_REG, 0xffffffff); 1054 1055 /* 1056 * Stop the media-check callout. Do not use callout_drain() because 1057 * we're holding a mutex the callout acquires, and if it's currently 1058 * waiting to acquire it, we'd deadlock. If it is waiting now, the 1059 * ffec_tick() routine will return without doing anything when it sees 1060 * that IFF_DRV_RUNNING is not set, so avoiding callout_drain() is safe. 1061 */ 1062 callout_stop(&sc->ffec_callout); 1063 1064 /* 1065 * Discard all untransmitted buffers. Each buffer is simply freed; 1066 * it's as if the bits were transmitted and then lost on the wire. 1067 * 1068 * XXX Is this right? Or should we use IFQ_DRV_PREPEND() to put them 1069 * back on the queue for when we get restarted later? 1070 */ 1071 idx = sc->tx_idx_tail; 1072 while (idx != sc->tx_idx_head) { 1073 desc = &sc->txdesc_ring[idx]; 1074 bmap = &sc->txbuf_map[idx]; 1075 if (desc->buf_paddr != 0) { 1076 bus_dmamap_unload(sc->txbuf_tag, bmap->map); 1077 m_freem(bmap->mbuf); 1078 bmap->mbuf = NULL; 1079 ffec_setup_txdesc(sc, idx, 0, 0); 1080 } 1081 idx = next_txidx(sc, idx); 1082 } 1083 1084 /* 1085 * Discard all unprocessed receive buffers. This amounts to just 1086 * pretending that nothing ever got received into them. We reuse the 1087 * mbuf already mapped for each desc, simply turning the EMPTY flags 1088 * back on so they'll get reused when we start up again. 1089 */ 1090 for (idx = 0; idx < RX_DESC_COUNT; ++idx) { 1091 desc = &sc->rxdesc_ring[idx]; 1092 ffec_setup_rxdesc(sc, idx, desc->buf_paddr); 1093 } 1094} 1095 1096static void 1097ffec_init_locked(struct ffec_softc *sc) 1098{ 1099 struct ifnet *ifp = sc->ifp; 1100 uint32_t maxbuf, maxfl, regval; 1101 1102 FFEC_ASSERT_LOCKED(sc); 1103 1104 /* 1105 * The hardware has a limit of 0x7ff as the max frame length (see 1106 * comments for MRBR below), and we use mbuf clusters as receive 1107 * buffers, and we currently are designed to receive an entire frame 1108 * into a single buffer. 1109 * 1110 * We start with a MCLBYTES-sized cluster, but we have to offset into 1111 * the buffer by ETHER_ALIGN to make room for post-receive re-alignment, 1112 * and then that value has to be rounded up to the hardware's DMA 1113 * alignment requirements, so all in all our buffer is that much smaller 1114 * than MCLBYTES. 1115 * 1116 * The resulting value is used as the frame truncation length and the 1117 * max buffer receive buffer size for now. It'll become more complex 1118 * when we support jumbo frames and receiving fragments of them into 1119 * separate buffers. 1120 */ 1121 maxbuf = MCLBYTES - roundup(ETHER_ALIGN, sc->rxbuf_align); 1122 maxfl = min(maxbuf, 0x7ff); 1123 1124 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1125 return; 1126 1127 /* Mask all interrupts and clear all current interrupt status bits. */ 1128 WR4(sc, FEC_IEM_REG, 0x00000000); 1129 WR4(sc, FEC_IER_REG, 0xffffffff); 1130 1131 /* 1132 * Go set up palr/puar, galr/gaur, ialr/iaur. 1133 */ 1134 ffec_setup_rxfilter(sc); 1135 1136 /* 1137 * TFWR - Transmit FIFO watermark register. 1138 * 1139 * Set the transmit fifo watermark register to "store and forward" mode 1140 * and also set a threshold of 128 bytes in the fifo before transmission 1141 * of a frame begins (to avoid dma underruns). Recent FEC hardware 1142 * supports STRFWD and when that bit is set, the watermark level in the 1143 * low bits is ignored. Older hardware doesn't have STRFWD, but writing 1144 * to that bit is innocuous, and the TWFR bits get used instead. 1145 */ 1146 WR4(sc, FEC_TFWR_REG, FEC_TFWR_STRFWD | FEC_TFWR_TWFR_128BYTE); 1147 1148 /* RCR - Receive control register. 1149 * 1150 * Set max frame length + clean out anything left from u-boot. 1151 */ 1152 WR4(sc, FEC_RCR_REG, (maxfl << FEC_RCR_MAX_FL_SHIFT)); 1153 1154 /* 1155 * TCR - Transmit control register. 1156 * 1157 * Clean out anything left from u-boot. Any necessary values are set in 1158 * ffec_miibus_statchg() based on the media type. 1159 */ 1160 WR4(sc, FEC_TCR_REG, 0); 1161 1162 /* 1163 * OPD - Opcode/pause duration. 1164 * 1165 * XXX These magic numbers come from u-boot. 1166 */ 1167 WR4(sc, FEC_OPD_REG, 0x00010020); 1168 1169 /* 1170 * FRSR - Fifo receive start register. 1171 * 1172 * This register does not exist on imx6, it is present on earlier 1173 * hardware. The u-boot code sets this to a non-default value that's 32 1174 * bytes larger than the default, with no clue as to why. The default 1175 * value should work fine, so there's no code to init it here. 1176 */ 1177 1178 /* 1179 * MRBR - Max RX buffer size. 1180 * 1181 * Note: For hardware prior to imx6 this value cannot exceed 0x07ff, 1182 * but the datasheet says no such thing for imx6. On the imx6, setting 1183 * this to 2K without setting EN1588 resulted in a crazy runaway 1184 * receive loop in the hardware, where every rx descriptor in the ring 1185 * had its EMPTY flag cleared, no completion or error flags set, and a 1186 * length of zero. I think maybe you can only exceed it when EN1588 is 1187 * set, like maybe that's what enables jumbo frames, because in general 1188 * the EN1588 flag seems to be the "enable new stuff" vs. "be legacy- 1189 * compatible" flag. 1190 */ 1191 WR4(sc, FEC_MRBR_REG, maxfl << FEC_MRBR_R_BUF_SIZE_SHIFT); 1192 1193 /* 1194 * FTRL - Frame truncation length. 1195 * 1196 * Must be greater than or equal to the value set in FEC_RCR_MAXFL. 1197 */ 1198 WR4(sc, FEC_FTRL_REG, maxfl); 1199 1200 /* 1201 * RDSR / TDSR descriptor ring pointers. 1202 * 1203 * When we turn on ECR_ETHEREN at the end, the hardware zeroes its 1204 * internal current descriptor index values for both rings, so we zero 1205 * our index values as well. 1206 */ 1207 sc->rx_idx = 0; 1208 sc->tx_idx_head = sc->tx_idx_tail = 0; 1209 sc->txcount = 0; 1210 WR4(sc, FEC_RDSR_REG, sc->rxdesc_ring_paddr); 1211 WR4(sc, FEC_TDSR_REG, sc->txdesc_ring_paddr); 1212 1213 /* 1214 * EIM - interrupt mask register. 1215 * 1216 * We always enable the same set of interrupts while running; unlike 1217 * some drivers there's no need to change the mask on the fly depending 1218 * on what operations are in progress. 1219 */ 1220 WR4(sc, FEC_IEM_REG, FEC_IER_TXF | FEC_IER_RXF | FEC_IER_EBERR); 1221 1222 /* 1223 * MIBC - MIB control (hardware stats); clear all statistics regs, then 1224 * enable collection of statistics. 1225 */ 1226 regval = RD4(sc, FEC_MIBC_REG); 1227 WR4(sc, FEC_MIBC_REG, regval | FEC_MIBC_DIS); 1228 ffec_clear_stats(sc); 1229 WR4(sc, FEC_MIBC_REG, regval & ~FEC_MIBC_DIS); 1230 1231 if (sc->fecflags & FECFLAG_RACC) { 1232 /* 1233 * RACC - Receive Accelerator Function Configuration. 1234 */ 1235 regval = RD4(sc, FEC_RACC_REG); 1236 WR4(sc, FEC_RACC_REG, regval | FEC_RACC_SHIFT16); 1237 } 1238 1239 /* 1240 * ECR - Ethernet control register. 1241 * 1242 * This must happen after all the other config registers are set. If 1243 * we're running on little-endian hardware, also set the flag for byte- 1244 * swapping descriptor ring entries. This flag doesn't exist on older 1245 * hardware, but it can be safely set -- the bit position it occupies 1246 * was unused. 1247 */ 1248 regval = RD4(sc, FEC_ECR_REG); 1249#if _BYTE_ORDER == _LITTLE_ENDIAN 1250 regval |= FEC_ECR_DBSWP; 1251#endif 1252 regval |= FEC_ECR_ETHEREN; 1253 WR4(sc, FEC_ECR_REG, regval); 1254 1255 ifp->if_drv_flags |= IFF_DRV_RUNNING; 1256 1257 /* 1258 * Call mii_mediachg() which will call back into ffec_miibus_statchg() to 1259 * set up the remaining config registers based on the current media. 1260 */ 1261 mii_mediachg(sc->mii_softc); 1262 callout_reset(&sc->ffec_callout, hz, ffec_tick, sc); 1263 1264 /* 1265 * Tell the hardware that receive buffers are available. They were made 1266 * available in ffec_attach() or ffec_stop(). 1267 */ 1268 WR4(sc, FEC_RDAR_REG, FEC_RDAR_RDAR); 1269} 1270 1271static void 1272ffec_init(void *if_softc) 1273{ 1274 struct ffec_softc *sc = if_softc; 1275 1276 FFEC_LOCK(sc); 1277 ffec_init_locked(sc); 1278 FFEC_UNLOCK(sc); 1279} 1280 1281static void 1282ffec_intr(void *arg) 1283{ 1284 struct ffec_softc *sc; 1285 uint32_t ier; 1286 1287 sc = arg; 1288 1289 FFEC_LOCK(sc); 1290 1291 ier = RD4(sc, FEC_IER_REG); 1292 1293 if (ier & FEC_IER_TXF) { 1294 WR4(sc, FEC_IER_REG, FEC_IER_TXF); 1295 ffec_txfinish_locked(sc); 1296 } 1297 1298 if (ier & FEC_IER_RXF) { 1299 WR4(sc, FEC_IER_REG, FEC_IER_RXF); 1300 ffec_rxfinish_locked(sc); 1301 } 1302 1303 /* 1304 * We actually don't care about most errors, because the hardware copes 1305 * with them just fine, discarding the incoming bad frame, or forcing a 1306 * bad CRC onto an outgoing bad frame, and counting the errors in the 1307 * stats registers. The one that really matters is EBERR (DMA bus 1308 * error) because the hardware automatically clears ECR[ETHEREN] and we 1309 * have to restart it here. It should never happen. 1310 */ 1311 if (ier & FEC_IER_EBERR) { 1312 WR4(sc, FEC_IER_REG, FEC_IER_EBERR); 1313 device_printf(sc->dev, 1314 "Ethernet DMA error, restarting controller.\n"); 1315 ffec_stop_locked(sc); 1316 ffec_init_locked(sc); 1317 } 1318 1319 FFEC_UNLOCK(sc); 1320 1321} 1322 1323static int 1324ffec_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1325{ 1326 struct ffec_softc *sc; 1327 struct mii_data *mii; 1328 struct ifreq *ifr; 1329 int mask, error; 1330 1331 sc = ifp->if_softc; 1332 ifr = (struct ifreq *)data; 1333 1334 error = 0; 1335 switch (cmd) { 1336 case SIOCSIFFLAGS: 1337 FFEC_LOCK(sc); 1338 if (ifp->if_flags & IFF_UP) { 1339 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 1340 if ((ifp->if_flags ^ sc->if_flags) & 1341 (IFF_PROMISC | IFF_ALLMULTI)) 1342 ffec_setup_rxfilter(sc); 1343 } else { 1344 if (!sc->is_detaching) 1345 ffec_init_locked(sc); 1346 } 1347 } else { 1348 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1349 ffec_stop_locked(sc); 1350 } 1351 sc->if_flags = ifp->if_flags; 1352 FFEC_UNLOCK(sc); 1353 break; 1354 1355 case SIOCADDMULTI: 1356 case SIOCDELMULTI: 1357 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 1358 FFEC_LOCK(sc); 1359 ffec_setup_rxfilter(sc); 1360 FFEC_UNLOCK(sc); 1361 } 1362 break; 1363 1364 case SIOCSIFMEDIA: 1365 case SIOCGIFMEDIA: 1366 mii = sc->mii_softc; 1367 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd); 1368 break; 1369 1370 case SIOCSIFCAP: 1371 mask = ifp->if_capenable ^ ifr->ifr_reqcap; 1372 if (mask & IFCAP_VLAN_MTU) { 1373 /* No work to do except acknowledge the change took. */ 1374 ifp->if_capenable ^= IFCAP_VLAN_MTU; 1375 } 1376 break; 1377 1378 default: 1379 error = ether_ioctl(ifp, cmd, data); 1380 break; 1381 } 1382 1383 return (error); 1384} 1385 1386static int 1387ffec_detach(device_t dev) 1388{ 1389 struct ffec_softc *sc; 1390 bus_dmamap_t map; 1391 int idx, irq; 1392 1393 /* 1394 * NB: This function can be called internally to unwind a failure to 1395 * attach. Make sure a resource got allocated/created before destroying. 1396 */ 1397 1398 sc = device_get_softc(dev); 1399 1400 if (sc->is_attached) { 1401 FFEC_LOCK(sc); 1402 sc->is_detaching = true; 1403 ffec_stop_locked(sc); 1404 FFEC_UNLOCK(sc); 1405 callout_drain(&sc->ffec_callout); 1406 ether_ifdetach(sc->ifp); 1407 } 1408 1409 /* XXX no miibus detach? */ 1410 1411 /* Clean up RX DMA resources and free mbufs. */ 1412 for (idx = 0; idx < RX_DESC_COUNT; ++idx) { 1413 if ((map = sc->rxbuf_map[idx].map) != NULL) { 1414 bus_dmamap_unload(sc->rxbuf_tag, map); 1415 bus_dmamap_destroy(sc->rxbuf_tag, map); 1416 m_freem(sc->rxbuf_map[idx].mbuf); 1417 } 1418 } 1419 if (sc->rxbuf_tag != NULL) 1420 bus_dma_tag_destroy(sc->rxbuf_tag); 1421 if (sc->rxdesc_map != NULL) { 1422 bus_dmamap_unload(sc->rxdesc_tag, sc->rxdesc_map); 1423 bus_dmamap_destroy(sc->rxdesc_tag, sc->rxdesc_map); 1424 } 1425 if (sc->rxdesc_tag != NULL) 1426 bus_dma_tag_destroy(sc->rxdesc_tag); 1427 1428 /* Clean up TX DMA resources. */ 1429 for (idx = 0; idx < TX_DESC_COUNT; ++idx) { 1430 if ((map = sc->txbuf_map[idx].map) != NULL) { 1431 /* TX maps are already unloaded. */ 1432 bus_dmamap_destroy(sc->txbuf_tag, map); 1433 } 1434 } 1435 if (sc->txbuf_tag != NULL) 1436 bus_dma_tag_destroy(sc->txbuf_tag); 1437 if (sc->txdesc_map != NULL) { 1438 bus_dmamap_unload(sc->txdesc_tag, sc->txdesc_map); 1439 bus_dmamap_destroy(sc->txdesc_tag, sc->txdesc_map); 1440 } 1441 if (sc->txdesc_tag != NULL) 1442 bus_dma_tag_destroy(sc->txdesc_tag); 1443 1444 /* Release bus resources. */ 1445 for (irq = 0; irq < MAX_IRQ_COUNT; ++irq) { 1446 if (sc->intr_cookie[irq] != NULL) { 1447 bus_teardown_intr(dev, sc->irq_res[irq], 1448 sc->intr_cookie[irq]); 1449 } 1450 } 1451 bus_release_resources(dev, irq_res_spec, sc->irq_res); 1452 1453 if (sc->mem_res != NULL) 1454 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->mem_res); 1455 1456 FFEC_LOCK_DESTROY(sc); 1457 return (0); 1458} 1459 1460static int 1461ffec_attach(device_t dev) 1462{ 1463 struct ffec_softc *sc; 1464 struct ifnet *ifp = NULL; 1465 struct mbuf *m; 1466 void *dummy; 1467 uintptr_t typeflags; 1468 phandle_t ofw_node; 1469 uint32_t idx, mscr; 1470 int error, phynum, rid, irq; 1471 uint8_t eaddr[ETHER_ADDR_LEN]; 1472 1473 sc = device_get_softc(dev); 1474 sc->dev = dev; 1475 1476 FFEC_LOCK_INIT(sc); 1477 1478 /* 1479 * There are differences in the implementation and features of the FEC 1480 * hardware on different SoCs, so figure out what type we are. 1481 */ 1482 typeflags = ofw_bus_search_compatible(dev, compat_data)->ocd_data; 1483 sc->fectype = (uint8_t)(typeflags & FECTYPE_MASK); 1484 sc->fecflags = (uint32_t)(typeflags & ~FECTYPE_MASK); 1485 1486 if (sc->fecflags & FECFLAG_AVB) { 1487 sc->rxbuf_align = 64; 1488 sc->txbuf_align = 1; 1489 } else { 1490 sc->rxbuf_align = 16; 1491 sc->txbuf_align = 16; 1492 } 1493 1494 /* 1495 * We have to be told what kind of electrical connection exists between 1496 * the MAC and PHY or we can't operate correctly. 1497 */ 1498 if ((ofw_node = ofw_bus_get_node(dev)) == -1) { 1499 device_printf(dev, "Impossible: Can't find ofw bus node\n"); 1500 error = ENXIO; 1501 goto out; 1502 } 1503 sc->phy_conn_type = mii_fdt_get_contype(ofw_node); 1504 if (sc->phy_conn_type == MII_CONTYPE_UNKNOWN) { 1505 device_printf(sc->dev, "No valid 'phy-mode' " 1506 "property found in FDT data for device.\n"); 1507 error = ENOATTR; 1508 goto out; 1509 } 1510 1511 callout_init_mtx(&sc->ffec_callout, &sc->mtx, 0); 1512 1513 /* Allocate bus resources for accessing the hardware. */ 1514 rid = 0; 1515 sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 1516 RF_ACTIVE); 1517 if (sc->mem_res == NULL) { 1518 device_printf(dev, "could not allocate memory resources.\n"); 1519 error = ENOMEM; 1520 goto out; 1521 } 1522 1523 error = bus_alloc_resources(dev, irq_res_spec, sc->irq_res); 1524 if (error != 0) { 1525 device_printf(dev, "could not allocate interrupt resources\n"); 1526 goto out; 1527 } 1528 1529 /* 1530 * Set up TX descriptor ring, descriptors, and dma maps. 1531 */ 1532 error = bus_dma_tag_create( 1533 bus_get_dma_tag(dev), /* Parent tag. */ 1534 FEC_DESC_RING_ALIGN, 0, /* alignment, boundary */ 1535 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 1536 BUS_SPACE_MAXADDR, /* highaddr */ 1537 NULL, NULL, /* filter, filterarg */ 1538 TX_DESC_SIZE, 1, /* maxsize, nsegments */ 1539 TX_DESC_SIZE, /* maxsegsize */ 1540 0, /* flags */ 1541 NULL, NULL, /* lockfunc, lockarg */ 1542 &sc->txdesc_tag); 1543 if (error != 0) { 1544 device_printf(sc->dev, 1545 "could not create TX ring DMA tag.\n"); 1546 goto out; 1547 } 1548 1549 error = bus_dmamem_alloc(sc->txdesc_tag, (void**)&sc->txdesc_ring, 1550 BUS_DMA_COHERENT | BUS_DMA_WAITOK | BUS_DMA_ZERO, &sc->txdesc_map); 1551 if (error != 0) { 1552 device_printf(sc->dev, 1553 "could not allocate TX descriptor ring.\n"); 1554 goto out; 1555 } 1556 1557 error = bus_dmamap_load(sc->txdesc_tag, sc->txdesc_map, sc->txdesc_ring, 1558 TX_DESC_SIZE, ffec_get1paddr, &sc->txdesc_ring_paddr, 0); 1559 if (error != 0) { 1560 device_printf(sc->dev, 1561 "could not load TX descriptor ring map.\n"); 1562 goto out; 1563 } 1564 1565 error = bus_dma_tag_create( 1566 bus_get_dma_tag(dev), /* Parent tag. */ 1567 sc->txbuf_align, 0, /* alignment, boundary */ 1568 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 1569 BUS_SPACE_MAXADDR, /* highaddr */ 1570 NULL, NULL, /* filter, filterarg */ 1571 MCLBYTES, 1, /* maxsize, nsegments */ 1572 MCLBYTES, /* maxsegsize */ 1573 0, /* flags */ 1574 NULL, NULL, /* lockfunc, lockarg */ 1575 &sc->txbuf_tag); 1576 if (error != 0) { 1577 device_printf(sc->dev, 1578 "could not create TX ring DMA tag.\n"); 1579 goto out; 1580 } 1581 1582 for (idx = 0; idx < TX_DESC_COUNT; ++idx) { 1583 error = bus_dmamap_create(sc->txbuf_tag, 0, 1584 &sc->txbuf_map[idx].map); 1585 if (error != 0) { 1586 device_printf(sc->dev, 1587 "could not create TX buffer DMA map.\n"); 1588 goto out; 1589 } 1590 ffec_setup_txdesc(sc, idx, 0, 0); 1591 } 1592 1593 /* 1594 * Set up RX descriptor ring, descriptors, dma maps, and mbufs. 1595 */ 1596 error = bus_dma_tag_create( 1597 bus_get_dma_tag(dev), /* Parent tag. */ 1598 FEC_DESC_RING_ALIGN, 0, /* alignment, boundary */ 1599 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 1600 BUS_SPACE_MAXADDR, /* highaddr */ 1601 NULL, NULL, /* filter, filterarg */ 1602 RX_DESC_SIZE, 1, /* maxsize, nsegments */ 1603 RX_DESC_SIZE, /* maxsegsize */ 1604 0, /* flags */ 1605 NULL, NULL, /* lockfunc, lockarg */ 1606 &sc->rxdesc_tag); 1607 if (error != 0) { 1608 device_printf(sc->dev, 1609 "could not create RX ring DMA tag.\n"); 1610 goto out; 1611 } 1612 1613 error = bus_dmamem_alloc(sc->rxdesc_tag, (void **)&sc->rxdesc_ring, 1614 BUS_DMA_COHERENT | BUS_DMA_WAITOK | BUS_DMA_ZERO, &sc->rxdesc_map); 1615 if (error != 0) { 1616 device_printf(sc->dev, 1617 "could not allocate RX descriptor ring.\n"); 1618 goto out; 1619 } 1620 1621 error = bus_dmamap_load(sc->rxdesc_tag, sc->rxdesc_map, sc->rxdesc_ring, 1622 RX_DESC_SIZE, ffec_get1paddr, &sc->rxdesc_ring_paddr, 0); 1623 if (error != 0) { 1624 device_printf(sc->dev, 1625 "could not load RX descriptor ring map.\n"); 1626 goto out; 1627 } 1628 1629 error = bus_dma_tag_create( 1630 bus_get_dma_tag(dev), /* Parent tag. */ 1631 1, 0, /* alignment, boundary */ 1632 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 1633 BUS_SPACE_MAXADDR, /* highaddr */ 1634 NULL, NULL, /* filter, filterarg */ 1635 MCLBYTES, 1, /* maxsize, nsegments */ 1636 MCLBYTES, /* maxsegsize */ 1637 0, /* flags */ 1638 NULL, NULL, /* lockfunc, lockarg */ 1639 &sc->rxbuf_tag); 1640 if (error != 0) { 1641 device_printf(sc->dev, 1642 "could not create RX buf DMA tag.\n"); 1643 goto out; 1644 } 1645 1646 for (idx = 0; idx < RX_DESC_COUNT; ++idx) { 1647 error = bus_dmamap_create(sc->rxbuf_tag, 0, 1648 &sc->rxbuf_map[idx].map); 1649 if (error != 0) { 1650 device_printf(sc->dev, 1651 "could not create RX buffer DMA map.\n"); 1652 goto out; 1653 } 1654 if ((m = ffec_alloc_mbufcl(sc)) == NULL) { 1655 device_printf(dev, "Could not alloc mbuf\n"); 1656 error = ENOMEM; 1657 goto out; 1658 } 1659 if ((error = ffec_setup_rxbuf(sc, idx, m)) != 0) { 1660 device_printf(sc->dev, 1661 "could not create new RX buffer.\n"); 1662 goto out; 1663 } 1664 } 1665 1666 /* Try to get the MAC address from the hardware before resetting it. */ 1667 ffec_get_hwaddr(sc, eaddr); 1668 1669 /* 1670 * Reset the hardware. Disables all interrupts. 1671 * 1672 * When the FEC is connected to the AXI bus (indicated by AVB flag), a 1673 * MAC reset while a bus transaction is pending can hang the bus. 1674 * Instead of resetting, turn off the ENABLE bit, which allows the 1675 * hardware to complete any in-progress transfers (appending a bad CRC 1676 * to any partial packet) and release the AXI bus. This could probably 1677 * be done unconditionally for all hardware variants, but that hasn't 1678 * been tested. 1679 */ 1680 if (sc->fecflags & FECFLAG_AVB) 1681 WR4(sc, FEC_ECR_REG, 0); 1682 else 1683 WR4(sc, FEC_ECR_REG, FEC_ECR_RESET); 1684 1685 /* Setup interrupt handler. */ 1686 for (irq = 0; irq < MAX_IRQ_COUNT; ++irq) { 1687 if (sc->irq_res[irq] != NULL) { 1688 error = bus_setup_intr(dev, sc->irq_res[irq], 1689 INTR_TYPE_NET | INTR_MPSAFE, NULL, ffec_intr, sc, 1690 &sc->intr_cookie[irq]); 1691 if (error != 0) { 1692 device_printf(dev, 1693 "could not setup interrupt handler.\n"); 1694 goto out; 1695 } 1696 } 1697 } 1698 1699 /* 1700 * Set up the PHY control register. 1701 * 1702 * Speed formula for ENET is md_clock = mac_clock / ((N + 1) * 2). 1703 * Speed formula for FEC is md_clock = mac_clock / (N * 2) 1704 * 1705 * XXX - Revisit this... 1706 * 1707 * For a Wandboard imx6 (ENET) I was originally using 4, but the uboot 1708 * code uses 10. Both values seem to work, but I suspect many modern 1709 * PHY parts can do mdio at speeds far above the standard 2.5 MHz. 1710 * 1711 * Different imx manuals use confusingly different terminology (things 1712 * like "system clock" and "internal module clock") with examples that 1713 * use frequencies that have nothing to do with ethernet, giving the 1714 * vague impression that maybe the clock in question is the periphclock 1715 * or something. In fact, on an imx53 development board (FEC), 1716 * measuring the mdio clock at the pin on the PHY and playing with 1717 * various divisors showed that the root speed was 66 MHz (clk_ipg_root 1718 * aka periphclock) and 13 was the right divisor. 1719 * 1720 * All in all, it seems likely that 13 is a safe divisor for now, 1721 * because if we really do need to base it on the peripheral clock 1722 * speed, then we need a platform-independant get-clock-freq API. 1723 */ 1724 mscr = 13 << FEC_MSCR_MII_SPEED_SHIFT; 1725 if (OF_hasprop(ofw_node, "phy-disable-preamble")) { 1726 mscr |= FEC_MSCR_DIS_PRE; 1727 if (bootverbose) 1728 device_printf(dev, "PHY preamble disabled\n"); 1729 } 1730 WR4(sc, FEC_MSCR_REG, mscr); 1731 1732 /* Set up the ethernet interface. */ 1733 sc->ifp = ifp = if_alloc(IFT_ETHER); 1734 1735 ifp->if_softc = sc; 1736 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1737 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1738 ifp->if_capabilities = IFCAP_VLAN_MTU; 1739 ifp->if_capenable = ifp->if_capabilities; 1740 ifp->if_start = ffec_txstart; 1741 ifp->if_ioctl = ffec_ioctl; 1742 ifp->if_init = ffec_init; 1743 IFQ_SET_MAXLEN(&ifp->if_snd, TX_DESC_COUNT - 1); 1744 ifp->if_snd.ifq_drv_maxlen = TX_DESC_COUNT - 1; 1745 IFQ_SET_READY(&ifp->if_snd); 1746 ifp->if_hdrlen = sizeof(struct ether_vlan_header); 1747 1748#if 0 /* XXX The hardware keeps stats we could use for these. */ 1749 ifp->if_linkmib = &sc->mibdata; 1750 ifp->if_linkmiblen = sizeof(sc->mibdata); 1751#endif 1752 1753 /* Set up the miigasket hardware (if any). */ 1754 ffec_miigasket_setup(sc); 1755 1756 /* Attach the mii driver. */ 1757 if (fdt_get_phyaddr(ofw_node, dev, &phynum, &dummy) != 0) { 1758 phynum = MII_PHY_ANY; 1759 } 1760 error = mii_attach(dev, &sc->miibus, ifp, ffec_media_change, 1761 ffec_media_status, BMSR_DEFCAPMASK, phynum, MII_OFFSET_ANY, 1762 (sc->fecflags & FECTYPE_MVF) ? MIIF_FORCEANEG : 0); 1763 if (error != 0) { 1764 device_printf(dev, "PHY attach failed\n"); 1765 goto out; 1766 } 1767 sc->mii_softc = device_get_softc(sc->miibus); 1768 1769 /* All ready to run, attach the ethernet interface. */ 1770 ether_ifattach(ifp, eaddr); 1771 sc->is_attached = true; 1772 1773 error = 0; 1774out: 1775 1776 if (error != 0) 1777 ffec_detach(dev); 1778 1779 return (error); 1780} 1781 1782static int 1783ffec_probe(device_t dev) 1784{ 1785 uintptr_t fectype; 1786 1787 if (!ofw_bus_status_okay(dev)) 1788 return (ENXIO); 1789 1790 fectype = ofw_bus_search_compatible(dev, compat_data)->ocd_data; 1791 if (fectype == FECTYPE_NONE) 1792 return (ENXIO); 1793 1794 device_set_desc(dev, (fectype & FECFLAG_GBE) ? 1795 "Freescale Gigabit Ethernet Controller" : 1796 "Freescale Fast Ethernet Controller"); 1797 1798 return (BUS_PROBE_DEFAULT); 1799} 1800 1801 1802static device_method_t ffec_methods[] = { 1803 /* Device interface. */ 1804 DEVMETHOD(device_probe, ffec_probe), 1805 DEVMETHOD(device_attach, ffec_attach), 1806 DEVMETHOD(device_detach, ffec_detach), 1807 1808/* 1809 DEVMETHOD(device_shutdown, ffec_shutdown), 1810 DEVMETHOD(device_suspend, ffec_suspend), 1811 DEVMETHOD(device_resume, ffec_resume), 1812*/ 1813 1814 /* MII interface. */ 1815 DEVMETHOD(miibus_readreg, ffec_miibus_readreg), 1816 DEVMETHOD(miibus_writereg, ffec_miibus_writereg), 1817 DEVMETHOD(miibus_statchg, ffec_miibus_statchg), 1818 1819 DEVMETHOD_END 1820}; 1821 1822static driver_t ffec_driver = { 1823 "ffec", 1824 ffec_methods, 1825 sizeof(struct ffec_softc) 1826}; 1827 1828static devclass_t ffec_devclass; 1829 1830DRIVER_MODULE(ffec, simplebus, ffec_driver, ffec_devclass, 0, 0); 1831DRIVER_MODULE(miibus, ffec, miibus_driver, miibus_devclass, 0, 0); 1832 1833MODULE_DEPEND(ffec, ether, 1, 1, 1); 1834MODULE_DEPEND(ffec, miibus, 1, 1, 1); 1835