1/*-
2 * Copyright (c) 2013 Ian Lepore <ian@freebsd.org>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 *    notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 *    notice, this list of conditions and the following disclaimer in the
12 *    documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 */
26
27#include <sys/cdefs.h>
28__FBSDID("$FreeBSD: stable/11/sys/arm/freescale/imx/imx6_ccm.c 331722 2018-03-29 02:50:57Z eadler $");
29
30/*
31 * Clocks and power control driver for Freescale i.MX6 family of SoCs.
32 */
33
34#include <sys/param.h>
35#include <sys/systm.h>
36#include <sys/kernel.h>
37#include <sys/module.h>
38#include <sys/bus.h>
39#include <sys/rman.h>
40
41#include <dev/ofw/ofw_bus.h>
42#include <dev/ofw/ofw_bus_subr.h>
43
44#include <machine/bus.h>
45
46#include <arm/freescale/imx/imx6_anatopreg.h>
47#include <arm/freescale/imx/imx6_anatopvar.h>
48#include <arm/freescale/imx/imx6_ccmreg.h>
49#include <arm/freescale/imx/imx_machdep.h>
50#include <arm/freescale/imx/imx_ccmvar.h>
51
52#ifndef CCGR_CLK_MODE_ALWAYS
53#define	CCGR_CLK_MODE_OFF		0
54#define	CCGR_CLK_MODE_RUNMODE		1
55#define	CCGR_CLK_MODE_ALWAYS		3
56#endif
57
58struct ccm_softc {
59	device_t	dev;
60	struct resource	*mem_res;
61};
62
63static struct ccm_softc *ccm_sc;
64
65static inline uint32_t
66RD4(struct ccm_softc *sc, bus_size_t off)
67{
68
69	return (bus_read_4(sc->mem_res, off));
70}
71
72static inline void
73WR4(struct ccm_softc *sc, bus_size_t off, uint32_t val)
74{
75
76	bus_write_4(sc->mem_res, off, val);
77}
78
79/*
80 * Until we have a fully functional ccm driver which implements the fdt_clock
81 * interface, use the age-old workaround of unconditionally enabling the clocks
82 * for devices we might need to use.  The SoC defaults to most clocks enabled,
83 * but the rom boot code and u-boot disable a few of them.  We turn on only
84 * what's needed to run the chip plus devices we have drivers for, and turn off
85 * devices we don't yet have drivers for.  (Note that USB is not turned on here
86 * because that is one we do when the driver asks for it.)
87 */
88static void
89ccm_init_gates(struct ccm_softc *sc)
90{
91	uint32_t reg;
92
93 	/* ahpbdma, aipstz 1 & 2 busses */
94	reg = CCGR0_AIPS_TZ1 | CCGR0_AIPS_TZ2 | CCGR0_ABPHDMA;
95	WR4(sc, CCM_CCGR0, reg);
96
97	/* enet, epit, gpt, spi */
98	reg = CCGR1_ENET | CCGR1_EPIT1 | CCGR1_GPT | CCGR1_ECSPI1 |
99	    CCGR1_ECSPI2 | CCGR1_ECSPI3 | CCGR1_ECSPI4 | CCGR1_ECSPI5;
100	WR4(sc, CCM_CCGR1, reg);
101
102	/* ipmux & ipsync (bridges), iomux, i2c */
103	reg = CCGR2_I2C1 | CCGR2_I2C2 | CCGR2_I2C3 | CCGR2_IIM |
104	    CCGR2_IOMUX_IPT | CCGR2_IPMUX1 | CCGR2_IPMUX2 | CCGR2_IPMUX3 |
105	    CCGR2_IPSYNC_IP2APB_TZASC1 | CCGR2_IPSYNC_IP2APB_TZASC2 |
106	    CCGR2_IPSYNC_VDOA;
107	WR4(sc, CCM_CCGR2, reg);
108
109	/* DDR memory controller */
110	reg = CCGR3_OCRAM | CCGR3_MMDC_CORE_IPG |
111	    CCGR3_MMDC_CORE_ACLK_FAST | CCGR3_CG11 | CCGR3_CG13;
112	WR4(sc, CCM_CCGR3, reg);
113
114	/* pl301 bus crossbar */
115	reg = CCGR4_PL301_MX6QFAST1_S133 |
116	    CCGR4_PL301_MX6QPER1_BCH | CCGR4_PL301_MX6QPER2_MAIN;
117	WR4(sc, CCM_CCGR4, reg);
118
119	/* uarts, ssi, sdma */
120	reg = CCGR5_SDMA | CCGR5_SSI1 | CCGR5_SSI2 | CCGR5_SSI3 |
121	    CCGR5_UART | CCGR5_UART_SERIAL;
122	WR4(sc, CCM_CCGR5, reg);
123
124	/* usdhc 1-4, usboh3 */
125	reg = CCGR6_USBOH3 | CCGR6_USDHC1 | CCGR6_USDHC2 |
126	    CCGR6_USDHC3 | CCGR6_USDHC4;
127	WR4(sc, CCM_CCGR6, reg);
128}
129
130static int
131ccm_detach(device_t dev)
132{
133	struct ccm_softc *sc;
134
135	sc = device_get_softc(dev);
136
137	if (sc->mem_res != NULL)
138		bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->mem_res);
139
140	return (0);
141}
142
143static int
144ccm_attach(device_t dev)
145{
146	struct ccm_softc *sc;
147	int err, rid;
148	uint32_t reg;
149
150	sc = device_get_softc(dev);
151	err = 0;
152
153	/* Allocate bus_space resources. */
154	rid = 0;
155	sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
156	    RF_ACTIVE);
157	if (sc->mem_res == NULL) {
158		device_printf(dev, "Cannot allocate memory resources\n");
159		err = ENXIO;
160		goto out;
161	}
162
163	ccm_sc = sc;
164
165	/*
166	 * Configure the Low Power Mode setting to leave the ARM core power on
167	 * when a WFI instruction is executed.  This lets the MPCore timers and
168	 * GIC continue to run, which is helpful when the only thing that can
169	 * wake you up is an MPCore Private Timer interrupt delivered via GIC.
170	 *
171	 * XXX Based on the docs, setting CCM_CGPR_INT_MEM_CLK_LPM shouldn't be
172	 * required when the LPM bits are set to LPM_RUN.  But experimentally
173	 * I've experienced a fairly rare lockup when not setting it.  I was
174	 * unable to prove conclusively that the lockup was related to power
175	 * management or that this definitively fixes it.  Revisit this.
176	 */
177	reg = RD4(sc, CCM_CGPR);
178	reg |= CCM_CGPR_INT_MEM_CLK_LPM;
179	WR4(sc, CCM_CGPR, reg);
180	reg = RD4(sc, CCM_CLPCR);
181	reg = (reg & ~CCM_CLPCR_LPM_MASK) | CCM_CLPCR_LPM_RUN;
182	WR4(sc, CCM_CLPCR, reg);
183
184	ccm_init_gates(sc);
185
186	err = 0;
187
188out:
189
190	if (err != 0)
191		ccm_detach(dev);
192
193	return (err);
194}
195
196static int
197ccm_probe(device_t dev)
198{
199
200	if (!ofw_bus_status_okay(dev))
201		return (ENXIO);
202
203        if (ofw_bus_is_compatible(dev, "fsl,imx6q-ccm") == 0)
204		return (ENXIO);
205
206	device_set_desc(dev, "Freescale i.MX6 Clock Control Module");
207
208	return (BUS_PROBE_DEFAULT);
209}
210
211void
212imx_ccm_ssi_configure(device_t _ssidev)
213{
214	struct ccm_softc *sc;
215	uint32_t reg;
216
217	sc = ccm_sc;
218
219	/*
220	 * Select PLL4 (Audio PLL) clock multiplexer as source.
221	 * PLL output frequency = Fref * (DIV_SELECT + NUM/DENOM).
222	 */
223
224	reg = RD4(sc, CCM_CSCMR1);
225	reg &= ~(SSI_CLK_SEL_M << SSI1_CLK_SEL_S);
226	reg |= (SSI_CLK_SEL_PLL4 << SSI1_CLK_SEL_S);
227	reg &= ~(SSI_CLK_SEL_M << SSI2_CLK_SEL_S);
228	reg |= (SSI_CLK_SEL_PLL4 << SSI2_CLK_SEL_S);
229	reg &= ~(SSI_CLK_SEL_M << SSI3_CLK_SEL_S);
230	reg |= (SSI_CLK_SEL_PLL4 << SSI3_CLK_SEL_S);
231	WR4(sc, CCM_CSCMR1, reg);
232
233	/*
234	 * Ensure we have set hardware-default values
235	 * for pre and post dividers.
236	 */
237
238	/* SSI1 and SSI3 */
239	reg = RD4(sc, CCM_CS1CDR);
240	/* Divide by 2 */
241	reg &= ~(SSI_CLK_PODF_MASK << SSI1_CLK_PODF_SHIFT);
242	reg &= ~(SSI_CLK_PODF_MASK << SSI3_CLK_PODF_SHIFT);
243	reg |= (0x1 << SSI1_CLK_PODF_SHIFT);
244	reg |= (0x1 << SSI3_CLK_PODF_SHIFT);
245	/* Divide by 4 */
246	reg &= ~(SSI_CLK_PRED_MASK << SSI1_CLK_PRED_SHIFT);
247	reg &= ~(SSI_CLK_PRED_MASK << SSI3_CLK_PRED_SHIFT);
248	reg |= (0x3 << SSI1_CLK_PRED_SHIFT);
249	reg |= (0x3 << SSI3_CLK_PRED_SHIFT);
250	WR4(sc, CCM_CS1CDR, reg);
251
252	/* SSI2 */
253	reg = RD4(sc, CCM_CS2CDR);
254	/* Divide by 2 */
255	reg &= ~(SSI_CLK_PODF_MASK << SSI2_CLK_PODF_SHIFT);
256	reg |= (0x1 << SSI2_CLK_PODF_SHIFT);
257	/* Divide by 4 */
258	reg &= ~(SSI_CLK_PRED_MASK << SSI2_CLK_PRED_SHIFT);
259	reg |= (0x3 << SSI2_CLK_PRED_SHIFT);
260	WR4(sc, CCM_CS2CDR, reg);
261}
262
263void
264imx_ccm_usb_enable(device_t _usbdev)
265{
266
267	/*
268	 * For imx6, the USBOH3 clock gate is bits 0-1 of CCGR6, so no need for
269	 * shifting and masking here, just set the low-order two bits to ALWAYS.
270	 */
271	WR4(ccm_sc, CCM_CCGR6, RD4(ccm_sc, CCM_CCGR6) | CCGR_CLK_MODE_ALWAYS);
272}
273
274void
275imx_ccm_usbphy_enable(device_t _phydev)
276{
277        /*
278         * XXX Which unit?
279         * Right now it's not clear how to figure from fdt data which phy unit
280         * we're supposed to operate on.  Until this is worked out, just enable
281         * both PHYs.
282         */
283#if 0
284	int phy_num, regoff;
285
286	phy_num = 0; /* XXX */
287
288	switch (phy_num) {
289	case 0:
290		regoff = 0;
291		break;
292	case 1:
293		regoff = 0x10;
294		break;
295	default:
296		device_printf(ccm_sc->dev, "Bad PHY number %u,\n",
297		    phy_num);
298		return;
299	}
300
301	imx6_anatop_write_4(IMX6_ANALOG_CCM_PLL_USB1 + regoff,
302	    IMX6_ANALOG_CCM_PLL_USB_ENABLE |
303	    IMX6_ANALOG_CCM_PLL_USB_POWER |
304	    IMX6_ANALOG_CCM_PLL_USB_EN_USB_CLKS);
305#else
306	imx6_anatop_write_4(IMX6_ANALOG_CCM_PLL_USB1 + 0,
307	    IMX6_ANALOG_CCM_PLL_USB_ENABLE |
308	    IMX6_ANALOG_CCM_PLL_USB_POWER |
309	    IMX6_ANALOG_CCM_PLL_USB_EN_USB_CLKS);
310
311	imx6_anatop_write_4(IMX6_ANALOG_CCM_PLL_USB1 + 0x10,
312	    IMX6_ANALOG_CCM_PLL_USB_ENABLE |
313	    IMX6_ANALOG_CCM_PLL_USB_POWER |
314	    IMX6_ANALOG_CCM_PLL_USB_EN_USB_CLKS);
315#endif
316}
317
318int
319imx6_ccm_sata_enable(void)
320{
321	uint32_t v;
322	int timeout;
323
324	/* Un-gate the sata controller. */
325	WR4(ccm_sc, CCM_CCGR5, RD4(ccm_sc, CCM_CCGR5) | CCGR5_SATA);
326
327	/* Power up the PLL that feeds ENET/SATA/PCI phys, wait for lock. */
328	v = RD4(ccm_sc, CCM_ANALOG_PLL_ENET);
329	v &= ~CCM_ANALOG_PLL_ENET_POWERDOWN;
330	WR4(ccm_sc, CCM_ANALOG_PLL_ENET, v);
331
332	for (timeout = 100000; timeout > 0; timeout--) {
333		if (RD4(ccm_sc, CCM_ANALOG_PLL_ENET) &
334		   CCM_ANALOG_PLL_ENET_LOCK) {
335			break;
336		}
337	}
338	if (timeout <= 0) {
339		return ETIMEDOUT;
340	}
341
342	/* Enable the PLL, and enable its 100mhz output. */
343	v |= CCM_ANALOG_PLL_ENET_ENABLE;
344	v &= ~CCM_ANALOG_PLL_ENET_BYPASS;
345	WR4(ccm_sc, CCM_ANALOG_PLL_ENET, v);
346
347	v |= CCM_ANALOG_PLL_ENET_ENABLE_100M;
348	WR4(ccm_sc, CCM_ANALOG_PLL_ENET, v);
349
350	return 0;
351}
352
353uint32_t
354imx_ccm_ecspi_hz(void)
355{
356
357	return (60000000);
358}
359
360uint32_t
361imx_ccm_ipg_hz(void)
362{
363
364	return (66000000);
365}
366
367uint32_t
368imx_ccm_perclk_hz(void)
369{
370
371	return (66000000);
372}
373
374uint32_t
375imx_ccm_sdhci_hz(void)
376{
377
378	return (200000000);
379}
380
381uint32_t
382imx_ccm_uart_hz(void)
383{
384
385	return (80000000);
386}
387
388uint32_t
389imx_ccm_ahb_hz(void)
390{
391	return (132000000);
392}
393
394void
395imx_ccm_ipu_enable(int ipu)
396{
397	struct ccm_softc *sc;
398	uint32_t reg;
399
400	sc = ccm_sc;
401	reg = RD4(sc, CCM_CCGR3);
402	if (ipu == 1)
403		reg |= CCGR3_IPU1_IPU | CCGR3_IPU1_DI0;
404	else
405		reg |= CCGR3_IPU2_IPU | CCGR3_IPU2_DI0;
406	WR4(sc, CCM_CCGR3, reg);
407}
408
409void
410imx_ccm_hdmi_enable(void)
411{
412	struct ccm_softc *sc;
413	uint32_t reg;
414
415	sc = ccm_sc;
416	reg = RD4(sc, CCM_CCGR2);
417	reg |= CCGR2_HDMI_TX | CCGR2_HDMI_TX_ISFR;
418	WR4(sc, CCM_CCGR2, reg);
419
420	/* Set HDMI clock to 280MHz */
421	reg = RD4(sc, CCM_CHSCCDR);
422	reg &= ~(CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK |
423	    CHSCCDR_IPU1_DI0_PODF_MASK | CHSCCDR_IPU1_DI0_CLK_SEL_MASK);
424	reg |= (CHSCCDR_PODF_DIVIDE_BY_3 << CHSCCDR_IPU1_DI0_PODF_SHIFT);
425	reg |= (CHSCCDR_IPU_PRE_CLK_540M_PFD << CHSCCDR_IPU1_DI0_PRE_CLK_SEL_SHIFT);
426	WR4(sc, CCM_CHSCCDR, reg);
427	reg |= (CHSCCDR_CLK_SEL_LDB_DI0 << CHSCCDR_IPU1_DI0_CLK_SEL_SHIFT);
428	WR4(sc, CCM_CHSCCDR, reg);
429}
430
431uint32_t
432imx_ccm_get_cacrr(void)
433{
434
435	return (RD4(ccm_sc, CCM_CACCR));
436}
437
438void
439imx_ccm_set_cacrr(uint32_t divisor)
440{
441
442	WR4(ccm_sc, CCM_CACCR, divisor);
443}
444
445static device_method_t ccm_methods[] = {
446	/* Device interface */
447	DEVMETHOD(device_probe,  ccm_probe),
448	DEVMETHOD(device_attach, ccm_attach),
449	DEVMETHOD(device_detach, ccm_detach),
450
451	DEVMETHOD_END
452};
453
454static driver_t ccm_driver = {
455	"ccm",
456	ccm_methods,
457	sizeof(struct ccm_softc)
458};
459
460static devclass_t ccm_devclass;
461
462EARLY_DRIVER_MODULE(ccm, simplebus, ccm_driver, ccm_devclass, 0, 0,
463    BUS_PASS_CPU + BUS_PASS_ORDER_EARLY);
464
465