arm/at91/at91_mci.c

190 WR4(struct at91_mci_softc *sc, bus_size_t off, uint32_t val)
243 	WR4(sc, PDC_PTCR, PDC_PTCR_TXTDIS | PDC_PTCR_RXTDIS);
244 	WR4(sc, PDC_RPR, 0);
245 	WR4(sc, PDC_RCR, 0);
246 	WR4(sc, PDC_RNPR, 0);
247 	WR4(sc, PDC_RNCR, 0);
248 	WR4(sc, PDC_TPR, 0);
249 	WR4(sc, PDC_TCR, 0);
250 	WR4(sc, PDC_TNPR, 0);
251 	WR4(sc, PDC_TNCR, 0);
279 	WR4(sc, MCI_IDR, 0xffffffff);
280 	WR4(sc, MCI_CR, MCI_CR_MCIDIS | MCI_CR_SWRST);
284 	WR4(sc, MCI_CR, MCI_CR_MCIEN|MCI_CR_PWSEN);
285 	WR4(sc, MCI_MR, mr);
286 	WR4(sc, MCI_SDCR, sdcr);
287 	WR4(sc, MCI_DTOR, dtor);
288 	WR4(sc, MCI_IER, imr);
304 	WR4(sc, MCI_CR, MCI_CR_MCIDIS | MCI_CR_SWRST); /* device into reset */
305 	WR4(sc, MCI_IDR, 0xffffffff);		/* Turn off interrupts */
306 	WR4(sc, MCI_DTOR, MCI_DTOR_DTOMUL_1M | 1);
311 	WR4(sc, MCI_MR, val);
313 	WR4(sc, MCI_SDCR, 0);			/* SLOT A, 1 bit bus */
319 	WR4(sc, MCI_SDCR, 1);			/* SLOT B, 1 bit bus */
327 	WR4(sc, MCI_CR, MCI_CR_MCIEN|MCI_CR_PWSEN);
335 	WR4(sc, MCI_IDR, 0xffffffff);		/* Turn off interrupts */
337 	WR4(sc, MCI_CR, MCI_CR_MCIDIS | MCI_CR_SWRST); /* device into reset */
573 		WR4(sc, MCI_CR, MCI_CR_MCIDIS);
576 		WR4(sc, MCI_CR, MCI_CR_MCIEN|MCI_CR_PWSEN);
591 		WR4(sc, MCI_SDCR, RD4(sc, MCI_SDCR) | MCI_SDCR_SDCBUS);
593 		WR4(sc, MCI_SDCR, RD4(sc, MCI_SDCR) & ~MCI_SDCR_SDCBUS);
594 	WR4(sc, MCI_MR, (RD4(sc, MCI_MR) & ~MCI_MR_CLKDIV) | clkdiv);
664 		WR4(sc, MCI_ARGR, cmd->arg);
665 		WR4(sc, MCI_CMDR, cmdr);
666 		WR4(sc, MCI_IDR, 0xffffffff);
667 		WR4(sc, MCI_IER, ier);
696 	WR4(sc, PDC_PTCR, PDC_PTCR_RXTDIS | PDC_PTCR_TXTDIS);
700 	WR4(sc, MCI_MR, mr | MCI_MR_PDCMODE|MCI_MR_PDCPADV);
756 			WR4(sc, PDC_RPR, paddr);
757 			WR4(sc, PDC_RCR, len / 4);
771 				WR4(sc, PDC_RNPR, paddr);
772 				WR4(sc, PDC_RNCR, len / 4);
776 			WR4(sc, PDC_PTCR, PDC_PTCR_RXTEN);
792 			WR4(sc, PDC_TPR,paddr);
793 			WR4(sc, PDC_TCR, (len < 12) ? 3 : len / 4);
809 				WR4(sc, PDC_TNPR, paddr);
810 				WR4(sc, PDC_TNCR, (len < 12) ? 3 : len / 4);
823 	WR4(sc, MCI_ARGR, cmd->arg);
824 	WR4(sc, MCI_CMDR, cmdr);
825 	WR4(sc, MCI_IER, MCI_SR_ERROR | MCI_SR_CMDRDY);
847 	WR4(sc, MCI_IDR, 0xffffffff);
944 		WR4(sc, PDC_PTCR, PDC_PTCR_RXTDIS | PDC_PTCR_TXTDIS);
948 		WR4(sc, PDC_RNCR, 0);
949 		WR4(sc, MCI_IER, MCI_SR_ERROR | MCI_SR_ENDRX);
967 	WR4(sc, PDC_PTCR, PDC_PTCR_RXTDIS | PDC_PTCR_TXTDIS);
977 		WR4(sc, MCI_IER, MCI_SR_ERROR | MCI_SR_NOTBUSY);
1042 		WR4(sc, MCI_IER, MCI_SR_ERROR | MCI_SR_NOTBUSY);
1128 		WR4(sc, MCI_IER, MCI_SR_ERROR | MCI_SR_NOTBUSY);
1148 			WR4(sc, PDC_PTCR, PDC_PTCR_TXTEN);
1150 		WR4(sc, MCI_IER, MCI_SR_ERROR | ier);
1182 	WR4(sc, MCI_IDR, isr);
1223 				WR4(sc, MCI_IER, MCI_SR_BLKE);