Searched refs:barrier (Results 76 - 100 of 545) sorted by last modified time

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/linux-master/drivers/perf/
H A D	xgene_pmu.c	452 XGENE_PMU_EVENT_ATTR(pa-barrier-occurrence, 0x1c), 453 XGENE_PMU_EVENT_ATTR(pa-barrier-cycles, 0x1d),
H A D	qcom_l2_pmu.c	23 #include <asm/barrier.h>
H A D	arm_spe_pmu.c	37 #include <asm/barrier.h>
/linux-master/drivers/net/ethernet/sun/
H A D	sunhme.c	145 * correct. I've added a write memory barrier between 569 barrier();
/linux-master/drivers/net/ethernet/broadcom/
H A D	tg3.c	6548 barrier(); 6649 * memory barrier, there is a small possibility that __tg3_start_xmit()
/linux-master/drivers/md/dm-vdo/indexer/
H A D	sparse-cache.c	27 * via the careful use of barrier messages sent to all the index zones by the triage queue worker 37 * and the serialization of the barrier requests from the triage queue ensures they will all 41 * are known to be blocked, waiting in the second barrier. Outside that critical section, all the 144 /* Lock for this barrier object */ 146 /* Semaphore for threads waiting at this barrier */ 150 /* Total number of threads using this barrier */ 169 static void initialize_threads_barrier(struct threads_barrier *barrier, argument 172 sema_init(&barrier->lock, 1); 173 barrier->arrived = 0; 174 barrier 199 enter_threads_barrier(struct threads_barrier *barrier) argument [all...]
/linux-master/drivers/iommu/amd/
H A D	io_pgtable_v2.c	17 #include <asm/barrier.h>
/linux-master/drivers/gpu/drm/v3d/
H A D	v3d_drv.h	459 barrier(); \
/linux-master/drivers/gpu/drm/mediatek/
H A D	mtk_drm_crtc.c	15 #include <asm/barrier.h>
/linux-master/drivers/gpu/drm/i915/
H A D	i915_utils.h	270 barrier(); \ 312 barrier(); \
H A D	i915_utils.c	115 barrier();
/linux-master/drivers/gpu/drm/amd/amdkfd/
H A D	cwsr_trap_handler_gfx10.asm	1152 // Clear DEBUG_EN before and restore MODE after the barrier. 1154 s_barrier //barrier to ensure the readiness of LDS before access attemps from any other wave in the same TG
/linux-master/arch/x86/mm/
H A D	tlb.c	548 * The membarrier system call requires a full memory barrier and 555 * when it really should issue a memory barrier. Writing to CR3 556 * provides that full memory barrier and core serializing 589 * The barrier synchronizes with the tlb_gen increment in 633 barrier(); 651 barrier(); 993 barrier(); 1015 /* This is also a barrier that synchronizes with switch_mm(). */
/linux-master/arch/x86/kernel/
H A D	alternative.c	1918 * Loading the temporary mm behaves as a compiler barrier, which 1929 * were issued by using a compiler barrier. 1931 barrier(); 2267 * Corresponds to the implicit memory barrier in try_get_desc() to 2283 * Corresponding read barrier in int3 notifier for making sure the
/linux-master/arch/sparc/kernel/
H A D	ds.c	824 barrier();
/linux-master/arch/s390/mm/
H A D	pgtable.c	143 barrier();
/linux-master/arch/arm64/mm/
H A D	mmu.c	29 #include <asm/barrier.h>
/linux-master/arch/arm64/kernel/
H A D	process.c	263 barrier(); 537 * This full barrier is also required by the membarrier system
H A D	mte.c	21 #include <asm/barrier.h>
H A D	fpsimd.c	1821 * This function may be called with preemption enabled. The barrier() 1826 * The final barrier ensures that TIF_FOREIGN_FPSTATE is seen set by any 1839 barrier(); 1842 barrier();
/linux-master/arch/arm64/include/asm/
H A D	io.h	15 #include <asm/barrier.h>
/linux-master/arch/arm/mm/
H A D	mmu.c	1661 * must get this prior to the pv update. The following barrier 1666 barrier();
/linux-master/tools/lib/bpf/
H A D	bpf_helpers.h	98 * Compiler (optimization) barrier. 100 #ifndef barrier 101 #define barrier() asm volatile("" ::: "memory") macro 104 /* Variable-specific compiler (optimization) barrier. It's a no-op which makes 115 * This is a variable-specific variant of more global barrier().
/linux-master/security/selinux/ss/
H A D	sidtab.c	18 #include <asm/barrier.h>
/linux-master/net/xfrm/
H A D	espintcp.c	535 barrier();

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Indexes created Sat May 04 09:44:38 MDT 2024