1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * Based on arch/arm/include/asm/io.h
4 *
5 * Copyright (C) 1996-2000 Russell King
6 * Copyright (C) 2012 ARM Ltd.
7 */
8#ifndef __ASM_IO_H
9#define __ASM_IO_H
10
11#include <linux/types.h>
12#include <linux/pgtable.h>
13
14#include <asm/byteorder.h>
15#include <asm/barrier.h>
16#include <asm/memory.h>
17#include <asm/early_ioremap.h>
18#include <asm/alternative.h>
19#include <asm/cpufeature.h>
20
21/*
22 * Generic IO read/write.  These perform native-endian accesses.
23 */
24#define __raw_writeb __raw_writeb
25static __always_inline void __raw_writeb(u8 val, volatile void __iomem *addr)
26{
27	volatile u8 __iomem *ptr = addr;
28	asm volatile("strb %w0, %1" : : "rZ" (val), "Qo" (*ptr));
29}
30
31#define __raw_writew __raw_writew
32static __always_inline void __raw_writew(u16 val, volatile void __iomem *addr)
33{
34	volatile u16 __iomem *ptr = addr;
35	asm volatile("strh %w0, %1" : : "rZ" (val), "Qo" (*ptr));
36}
37
38#define __raw_writel __raw_writel
39static __always_inline void __raw_writel(u32 val, volatile void __iomem *addr)
40{
41	volatile u32 __iomem *ptr = addr;
42	asm volatile("str %w0, %1" : : "rZ" (val), "Qo" (*ptr));
43}
44
45#define __raw_writeq __raw_writeq
46static __always_inline void __raw_writeq(u64 val, volatile void __iomem *addr)
47{
48	volatile u64 __iomem *ptr = addr;
49	asm volatile("str %x0, %1" : : "rZ" (val), "Qo" (*ptr));
50}
51
52#define __raw_readb __raw_readb
53static __always_inline u8 __raw_readb(const volatile void __iomem *addr)
54{
55	u8 val;
56	asm volatile(ALTERNATIVE("ldrb %w0, [%1]",
57				 "ldarb %w0, [%1]",
58				 ARM64_WORKAROUND_DEVICE_LOAD_ACQUIRE)
59		     : "=r" (val) : "r" (addr));
60	return val;
61}
62
63#define __raw_readw __raw_readw
64static __always_inline u16 __raw_readw(const volatile void __iomem *addr)
65{
66	u16 val;
67
68	asm volatile(ALTERNATIVE("ldrh %w0, [%1]",
69				 "ldarh %w0, [%1]",
70				 ARM64_WORKAROUND_DEVICE_LOAD_ACQUIRE)
71		     : "=r" (val) : "r" (addr));
72	return val;
73}
74
75#define __raw_readl __raw_readl
76static __always_inline u32 __raw_readl(const volatile void __iomem *addr)
77{
78	u32 val;
79	asm volatile(ALTERNATIVE("ldr %w0, [%1]",
80				 "ldar %w0, [%1]",
81				 ARM64_WORKAROUND_DEVICE_LOAD_ACQUIRE)
82		     : "=r" (val) : "r" (addr));
83	return val;
84}
85
86#define __raw_readq __raw_readq
87static __always_inline u64 __raw_readq(const volatile void __iomem *addr)
88{
89	u64 val;
90	asm volatile(ALTERNATIVE("ldr %0, [%1]",
91				 "ldar %0, [%1]",
92				 ARM64_WORKAROUND_DEVICE_LOAD_ACQUIRE)
93		     : "=r" (val) : "r" (addr));
94	return val;
95}
96
97/* IO barriers */
98#define __io_ar(v)							\
99({									\
100	unsigned long tmp;						\
101									\
102	dma_rmb();								\
103									\
104	/*								\
105	 * Create a dummy control dependency from the IO read to any	\
106	 * later instructions. This ensures that a subsequent call to	\
107	 * udelay() will be ordered due to the ISB in get_cycles().	\
108	 */								\
109	asm volatile("eor	%0, %1, %1\n"				\
110		     "cbnz	%0, ."					\
111		     : "=r" (tmp) : "r" ((unsigned long)(v))		\
112		     : "memory");					\
113})
114
115#define __io_bw()		dma_wmb()
116#define __io_br(v)
117#define __io_aw(v)
118
119/* arm64-specific, don't use in portable drivers */
120#define __iormb(v)		__io_ar(v)
121#define __iowmb()		__io_bw()
122#define __iomb()		dma_mb()
123
124/*
125 *  I/O port access primitives.
126 */
127#define arch_has_dev_port()	(1)
128#define IO_SPACE_LIMIT		(PCI_IO_SIZE - 1)
129#define PCI_IOBASE		((void __iomem *)PCI_IO_START)
130
131/*
132 * String version of I/O memory access operations.
133 */
134extern void __memcpy_fromio(void *, const volatile void __iomem *, size_t);
135extern void __memcpy_toio(volatile void __iomem *, const void *, size_t);
136extern void __memset_io(volatile void __iomem *, int, size_t);
137
138#define memset_io(c,v,l)	__memset_io((c),(v),(l))
139#define memcpy_fromio(a,c,l)	__memcpy_fromio((a),(c),(l))
140#define memcpy_toio(c,a,l)	__memcpy_toio((c),(a),(l))
141
142/*
143 * I/O memory mapping functions.
144 */
145
146#define ioremap_prot ioremap_prot
147
148#define _PAGE_IOREMAP PROT_DEVICE_nGnRE
149
150#define ioremap_wc(addr, size)	\
151	ioremap_prot((addr), (size), PROT_NORMAL_NC)
152#define ioremap_np(addr, size)	\
153	ioremap_prot((addr), (size), PROT_DEVICE_nGnRnE)
154
155/*
156 * io{read,write}{16,32,64}be() macros
157 */
158#define ioread16be(p)		({ __u16 __v = be16_to_cpu((__force __be16)__raw_readw(p)); __iormb(__v); __v; })
159#define ioread32be(p)		({ __u32 __v = be32_to_cpu((__force __be32)__raw_readl(p)); __iormb(__v); __v; })
160#define ioread64be(p)		({ __u64 __v = be64_to_cpu((__force __be64)__raw_readq(p)); __iormb(__v); __v; })
161
162#define iowrite16be(v,p)	({ __iowmb(); __raw_writew((__force __u16)cpu_to_be16(v), p); })
163#define iowrite32be(v,p)	({ __iowmb(); __raw_writel((__force __u32)cpu_to_be32(v), p); })
164#define iowrite64be(v,p)	({ __iowmb(); __raw_writeq((__force __u64)cpu_to_be64(v), p); })
165
166#include <asm-generic/io.h>
167
168#define ioremap_cache ioremap_cache
169static inline void __iomem *ioremap_cache(phys_addr_t addr, size_t size)
170{
171	if (pfn_is_map_memory(__phys_to_pfn(addr)))
172		return (void __iomem *)__phys_to_virt(addr);
173
174	return ioremap_prot(addr, size, PROT_NORMAL);
175}
176
177/*
178 * More restrictive address range checking than the default implementation
179 * (PHYS_OFFSET and PHYS_MASK taken into account).
180 */
181#define ARCH_HAS_VALID_PHYS_ADDR_RANGE
182extern int valid_phys_addr_range(phys_addr_t addr, size_t size);
183extern int valid_mmap_phys_addr_range(unsigned long pfn, size_t size);
184
185extern bool arch_memremap_can_ram_remap(resource_size_t offset, size_t size,
186					unsigned long flags);
187#define arch_memremap_can_ram_remap arch_memremap_can_ram_remap
188
189#endif	/* __ASM_IO_H */
190