/linux-master/arch/x86/platform/ce4100/ |
H A D | ce4100.c | 39 return readl(p->membase + offset); 58 ret = readl(p->membase + offset); 79 writel(value, p->membase + offset); 96 up->membase = 98 up->membase += up->mapbase & ~PAGE_MASK; 100 up->membase += port * 0x100;
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/linux-master/drivers/tty/serial/ |
H A D | mvebu-uart.c | 191 st = readl(port->membase + UART_STAT); 213 unsigned int ctl = readl(port->membase + UART_INTR(port)); 216 writel(ctl, port->membase + UART_INTR(port)); 225 writel(xmit->buf[xmit->tail], port->membase + UART_TSH(port)); 229 ctl = readl(port->membase + UART_INTR(port)); 231 writel(ctl, port->membase + UART_INTR(port)); 238 ctl = readl(port->membase + UART_CTRL(port)); 240 writel(ctl, port->membase + UART_CTRL(port)); 242 ctl = readl(port->membase + UART_INTR(port)); 244 writel(ctl, port->membase [all...] |
H A D | meson_uart.c | 102 val = readl(port->membase + AML_UART_STATUS); 111 val = readl(port->membase + AML_UART_CONTROL); 113 writel(val, port->membase + AML_UART_CONTROL); 120 val = readl(port->membase + AML_UART_CONTROL); 122 writel(val, port->membase + AML_UART_CONTROL); 134 val = readl(port->membase + AML_UART_CONTROL); 137 writel(val, port->membase + AML_UART_CONTROL); 153 while (!(readl(port->membase + AML_UART_STATUS) & AML_UART_TX_FULL)) { 155 writel(port->x_char, port->membase + AML_UART_WFIFO); 165 writel(ch, port->membase [all...] |
H A D | sunplus-uart.c | 82 writel(ch, port->membase + SUP_UART_DATA); 87 unsigned int lsr = readl(port->membase + SUP_UART_LSR); 94 unsigned int lsr = readl(port->membase + SUP_UART_LSR); 101 unsigned int mcr = readl(port->membase + SUP_UART_MCR); 128 writel(mcr, port->membase + SUP_UART_MCR); 135 mcr = readl(port->membase + SUP_UART_MCR); 159 isc = readl(port->membase + SUP_UART_ISC); 161 writel(isc, port->membase + SUP_UART_ISC); 168 isc = readl(port->membase + SUP_UART_ISC); 170 writel(isc, port->membase [all...] |
H A D | digicolor-usart.c | 85 return !!(readb_relaxed(port->membase + UA_STATUS_FIFO) & 91 return !!(readb_relaxed(port->membase + UA_STATUS_FIFO) & 97 u8 int_enable = readb_relaxed(port->membase + UA_INT_ENABLE); 100 writeb_relaxed(int_enable, port->membase + UA_INT_ENABLE); 105 u8 int_enable = readb_relaxed(port->membase + UA_INT_ENABLE); 108 writeb_relaxed(int_enable, port->membase + UA_INT_ENABLE); 113 u8 int_enable = readb_relaxed(port->membase + UA_INT_ENABLE); 116 writeb_relaxed(int_enable, port->membase + UA_INT_ENABLE); 127 writeb_relaxed(UA_INT_RX, dp->port.membase + UA_INTFLAG_SET); 144 ch = readb_relaxed(port->membase [all...] |
H A D | fsl_linflexuart.c | 147 ier = readl(port->membase + LINIER); 149 writel(ier, port->membase + LINIER); 156 ier = readl(port->membase + LINIER); 157 writel(ier & ~LINFLEXD_LINIER_DRIE, port->membase + LINIER); 164 writeb(c, sport->membase + BDRL); 167 while (((status = readl(sport->membase + UARTSR)) & 172 writel(status | LINFLEXD_UARTSR_DTFTFF, sport->membase + UARTSR); 196 ier = readl(port->membase + LINIER); 197 writel(ier | LINFLEXD_LINIER_DTIE, port->membase + LINIER); 235 status = readl(sport->membase [all...] |
H A D | men_z135_uart.c | 145 reg = ioread32(port->membase + addr); 147 iowrite32(reg, port->membase + addr); 167 reg = ioread32(port->membase + addr); 169 iowrite32(reg, port->membase + addr); 228 stat_reg = ioread32(port->membase + MEN_Z135_STAT_REG); 271 memcpy_fromio(uart->rxbuf, port->membase + MEN_Z135_RX_RAM, room); 274 iowrite32(room, port->membase + MEN_Z135_RX_CTRL); 320 wptr = ioread32(port->membase + MEN_Z135_TX_CTRL); 354 memcpy_toio(port->membase + MEN_Z135_TX_RAM, &xmit->buf[xmit->tail], n); 355 iowrite32(n & 0x3ff, port->membase [all...] |
H A D | altera_jtaguart.c | 55 u32 ctl = readl(port->membase + ALTERA_JTAGUART_CONTROL_REG); 81 port->membase + ALTERA_JTAGUART_CONTROL_REG); 88 port->membase + ALTERA_JTAGUART_CONTROL_REG); 95 port->membase + ALTERA_JTAGUART_CONTROL_REG); 116 while ((status = readl(port->membase + ALTERA_JTAGUART_DATA_REG)) & 138 writel(ch, port->membase + ALTERA_JTAGUART_DATA_REG), 147 isr = (readl(port->membase + ALTERA_JTAGUART_CONTROL_REG) >> 167 writel(0, port->membase + ALTERA_JTAGUART_CONTROL_REG); 188 port->membase + ALTERA_JTAGUART_CONTROL_REG); 204 port->membase [all...] |
H A D | liteuart.c | 81 litex_write8(port->membase + OFF_EV_ENABLE, uart->irq_reg); 104 unsigned char __iomem *membase = port->membase; local 107 while (!litex_read8(membase + OFF_RXEMPTY)) { 108 ch = litex_read8(membase + OFF_RXTX); 112 litex_write8(membase + OFF_EV_PENDING, EV_RX); 127 !litex_read8(port->membase + OFF_TXFULL), 128 litex_write8(port->membase + OFF_RXTX, ch)); 143 isr = litex_read8(port->membase + OFF_EV_PENDING) & uart->irq_reg; 165 if (!litex_read8(port->membase [all...] |
H A D | lantiq.c | 144 u32 fstat = __raw_readl(port->membase + LTQ_ASC_FSTAT); 159 writeb(ch, port->membase + LTQ_ASC_TBUF)); 167 __raw_writel(ASCWHBSTATE_CLRREN, port->membase + LTQ_ASC_WHBSTATE); 176 fifocnt = __raw_readl(port->membase + LTQ_ASC_FSTAT) & 180 ch = readb(port->membase + LTQ_ASC_RBUF); 181 rsr = (__raw_readl(port->membase + LTQ_ASC_STATE) 194 port->membase + LTQ_ASC_WHBSTATE); 198 port->membase + LTQ_ASC_WHBSTATE); 203 port->membase + LTQ_ASC_WHBSTATE); 240 __raw_writel(ASC_IRNCR_TIR, port->membase [all...] |
/linux-master/arch/mips/ralink/ |
H A D | cevt-rt3352.c | 33 void __iomem *membase; member in struct:systick_device 49 count = ioread32(sdev->membase + SYSTICK_COUNT); 51 iowrite32(count, sdev->membase + SYSTICK_COMPARE); 94 iowrite32(0, systick.membase + SYSTICK_CONFIG); 114 systick.membase + SYSTICK_CONFIG); 123 systick.membase = of_iomap(np, 0); 124 if (!systick.membase) 139 ret = clocksource_mmio_init(systick.membase + SYSTICK_COUNT, np->name,
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/linux-master/arch/arm/plat-orion/include/plat/ |
H A D | common.h | 17 void __init orion_uart0_init(void __iomem *membase, 22 void __init orion_uart1_init(void __iomem *membase, 27 void __init orion_uart2_init(void __iomem *membase, 32 void __init orion_uart3_init(void __iomem *membase,
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/linux-master/drivers/net/mdio/ |
H A D | mdio-hisi-femac.c | 25 void __iomem *membase; member in struct:hisi_femac_mdio_data 32 return readl_poll_timeout(data->membase + MDIO_RWCTRL, 46 data->membase + MDIO_RWCTRL); 52 return readl(data->membase + MDIO_RO_DATA) & 0xFFFF; 67 data->membase + MDIO_RWCTRL); 90 data->membase = devm_platform_ioremap_resource(pdev, 0); 91 if (IS_ERR(data->membase)) { 92 ret = PTR_ERR(data->membase);
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/linux-master/arch/arm/kernel/ |
H A D | isa.c | 21 .procname = "membase", 44 register_isa_ports(unsigned int membase, unsigned int portbase, unsigned int portshift) argument 46 isa_membase = membase;
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/linux-master/drivers/misc/ |
H A D | vcpu_stall_detector.c | 36 void __iomem *membase; member in struct:vcpu_stall_detect_config 51 (void __iomem *)(vcpu_stall_config.membase + \ 137 void __iomem *membase; local 147 membase = devm_platform_get_and_ioremap_resource(pdev, 0, &r); 148 if (IS_ERR(membase)) { 150 return PTR_ERR(membase); 170 .membase = membase,
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/linux-master/drivers/input/keyboard/ |
H A D | locomokbd.c | 72 static inline void locomokbd_charge_all(unsigned long membase) argument 74 locomo_writel(0x00FF, membase + LOCOMO_KSC); 77 static inline void locomokbd_activate_all(unsigned long membase) argument 81 locomo_writel(0, membase + LOCOMO_KSC); 82 r = locomo_readl(membase + LOCOMO_KIC); 84 locomo_writel(r, membase + LOCOMO_KIC); 87 static inline void locomokbd_activate_col(unsigned long membase, int col) argument 94 locomo_writel(nbset, membase + LOCOMO_KSC); 97 static inline void locomokbd_reset_col(unsigned long membase, int col) argument 102 locomo_writel(nbset, membase 117 unsigned long membase = locomokbd->base; local [all...] |
/linux-master/drivers/clk/x86/ |
H A D | clk-cgu.c | 30 lgm_set_clk_val(ctx->membase, list->div_off, list->div_shift, 46 val = lgm_get_clk_val(mux->membase, mux->reg, mux->shift, 60 lgm_set_clk_val(mux->membase, mux->reg, mux->shift, 104 mux->membase = ctx->membase; 117 lgm_set_clk_val(mux->membase, reg, shift, width, list->mux_val); 128 val = lgm_get_clk_val(divider->membase, divider->reg, 157 lgm_set_clk_val(divider->membase, divider->reg, 168 lgm_set_clk_val(div->membase, div->reg, div->shift_gate, 217 div->membase [all...] |
H A D | clk-cgu.h | 16 struct regmap *membase; member in struct:lgm_clk_mux 25 struct regmap *membase; member in struct:lgm_clk_divider 37 struct regmap *membase; member in struct:lgm_clk_ddiv 54 struct regmap *membase; member in struct:lgm_clk_gate 71 * @membase: IO mem base address for CGU. 77 struct regmap *membase; member in struct:lgm_clk_provider 91 struct regmap *membase; member in struct:lgm_clk_pll 300 static inline void lgm_set_clk_val(struct regmap *membase, u32 reg, argument 305 regmap_update_bits(membase, reg, mask, set_val << shift); 308 static inline u32 lgm_get_clk_val(struct regmap *membase, u3 argument [all...] |
/linux-master/drivers/i2c/busses/ |
H A D | i2c-uniphier-f.c | 81 void __iomem *membase; member in struct:uniphier_fi2c_priv 109 writel(*priv->buf++, priv->membase + UNIPHIER_FI2C_DTTX); 123 *priv->buf++ = readl(priv->membase + UNIPHIER_FI2C_DTRX); 130 writel(priv->enabled_irqs, priv->membase + UNIPHIER_FI2C_IE); 136 writel(mask, priv->membase + UNIPHIER_FI2C_IC); 144 priv->membase + UNIPHIER_FI2C_CR); 154 irq_status = readl(priv->membase + UNIPHIER_FI2C_INT); 213 priv->membase + UNIPHIER_FI2C_CR); 254 writel(0, priv->membase + UNIPHIER_FI2C_TBC); 257 priv->membase [all...] |
/linux-master/drivers/net/ethernet/sfc/falcon/ |
H A D | io.h | 70 __raw_writeq((__force u64)value, efx->membase + reg); 74 return (__force __le64)__raw_readq(efx->membase + reg); 81 __raw_writel((__force u32)value, efx->membase + reg); 85 return (__force __le32)__raw_readl(efx->membase + reg); 112 static inline void ef4_sram_writeq(struct ef4_nic *efx, void __iomem *membase, argument 124 __raw_writeq((__force u64)value->u64[0], membase + addr); 126 __raw_writel((__force u32)value->u32[0], membase + addr); 127 __raw_writel((__force u32)value->u32[1], membase + addr + 4); 163 static inline void ef4_sram_readq(struct ef4_nic *efx, void __iomem *membase, argument 171 value->u64[0] = (__force __le64)__raw_readq(membase [all...] |
/linux-master/drivers/pinctrl/ |
H A D | pinctrl-equilibrium.h | 84 * @membase: base address of the pin bank register. 91 void __iomem *membase; member in struct:eqbr_pin_bank 105 * @membase: base address of the gpio controller. 114 void __iomem *membase; member in struct:eqbr_gpio_ctrl 125 * @membase: base address of pin controller 136 void __iomem *membase; member in struct:eqbr_pinctrl_drv_data
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/linux-master/drivers/net/ethernet/sfc/siena/ |
H A D | io.h | 87 __raw_writeq((__force u64)value, efx->membase + reg); 91 return (__force __le64)__raw_readq(efx->membase + reg); 98 __raw_writel((__force u32)value, efx->membase + reg); 102 return (__force __le32)__raw_readl(efx->membase + reg); 129 static inline void efx_sram_writeq(struct efx_nic *efx, void __iomem *membase, argument 141 __raw_writeq((__force u64)value->u64[0], membase + addr); 143 __raw_writel((__force u32)value->u32[0], membase + addr); 144 __raw_writel((__force u32)value->u32[1], membase + addr + 4); 180 static inline void efx_sram_readq(struct efx_nic *efx, void __iomem *membase, argument 188 value->u64[0] = (__force __le64)__raw_readq(membase [all...] |
/linux-master/drivers/tty/serial/8250/ |
H A D | 8250_uniphier.c | 43 if (!device->port.membase) 92 return (readl(p->membase + offset) >> valshift) & 0xff; 123 writel(value, p->membase + offset); 135 tmp = readl(p->membase + offset); 138 writel(tmp, p->membase + offset); 150 return readl(up->port.membase + UNIPHIER_UART_DLR); 155 writel(value, up->port.membase + UNIPHIER_UART_DLR); 164 void __iomem *membase; local 173 membase = devm_ioremap(dev, regs->start, resource_size(regs)); 174 if (!membase) [all...] |
H A D | 8250_pci1xxxx.c | 141 void __iomem *membase; member in struct:pci1xxxx_8250 154 writel(UART_SYSLOCK, port->membase + UART_SYSLOCK_REG); 155 return readl(port->membase + UART_SYSLOCK_REG); 170 writel(0x0, port->membase + UART_SYSLOCK_REG); 249 writel(UART_BIT_DIVISOR_8, port->membase + FRAC_DIV_CFG_REG); 251 writel(UART_BIT_DIVISOR_16, port->membase + FRAC_DIV_CFG_REG); 254 port->membase + UART_BAUD_CLK_DIVISOR_REG); 268 frac_div = readl(port->membase + FRAC_DIV_CFG_REG); 286 clock_div = readl(port->membase + UART_BAUD_CLK_DIVISOR_REG); 303 writel(mode_cfg, port->membase [all...] |
/linux-master/drivers/char/hw_random/ |
H A D | geode-rng.c | 56 void __iomem *membase; member in struct:amd_geode_priv 62 void __iomem *mem = priv->membase; 72 void __iomem *mem = priv->membase; 125 priv->membase = mem; 152 iounmap(priv->membase);
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