tty/serial/digicolor-usart.c

85 	return !!(readb_relaxed(port->membase + UA_STATUS_FIFO) &
91 	return !!(readb_relaxed(port->membase + UA_STATUS_FIFO) &
97 	u8 int_enable = readb_relaxed(port->membase + UA_INT_ENABLE);
100 	writeb_relaxed(int_enable, port->membase + UA_INT_ENABLE);
105 	u8 int_enable = readb_relaxed(port->membase + UA_INT_ENABLE);
108 	writeb_relaxed(int_enable, port->membase + UA_INT_ENABLE);
113 	u8 int_enable = readb_relaxed(port->membase + UA_INT_ENABLE);
116 	writeb_relaxed(int_enable, port->membase + UA_INT_ENABLE);
127 		writeb_relaxed(UA_INT_RX, dp->port.membase + UA_INTFLAG_SET);
144 		ch = readb_relaxed(port->membase + UA_EMI_REC);
145 		status = readb_relaxed(port->membase + UA_STATUS);
192 		writeb_relaxed(port->x_char, port->membase + UA_EMI_REC);
204 		writeb(c, port->membase + UA_EMI_REC);
220 	u8 int_status = readb_relaxed(port->membase + UA_INT_STATUS);
223 		       port->membase + UA_INTFLAG_CLEAR);
235 	u8 status = readb_relaxed(port->membase + UA_STATUS);
258 	writeb_relaxed(UA_ENABLE_ENABLE, port->membase + UA_ENABLE);
259 	writeb_relaxed(UA_CONTROL_SOFT_RESET, port->membase + UA_CONTROL);
260 	writeb_relaxed(0, port->membase + UA_CONTROL);
264 		       port->membase + UA_CONFIG_FIFO);
266 		       port->membase + UA_STATUS_FIFO);
268 		       port->membase + UA_CONTROL);
270 		       port->membase + UA_INT_ENABLE);
282 	writeb_relaxed(0, port->membase + UA_ENABLE);
340 	writeb_relaxed(config, port->membase + UA_CONFIG);
341 	writeb_relaxed(divisor & 0xff, port->membase + UA_HBAUD_LO);
342 	writeb_relaxed(divisor >> 8, port->membase + UA_HBAUD_HI);
389 	writeb_relaxed(ch, port->membase + UA_EMI_REC);
412 		status = readb_relaxed(port->membase + UA_STATUS);
474 	dp->port.membase = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
475 	if (IS_ERR(dp->port.membase))
476 		return PTR_ERR(dp->port.membase);